JPS6330033U - - Google Patents
Info
- Publication number
- JPS6330033U JPS6330033U JP12334986U JP12334986U JPS6330033U JP S6330033 U JPS6330033 U JP S6330033U JP 12334986 U JP12334986 U JP 12334986U JP 12334986 U JP12334986 U JP 12334986U JP S6330033 U JPS6330033 U JP S6330033U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- conversion
- converter
- pass filter
- fcut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は本考案の他の一実施例の構成を示
すブロツク図、第３図は従来例を示すブロツク図
である。
１１……Ｄ／Ａ変換周辺回路、１２……クロツ
ク発生回路、１３……バイナリーカウンタ、１４
……ＲＯＭ、１５……Ｄ／Ａコンバータ、１６…
…ローパスフイルタ、１７……連動軸、２２，３
３，３４……可変抵抗。
FIG. 1 is a block diagram showing the structure of one embodiment of the present invention, FIG. 2 is a block diagram showing the structure of another embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example. 11...D/A conversion peripheral circuit, 12...Clock generation circuit, 13...Binary counter, 14
...ROM, 15...D/A converter, 16...
...Low pass filter, 17...Interlocking shaft, 22,3
3, 34...variable resistance.
Claims (1)
コンバータと、このコンバータの変換速度を決定
するクロツクを発生するクロツク発生回路と、変
換前又は変換後のアナログ信号から不要な高域成
分を除去するローパスフイルタと、前記クロツク
発生回路のクロツク周波数ｆｃｋ及び前記ローパ
スフイルタの遮断周波数ｆｃｕｔとをｆｃｕｔ≦
ｆｃｋ／２の関係を保つように変える連動変化手
段とを備えたデイジタル・アナログ間変換周辺回
路。 A converter that converts between a digital signal and an analog signal, a clock generation circuit that generates a clock that determines the conversion speed of this converter, and a low-pass filter that removes unnecessary high-frequency components from the analog signal before or after conversion. The clock frequency fck of the clock generation circuit and the cutoff frequency fcut of the low-pass filter are set such that fcut≦
A digital-to-analog conversion peripheral circuit comprising interlocking change means for changing so as to maintain the relationship of fck/2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12334986U JPS6330033U (en) | 1986-08-13 | 1986-08-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12334986U JPS6330033U (en) | 1986-08-13 | 1986-08-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6330033U true JPS6330033U (en) | 1988-02-27 |
Family
ID=31014374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12334986U Pending JPS6330033U (en) | 1986-08-13 | 1986-08-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6330033U (en) |
-
1986
- 1986-08-13 JP JP12334986U patent/JPS6330033U/ja active Pending
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