JPS63299515A - Pulse counting circuit - Google Patents

Abstract

PURPOSE:To control the counting action of a counter at the accurate time intervals by using a control circuit for ON/OFF actions of a switch circuit, a timepiece signal generating means which controls said control circuit and a CPU which functions just to give a cue to the control circuit for its actions. CONSTITUTION:A switch circuit 2 is provided to control the input of the pulse signal to a counter 3 together with a means which produces the timepiece signals at accurate time intervals, and a control circuit 8 which controls the circuit 2 so that the pulse signals are supplied to the counter 3 for a period of time set by the timepiece signal generating circuit. A CPU 4 counts the timepiece signals and gives an instruction to the circuit 8 to supply the pulse signal to the circuit 8 when the count value of the timepiece signals reaches a prescribed level. Thus a starting cue of the circuit 8 is received from the CPU 4 and the time needed for subsequent counting actions is processed by hardware. Then the pulse signals are counted at accurate time intervals.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse counter circuit that counts pulse signals, and more particularly, the present invention relates to a pulse counter circuit that counts pulse signals. The present invention relates to a pulse counter circuit that counts the number of pulse signals in a pulse counter.

[Technical Background of the Invention] In measuring instruments and the like, it is widely practiced to convert the measured value into a digital signal, for example, by A/D conversion, and to display the measured value as a readable measurement result by the number of pulse signals. The reading device for counting the number of pulse signals includes, for example, a counter that constantly counts the signal to be measured, and a clock signal that is sent at certain regular intervals to a central processing unit (hereinafter referred to as CPU) composed of a microcomputer or the like. Some devices are equipped with an oscillator, and the CPU reads the value of the counter at that time when a control signal is applied.

[Problems to be Solved by the Invention] Although the above-described configuration is simple, there is a drawback that the timing of data acquisition is not always constant because it depends on the software of the CPU. Therefore, a latch circuit composed of a flip-flop circuit or the like is interposed between the counter and the CPU, and the signal from the oscillator is also applied to this latch circuit, and each time the signal from the oscillator is applied, the latch circuit By latching the counter value, the timing at which data is latched is always constant, and the counter value can be captured at accurate time intervals. However, when it is desired to increase the number of bits of data to be taken in, a latch circuit is required for each bit, so a large number of latch circuits are required, and the overall configuration becomes complicated and large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse counting circuit that can count pulse signals at accurate time intervals with a simple configuration.

[Means for Solving the Problems] The present invention provides a pulse count circuit in which a pulse signal, which is a signal to be measured, is counted by a counter at time intervals controlled by a CPU, and a switch that controls input of the pulse signal to the counter. A clock signal generating means that generates a clock signal at accurate time intervals, and a control circuit that controls a switch circuit to input a pulse signal to a counter for a time set by the clock signal generating means. , CI? U is characterized in that it counts the clock signal and, when a predetermined count value is reached, instructs the control circuit to input a pulse signal to the counter.

[Operation] The pulse signal of the signal to be measured is constantly applied to the switch circuit, and the on/off operation of this switch circuit is controlled by the control circuit. This control circuit is controlled by a CPU that counts a precisely time-controlled time signal from the time signal generating means and a signal representing the time when a predetermined value is reached.

Therefore, the trigger for controlling the control circuit is given by the CPU, and the time required for subsequent counting is processed by hardware, so that pulse signals can be counted at accurate time intervals.

[Embodiment] Hereinafter, an embodiment of the pulse count circuit of the present invention shown in the drawings will be explained. A pulse signal from the signal under test generator 1 is applied to the counter 3 via the switch circuit 2, and the number of pulses is It is counted and the data is input to the CPU 4. The CPU 4 is connected to set the frequency dividing period of a frequency divider 6 that divides the output from an oscillator 5 that continuously oscillates at a precise frequency, and also uses an internal counter 7 to set the frequency division period of the frequency divider 6. When the pulses are counted and, for example, an initial value is set to a high level, a low level pulse is outputted via the CPU 4 when a predetermined value set by the software of the CPU 4 is reached. The output of frequency divider 6 is C
The PU 4 and the frequency divider 6 are connected to a control circuit 8 that controls on/off of the switch circuit 2 .

The switch circuit 2 is composed of a two-man operated OR gate 11, one input side of which is connected to the output side of the signal under test generator 1,
Its output is connected to the input of the counter 3.

The control circuit 8 is composed of a two-man power OR gate 12 and a D-type flip-flop (hereinafter referred to as an FF circuit) 13, and one input side of the OR gate 12 is configured such that the output pulse of the internal counter 7 of the CPU 4 is applied. The output side is connected to the data input terminal (D
ATA).

The clock input terminal (CLOCK) of the FF circuit 13 is connected to the output side of the frequency divider 6, its ζ output terminal is connected to the other input side of the OR gate 11, and the ζ output terminal is connected to the other input side of the OR gate 12. It is connected.

Next, the operation of this pulse count circuit is shown in Figures 2 and 3.
This will be explained with figures. The pulse signal generated by the signal under test generator 1 is applied to one input side of the OR gate 11 of the switch circuit 2 . On the other hand, the oscillator 5 continuously oscillates at a precise frequency, and its oscillation output is sent to the frequency divider 6.
is applied to

The frequency divider 6 outputs one pulse signal for each constant frequency division period set by the CPU 4. The output pulse signal of the frequency divider 6 is applied to the CPU 4 and the clock input terminal of the FF circuit 13 of the control circuit 8.

The CPU 4 sets the frequency division number of the frequency divider 6 and counts the output from the frequency divider 6 using an internal counter 7.
When a predetermined count value is reached, a low level signal (hereinafter referred to as "hereinafter") is sent to the OR gate 12.

Since the CPU manages the counting process of the signals from the frequency divider 6 using software and generates the output, the time for generating the signal from the frequency divider 6 and the signal generation from the CPU 4 to the OR gate 12 depends on the software execution time, etc. The relationship is not constant.

In the initial state, the CPU 4 sends a high level signal (hereinafter referred to as I) to the OR gate 12 because the signal from the frequency divider 6 does not reach a predetermined count value. Therefore, the FF circuit 13 maintains its state with the ζ output set to H and the ζ output terminal set to L based on the signal from the frequency divider 6. Since the OR gate 11 to which the ζ output of the FF circuit 13 is sent is fixed at H, the counter 3 does not perform a counting operation. When the signal generation from the frequency divider 6 reaches a predetermined count value, the CPU 4 sends L to the OR gate 12. After sending out the L signal, the CPU 4 again converts the output to the OR gate 12 to H based on the signal from the frequency divider 6. When the output of the CPU 4 to the OR gate 12 becomes L, the ζ output of the FF circuit 13 becomes L, and the OR gate 12 sends L to the FF circuit 13. In this state, when the signal from the frequency divider 6 is input, the FF circuit 1
3 inverts the output, and the ζ output becomes L◇ζ output H. FF
When the ζ output of the circuit 13 becomes H, the output of the OR gate 12 also becomes H, and the next signal from the frequency divider 6 causes the ζ output to become H and the ζ output to become L again. The CPU 4 generates an L output to the OR gate 12 as described above, and then changes it to H again by the next signal from the 1 frequency divider 6, but this signal from the frequency divider 6 also causes the FF circuit 13 to output ζ as described above. The I(, ζ outputs have changed to L. The FF circuit 13 maintains its state again by the H signal from the CPU 4 to the OR gate 12.

In this way, the L output of the ζ output of the FF circuit 13 and the
Although the signal generation by the constant signal generator 1 is controlled by the CPU 4, the generation time is equal to the time determined by the oscillator 5 and the frequency divider 6.

When the ζ output of the FF circuit 13 becomes L, the OR gate 11 generates an output that changes in synchronization with the signal of the signal under test generator 1, and this output is counted by a counter. Therefore, the count value of this counter is a highly accurate constant time count value determined by the oscillator 5 and frequency divider 6, regardless of the software execution time of the CPU 4, etc.

[Effects of the Invention] As described above, in the pulse count circuit of the present invention, the counting operation time of the counter that counts the signal under test is determined by the switching circuit, the control circuit that controls the on/off operation of the switch circuit, and the control circuit that controls the on/off operation of the switch circuit. The clock signal generating means generates a clock signal for regulating the operation, and CI)U only provides a trigger for the operation of the control circuit, so the counter counts at precise time intervals. can be controlled. The trigger for turning on and off the switch circuit can be adjusted by the CPU.

The counting operation interval of the counter can be set by software of the CPU. Further, if the frequency division period of the frequency divider can be adjusted by the CPU as in the above embodiment, the output interval of the output signal can also be set arbitrarily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a timing chart, and FIG. 3 is a flowchart. In the drawing, 1 is a signal generation unit to be measured, 2 is a switch circuit, 3 is a counter, 4 is a CPU, 5 is an oscillator, 6 is a frequency divider, 7 is an internal counter, 8 is a control circuit, 11.12 is an OR gate, 13 is an FF circuit. Patent applicant Nichili! Denki Co., Ltd. Agent Patent Attorney Takuya OharaFigure 2 (a)ゞJ'l! i% 1 book---111---
-----------Output of book generator 1 (b) Output of frequency division H6 (c) Output of CPU 4 (d) Output of Q (e) Output of OR gate 12 (f) Output of Q (g ) Output of OR gate 11 -11←-t'-Q Figure 3

Claims (4)

[Claims] (1) In a pulse counting circuit in which a counter counts a pulse signal, which is a signal to be measured, at time intervals controlled by a central processing unit, a switch circuit that controls the input of the pulse signal to the counter, and a switch circuit that controls the input of the pulse signal to the counter, and a switch circuit that controls the input of the pulse signal to the counter, and and a control circuit that controls the switch circuit so as to input the pulse signal to the counter for a time set by the clock signal generating means, A pulse counting circuit, wherein the device counts the time signal and instructs the control circuit to input the pulse signal to the counter when a predetermined count value is reached. (2) In claim 1, when the central processing unit reaches the predetermined count value, the central processing unit controls the switch circuit via the control circuit until counting the next time signal. A pulse counting circuit characterized by performing a counting operation. (3) The pulse counting circuit according to claim 1, wherein the time signal generating means is comprised of an oscillator and a frequency divider that divides the output signal of the oscillator at predetermined intervals. . (4) In claim 1, the control circuit is constituted by a D-type flip-flop circuit, and the clock input terminal thereof is configured such that the clock signal of the clock signal generating means is applied and the data thereof is A pulse counting circuit characterized in that an input terminal is connected to receive a signal representing the count value of the central processing unit, and the switch circuit is controlled by the output of the Q output terminal.