JPS63299514A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63299514A JPS63299514A JP62135040A JP13504087A JPS63299514A JP S63299514 A JPS63299514 A JP S63299514A JP 62135040 A JP62135040 A JP 62135040A JP 13504087 A JP13504087 A JP 13504087A JP S63299514 A JPS63299514 A JP S63299514A
- Authority
- JP
- Japan
- Prior art keywords
- dfet
- field effect
- source
- threshold voltage
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000005669 field effect Effects 0.000 claims abstract description 20
- 230000007423 decrease Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241001024304 Mino Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＧａＡｓ等の化合物半導体基板上に形成され
る電界効果トランジスタを用いた半導体集積回路に利用
される。特に、ＤＣＦＬ （ＤｉｒｅｃｔＣｏｕｐｌｅ
ｄ ＦＥＴ Ｌｏｇｉｃ）と呼ばれる論理回路を用い
た半導体集積回路に利用される。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to a semiconductor integrated circuit using a field effect transistor formed on a compound semiconductor substrate such as GaAs. In particular, DCFL (Direct Couple
It is used in semiconductor integrated circuits using a logic circuit called dFET Logic.
従来の技術
化合物半導体基板上に形成される電界効果トランジスタ
を用いた半導体集積回路には、種々の論理回路が用いら
れている。特に、ＤＣＦＬはその低電力性と高速性から
広く用いられている論理回路である。2. Description of the Related Art Various logic circuits are used in semiconductor integrated circuits using field effect transistors formed on compound semiconductor substrates. In particular, DCFL is a logic circuit that is widely used because of its low power consumption and high speed.
第２図に、ＤＣＦＬによるインバータの回路図？示す。Figure 2 shows the circuit diagram of an inverter using DCFL. show.
図中において、Ｔ１は負荷抵抗体となるデプレッション
型電界効果トランジスタ（以下、ＤＦＥＴと略す）であ
る。さらに、Ｔ２はスイッチングを行うエンハンスメン
ト型電界効果トランジスタ（以下、ＥＦＥＴと略す）で
ある。ＤＦＥＴ、Ｔ１ のゲートとソースは短絡され
て、ＥＦＥＴ 、 Ｔ ２ のドレインに接続され
ている。さらに、ＤＦＥＴ 、Ｔ１のドレインは、電源
ｖＤＤ、１に接続されている。ＥＦＥＴ、Ｔ２ の
ソースは接地されている。In the figure, T1 is a depletion field effect transistor (hereinafter abbreviated as DFET) serving as a load resistor. Furthermore, T2 is an enhancement type field effect transistor (hereinafter abbreviated as EFET) that performs switching. The gate and source of DFET, T1, are shorted and connected to the drain of EFET, T2. Furthermore, the drain of DFET, T1, is connected to the power supply vDD,1. The source of EFET, T2, is grounded.
インバータの入力は、ＥＦＥＴ、Ｔ２ のゲート、
２である。又、出力はＥＦＥＴ、Ｔ２ のドレイン
、３である。The input of the inverter is EFET, the gate of T2,
It is 2. Also, the output is the drain of EFET, T2, 3.
さて、ＤＣＦＬにおいてゲート遅延時間は、前記ＤＦＥ
ＴとＥＦＥＴの電流駆動能力によシ決定されている。Now, in the DCFL, the gate delay time is
It is determined by T and the current drive capability of the EFET.
周知のように、ＤＦＥＴとＥＦＥＴの電流駆動能力の比
が大きくなる程ゲート遅延時間は小ざくなる。As is well known, the gate delay time decreases as the ratio of the current drive capabilities of the DFET and EFET increases.
しかし、同時に論理振幅が小さくなシ、ノイズマージン
が小さくなる。逆に、前記電流駆動能力の比が大きくな
ると、ノイズマージンが大きくなるが、ゲート遅延時間
も大きくなる。その結果、前記ＤＦＥＴとＥＦＥＴの電
流駆動能力の比には最適値が存在する。However, at the same time, since the logic amplitude is small, the noise margin becomes small. Conversely, as the ratio of the current drive capabilities increases, the noise margin increases, but the gate delay time also increases. As a result, there is an optimum value for the ratio of current drive capabilities of the DFET and EFET.
ところで、ＤＦ ＥＴとＥＦＥＴ の電流駆動能力は
、主にＦＥＴのしきい電圧により決定される。また、一
般にＥＦＥＴのしきい電圧のバラツキに比べ、ＤＦＥＴ
のしきい電圧のバラツキが大きい。By the way, the current drive capability of DFET and EFET is mainly determined by the threshold voltage of the FET. Additionally, in general, compared to the variation in threshold voltage of EFET, DFET
There are large variations in the threshold voltage.
その結果、従来の技術によるＤＣＦＬは、ＤＦＥＴのし
きい電圧のバラツキにより、ゲート遅延時間とノイズマ
ージンに大きなバラツキが生じていた。As a result, DCFLs according to the prior art have large variations in gate delay time and noise margin due to variations in the threshold voltage of the DFET.
発明が解決しようとする問題点
本発明が解決しようとする問題点は、前記のような従来
技術によるＤＣＦＬＯ問題点である。つまシ、負荷抵抗
体となるＤＦＥＴのしきい電圧のバラツキにより、ゲー
ト遅延時間とノイズマージンに大きなバラツキが生じて
いた事である。その結果、半導体集積回路の動作速度が
遅くなるとか、製造歩留りが低下するという原因となっ
ていた。Problems to be Solved by the Invention The problems to be solved by the present invention are the problems of the DCFLO according to the prior art as described above. Unfortunately, due to variations in the threshold voltage of the DFET that serves as the load resistor, large variations have occurred in gate delay time and noise margin. As a result, the operating speed of the semiconductor integrated circuit becomes slow and the manufacturing yield decreases.
問題点を解決するための手段
本発明による半導体集積回路は、負荷抵抗体となるミノ
界効果トランジスタとスイッチングを行う電界効果トラ
ンジスタを直列に接続して構成される論理回路を用いた
半導体集積回路において、前記負荷抵抗体となる電界効
果トランジスタのソースとゲートが抵抗により接続され
るとともに、該ゲートが前記スイッチングを行う電界効
果トランジスタのドレインに接続されている事を特徴と
する論理回路を少なくとも１個含むものである。Means for Solving the Problems The semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit using a logic circuit configured by connecting in series a mino field effect transistor serving as a load resistor and a field effect transistor performing switching. , at least one logic circuit characterized in that the source and gate of the field effect transistor serving as the load resistor are connected by a resistor, and the gate is connected to the drain of the field effect transistor performing the switching. It includes.
作 用
前記負荷抵抗体となる電界効果トランジスタのソースと
ゲート間に接続される抵抗により、該電界効果トランジ
スタのしきい電圧のノ（ラツキを減少させることかでき
、電流駆動能力のバラツキを減少させることができる。Function: The resistor connected between the source and gate of the field effect transistor, which serves as the load resistor, can reduce the fluctuations in the threshold voltage of the field effect transistor, thereby reducing the fluctuations in current drive capability. be able to.
実施例
第１図に、本発明の一実施例であるインバータの回路図
を示す。図中において、Ｔｓは負荷抵抗体となるＤＦＥ
Ｔである。Ｔ４は、スイッチングを行うＥＦＥＴである
。ＤＦＥＴ 、Ｔｓのソース１１とゲート間に、抵抗、
１２が接続でれている。さらに、ＤＦＥＴ、Ｔｓ
のゲートとＥＦＥＴ、Ｔ４ のドレインが接続され
ている。ＤＦＥＴのドレインは、電源ＶＤＤ、１ａ
に接続されている。ＥＦＥＴのソースは接地されてい
る。インバータの入力はＥＦＥＴのゲート１４である。Embodiment FIG. 1 shows a circuit diagram of an inverter which is an embodiment of the present invention. In the figure, Ts is the DFE serving as a load resistor.
It is T. T4 is an EFET that performs switching. DFET, between the source 11 and gate of Ts, a resistor,
12 is connected. Furthermore, DFET, Ts
The gate of EFET and the drain of T4 are connected. The drain of DFET is connected to the power supply VDD, 1a
It is connected to the. The source of the EFET is grounded. The input of the inverter is the gate 14 of the EFET.
インバータの出力は、ＥＦＥＴのドレイン、１５である
。The output of the inverter is the drain of the EFET, 15.
さて、ＤＦＥＴのソースとゲート間を抵抗で接続するこ
とにより、ＤＦＥＴのしきい電圧の）くラツキによるＤ
ＦＥＴの電流駆動能力のノくラツキが低減される訳であ
るが、その理由を以下に述べる。Now, by connecting the source and gate of the DFET with a resistor, the D
The fluctuations in the current drive capability of the FET are reduced, and the reason for this will be described below.
今、ＤＦＥＴのしきい電圧が設計中心より負側となった
場合を考える。従来技術では、ＤＦ ＥＴに流れる電流
はしきい電圧の２乗に比例して増加した。Now, consider a case where the threshold voltage of the DFET is on the negative side from the design center. In the prior art, the current flowing through the DFET increased in proportion to the square of the threshold voltage.
しかし、本発明では、ＤＦＥＴのソースに抵抗が接続さ
れている為に、ＤＦＥＴに流れる電流が増加するとリー
ス電位が上昇する。その結果、ＤＦＥＴに流れる電流の
増加は、従来技術に比べて大巾に小さくなる訳である。However, in the present invention, since a resistor is connected to the source of the DFET, the lease potential increases as the current flowing through the DFET increases. As a result, the increase in current flowing through the DFET is significantly smaller than in the prior art.
逆に、ＤＦＥＴのしきい電圧が設計中心よシ正側となっ
た場合を考える。従来技術では、ＤＦＥＴに流れる電流
は、しきい電圧の２乗に比例して減少する。しかし、本
発明では、ＤＦＥＴに流れる電流が減少するとソース電
位が下降する。その結果、ＤＦＥＴに流れる電流の減少
は、従来技術に比べて大巾に小さくなる。Conversely, consider a case where the threshold voltage of the DFET is on the positive side of the design center. In the prior art, the current flowing through the DFET decreases in proportion to the square of the threshold voltage. However, in the present invention, when the current flowing through the DFET decreases, the source potential decreases. As a result, the reduction in current flowing through the DFET is much smaller than in the prior art.
以上の説明で明らかなように、本発明によればＤＦＥＴ
のしきい電圧が設計中心からのバラツキが生じても、Ｄ
ＦＥＴのソースに接続された抵抗によりソース電位が変
化し、ＤＦＥＴに流れる電流の変化が抑制される。その
結果、ＤＦＥＴのしきい電圧のバラツキにより生じてい
たＤＦＥＴの電流駆動能力のバラツキが抑制される訳で
ある。As is clear from the above explanation, according to the present invention, the DFET
Even if the threshold voltage varies from the design center, D
A resistor connected to the source of the FET changes the source potential, suppressing changes in the current flowing through the DFET. As a result, variations in the current drive capability of the DFET caused by variations in the threshold voltage of the DFET are suppressed.
なお、本発明ではＤＣＦＬによるインバータのみについ
て説明したが、スイッチングを行うＥＦ ＥＴを並列に
接続したＮＯＲ回路など他の回路にも適用できることは
自明である。In the present invention, only an inverter using a DCFL has been described, but it is obvious that the present invention can be applied to other circuits such as a NOR circuit in which switching EFETs are connected in parallel.
発明の効果
上述のように本発明によれば、負荷抵抗となるＤＦＥＴ
のしきい電圧のバラツキにより、ゲート遅延時間とノイ
ズマージンに大きなバラツキが生じるという従来技術に
よるＤＣＦＬの問題点が解決された。その結果、ＤＣＦ
Ｌによる半導体集積回路の動作速度が向上し、製造歩留
りが大巾に改善された。Effects of the Invention As described above, according to the present invention, the DFET serving as a load resistance
This solves the problem of conventional DCFLs in which large variations in gate delay time and noise margin occur due to variations in threshold voltage. As a result, DCF
The operating speed of semiconductor integrated circuits using L has been improved, and manufacturing yields have been greatly improved.
第１図は本発明によるＤＣＦＬのインバータの回路図、
第２図は従来技術によるＤＣＦＬのインバータの回路図
である。
Ｔ１．Ｔ３・・・・・・負荷抵抗となる電界効果トラン
ジスタ、Ｔ２．Ｔ４・・・・・・スイッチングを行う電
界効果トランジスタ、１．１３・・・・・・電源ＶＤＤ
、２゜１４・・・・・・インバータの入力、３，１５・
・・・・・インノ（−夕の出力、１１・・・・・・ＤＦ
ＥＴのソース、１２・・・・・・本発明の特徴である抵
抗。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１１２１
第２図
／Ｉ−ＤＦＥ７のソース
／２−ｉ氏抗
／３−ＶＤＤ
！４−・・入力
ｌ５−−一エカ
、７３−Ｄ Ｆ ＥＴ
Ｔ４−−・日ＦＥＴ
／ −−Ｖｏ。
？−人力
３−一一已カ
Ｔ、−１）ＦＥＴ
Ｔこ− ＥＦＥＴFIG. 1 is a circuit diagram of a DCFL inverter according to the present invention,
FIG. 2 is a circuit diagram of a DCFL inverter according to the prior art. T1. T3... Field effect transistor serving as a load resistance, T2. T4... Field effect transistor for switching, 1.13... Power supply VDD
, 2゜14... Inverter input, 3,15.
...Inno (-evening output, 11...DF
Source of ET, 12...Resistance which is a feature of the present invention. Name of agent: Patent attorney Toshio Nakao and 1 other person
1121 Figure 2/I-DFE7 source/2-i Mr. Anti/3-VDD! 4--Input l5--Eka, 73-D FET T4--Day FET/--Vo. ? -Manpower 3-11 T, -1) FET T- EFET
Claims (1)
を行う電界効果トランジスタを直列に接続して構成され
る論理回路を用いた半導体集積回路であって、前記負荷
抵抗体となる電界効果トランジスタのソースとゲートが
抵抗を介して接続されるとともに、前記ゲートが前記ス
イッチングを行う電界効果トランジスタのドレインに接
続されていることを特徴とする論理回路を少なくとも１
個含む半導体集積回路。A semiconductor integrated circuit using a logic circuit configured by connecting a field effect transistor serving as a load resistor and a field effect transistor performing switching in series, the source and gate of the field effect transistor serving as the load resistor being connected in series. At least one logic circuit is connected through a resistor, and the gate is connected to the drain of the field effect transistor that performs the switching.
Semiconductor integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62135040A JPS63299514A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62135040A JPS63299514A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63299514A true JPS63299514A (en) | 1988-12-07 |
Family
ID=15142536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62135040A Pending JPS63299514A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63299514A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8933497B2 (en) | 2009-05-19 | 2015-01-13 | Murata Manufacturing Co., Ltd. | Semiconductor switch device and method of manufacturing semiconductor switch device |
-
1987
- 1987-05-29 JP JP62135040A patent/JPS63299514A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8933497B2 (en) | 2009-05-19 | 2015-01-13 | Murata Manufacturing Co., Ltd. | Semiconductor switch device and method of manufacturing semiconductor switch device |
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