JPS63298800A - Shift register - Google Patents

Abstract

PURPOSE:To reduce the number of gates by providing an output control section leading out an output signal of a register section in response to a prescribed signal from a counter section to eliminate the need for a reset function of a flip-flop. CONSTITUTION:A register section 10 consists of plural flip-flops connected in series and transfers 9 signal D1 inputted to a 1st stage flip-flop sequentially to post-stage flip-flops and an output D0 is obtained from the final-stage flip- flop. A counter section 12 has a reset function and reset by an external signal RS, then a prescribed signal C is outputted after a prescribed number of clock pulses CK are inputted and an output control section introduces a signal Y outputted from the flip-flop of the final stage. Thus, even the length of the register is mode longer, the number of gates required for the reset function is not increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift register that can be reset by an external signal.

[Prior Art] Fig. 4 shows a conventional n-stage shifter 1- with a reset function.
FIG. 3 is a diagram showing a register.

In the figure, the register 40 shown at J3 is composed of n flip-flops with gate terminals connected in series. Each logic flop has an input terminal, an output terminal, and a clock terminal J3.
and a reset terminal, and when a clock pulse is input to the clock terminal, the data input to the input terminal is output from the output terminal. and,
When a signal of "0 level" is input to the reset terminal, the contents of the flip-flop are reset to "0".

The clock terminals of each of the seven lip-flops are commonly connected to an external clock terminal, and a clock signal GK is input to the external clock terminal.

Further, the reset terminals of each of the seven lip flops are commonly connected to an external reset terminal, and the reset signal R8 is input to the external reset terminal.

Data D is input to the input terminal of the flip-flop in the first stage, and data Y is output from the output terminal of the seven flip-flops in the final stage.

First, the contents of all flip-flops in the register 40 are reset to "0" by the reset signal R8. and,
Each time one clock pulse is input, data DI is input one by one from the input terminal, and the data held in each flip-flop is sequentially shifted to the subsequent flip-flop and transferred from the output terminal to the f-data. 1 as Y
output one by one. Therefore, after n (113 rOJs) are output from the output terminal of the axis stage flip-flop, the data DI input to the input terminal is sequentially output from the output terminal.

[Problems to be Solved by the Invention] The flip-flop with a reset terminal used in the shift register has an increased number of gates for reset ii compared to a flip-flop without a reset terminal.

Since the above shift register uses flip-flops with reset terminals for all bits, the number of "C games" increases significantly compared to a shift register without a reset function.

Furthermore, since many set terminals are connected to the external reset terminal, a large load is applied, and the time required for resetting y2 increases.

These phenomena become more pronounced as the register length becomes longer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a shift register in which the number of gates required for a reset function does not increase even when the register length becomes long, and the load on a set terminal does not increase.

[Means for Solving the Problems] A shift register according to the present invention is a shift register that can be started by an external signal, and is composed of a register section, a counter section, and an output control section.

The register section consists of a plurality of 7-slip-flops connected in series, and each time a clock pulse is input, the signal input to the 7-slip-flops in the first stage is sequentially transferred to the 7-slip-flops in the subsequent stage. It is output from a lip-flop.

The counter section has a reset function, and outputs a predetermined signal after being reset by the external signal and after receiving a predetermined number of clock pulses.

The output control section derives the output signal of the register section in response to the predetermined signal from the counter section.

[Operation] In the shift register according to the present invention, first, when the counter section is reset, the output control section enters a state in which it does not derive the output signal of the register section due to the output signal of the counter section. This state is maintained until a predetermined number of clock pulses are input to the counter section. On the other hand, in the register section, each time a clock pulse is input, a signal is input to the flip-flop in the first stage, and the signal held by each flip-flop is sequentially transferred to the 7 flip-flops in the subsequent stage, and the output is output from the final stage. Output from flip-flop.

When a predetermined number of clock pulses are input, a predetermined signal is output from the counter section, whereby the output control section outputs the signal from the final stage flip-flop of the register section.
This will lead to the derivation of the signal.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of a shift register according to the present invention.

This shift register consists of register 10 and decimal counter 1.
2 and a mask gate 14.

The register 10 is made up of n flip-flops connected in series that do not have a reset function.

Each flip-flop has an input terminal, an output terminal, and a clock terminal, and when a clock pulse is input to the input terminal, the data input to the input terminal is output and held from the output terminal. be. Each flip [
A common clock signal CK is input to one clock terminal. Each time a clock pulse is input to this register 10, data is input from the input terminal of the flip-flop in the first stage, and the data held by each flip-flop is sequentially shifted to the seven flip-flops in the succeeding stage. It is output from the output terminal of the flip-flop.

The n-ary counter 12 has a clock terminal, a reset terminal, and an output terminal. rOJ from the output terminal until
A level signal is output, and after n clock pulses are input, a "1" level signal is output. A clock signal GK common to the register 10 is input to the clock terminal of the counter 12.

The mask gate 14 is composed of a two-manual AND gate, and one input terminal of the mask gate 14 receives the output data Do from the register 10, and the other input terminal receives the output signal C from the counter 12. . This mask gate 14 is configured such that the output signal C from the counter 12 is rOJ.
When the output signal C from the counter 12 is at the "1" level, a signal at the "0" level is output, and when the output signal C from the counter 12 is at the "1" level, the output data Do from the register 10 is output. The n-ary counter 12 has a simple circuit configuration in the case of n-2''.
become.

The 2m base counter is not shown in Figure 5. This 2'''-adjustable counter is composed of one 7-lip flop 51 and (i-1) inverters 52, and when the rOJ level reset signal R8 is input, 2''' It outputs a "0" level signal until a pulse is input, and after m clock pulses are input, it outputs a "1j level signal."

Next, the operation of the shift register shown in FIG. 1 will be explained using the timing chart shown in FIG.

First, when the reset signal R8 reaches the rOJ level, the output signal C of the counter 12 becomes the [0] level at its fall. As a result, the output signal Y of the mask gate 14 is also r
It will be OJ level. The output signal C of the counter 12 is kept at 0 level from when the reset signal R8 becomes 10 level until n clock pulses are input. At each time, data Or is input from the input terminal, and the data held by each flip-flop is sequentially shifted to the subsequent flip-flop, and output data Do is input from the output terminal.
is output as However, the output signal C of the counter 12
is at “0” level, the output data Do of the register 10
is not output from mask gate 14, and mask gate 1
The output signal Y of No. 4 maintains the "0" level.

When the nth clock pulse is input, the counter 12
The output signal DC becomes "1" level, and thereafter the mask gate 14 is in a state of transmitting the output data DO of the register 10.

The data DI input to the register 10 immediately after the reset signal T rises from the "0" level to the "1" level is output from the mask gate 14 because it has been shifted to the output terminal of the register 10 at this point. Thereafter, the output data Do of the register 10 is sequentially outputted from the mask gate 14 every time the D-sink pulse is input.

FIG. 2 is a diagram showing a second embodiment of the shift register of the present invention.

This shift register does not have a reset function (n-
1) A register 20 consisting of flip-flops, and (
n-1) Base counter 22 and reset I that controls the output
It is composed of a flip-flop 24 with an M section.

The configurations of the register 20 and counter 22 are similar to those of the register 101t5 and counter 12 in the first embodiment. The flip-flop 24 has an input terminal, an output terminal, a clock terminal, and a reset terminal, and when a "1" level signal is input to the reset terminal,
When a clock pulse is input to the clock terminal, the data input to the input terminal is output from the output terminal and held, and when a "0" level signal is input to the reset terminal, "0" is output from the output terminal. Outputs a level signal. The output data Do of the register 2o is input to the input terminal of this flip-flop 24, and the output data Do of the register 2o is input to the reset terminal.
The output signal C of the register 2o and the counter 22 is input to the clock terminal.
K is input.

Next, the operation of this shift register will be explained.

First, when the reset signal R8 goes to the "0" level, the output signal C of the counter 22 goes to the rOJ level at its fall. As a result, the flip-flop 24 is reset, and the output signal Y becomes the rOJ level. counter 2
This state is maintained until (n-1)I clock pulses are input thereto. On the other hand, each time a clock pulse is input to the register 20, data DI is input from the input terminal, and data held by each flip-flop is sequentially shifted to the subsequent flip-flop, and output data DO is output from the output terminal. is output as

When the (n-1)th clock pulse is input, the output signal C of the counter 20 becomes "1" level, and the reset state of the flip-flop 24 is released. As a result, the flip-flop 24 inputs and latches the output data Do of the register 20 from the next clock pulse. The data DI input to the register 20 immediately after the counter 22 is hit is shifted to the (n-1)th flip-flop by (n-1> clock pulses) and output from the output terminal. , by the n-th clock pulse, it is latched into the flip-flop 24 and outputted as an output signal Y. Thereafter, every time a clock pulse is input, the output data Do of the register 20 is sequentially latched into the flip-flop 24 and outputted. In other words, this shift register works as an n-stage shift register.

FIG. 3 is a diagram showing a third embodiment of the shift register of the present invention.

In this embodiment, a shift register having an arbitrary number of stages, for example, n stages, is constructed using a specific number of counters, for example, a 25-decimal counter. Here, 2"+1<n
The school shall be selected in such a way that the number of students will be less than 21. This shift register consists of a first register 30 consisting of 21 flip-flops without a reset function, and a second register 30 consisting of (n-2"-1) IJ flip-flops without a reset function. 31 and binary counter 3
2, a flip-flop 33 with a reset function, and a mask gate 34 consisting of a two-man AND gate.

The output data DOA of the first register 30 is input to the input terminal of the flip-flop 33.
The output data DOa of the second register 31 is input to the input terminal of the second register 31, and the output data DOc of the second register 31 is input to one input terminal of the mask gate 34. Further, a common clock signal GK is input to the clock terminals of the first register 30, the flip-flop 33, the second register 31, and the counter 32. Furthermore, the output signal C of the counter 32 is input to the reset terminal of the flip 7O block 33 and the other input terminal of the mask gate 34.

In this shift register, when the reset signal (2) reaches the rOJ level, the output signal C of the counter 32 maintains the "0" level until a 2'' pulse is input, and the flip-flop 33 outputs a signal at the rOJ level. The mask gate 34 outputs a "0" level signal @Y. During this time, the data DI input to the input terminal of the register 3o immediately after reset 1- is shifted to the 2'' stage flip-flop of the register 3o, and when 2'' clock pulses are input, the data DI input to the input terminal of the register 3o is shifted to the flip-flop The reset state of is released, and since (n-2'''-1><2'), the (n-2'''-1) stage shift register 31
Each flip-flop of
0'' level output signal is held.

At the (2'+1)th clock pulse, the "0" level output signal of the flip-flop 33 is transferred to the second register 31.
At the same time, the output data DOA of the first shift register 30 is wrapped in the flip-flop 33. In addition, the mask gate 34
The output data DOC of the second register 31 is outputted from.

Thereafter, every time the reverse pulse is input, data OI is input from the input terminal of the first register 30, and output data DOa of the flip-flop 33 is sequentially shifted to the register 31 of box 2. In this way, ((2”+1)+(n −2′ −1)) m,
That is, until n clock pulses are input, the mask gate 34 outputs a "0" level signal Y, but immediately after n clock pulses are input, the first register 30 The data Dr inputted to is sequentially outputted.

The table shows a comparison result between a conventional shift register with a reset function and a reset i-burning shift register according to the present invention.

As shown in the table, stage l of the shift register! When n is 308 degrees, the shift register according to the present invention can reduce the number of gates by about 3% compared to the conventional shift register, but as the number of stages n increases, the ratio increases, and n-
512, the number of gates is reduced by about 18%.

In addition, the rate of increase in the number of stages compared to a shift register without a reset function also decreases as the number of stages n becomes smaller in the shift register according to the present invention, and n-
512, the increase is about 2%.

Furthermore, in the shift register of the present invention, the load on the external reset terminal is significantly reduced compared to the conventional shift register, since the reset signal is input only to the counter.

[Effects of the Invention] As described above, according to the present invention, the flip-flops constituting the register section do not require a reset function, so it is possible to reduce the number of gates required for the reset function for each of the seven flip-flops. Furthermore, since the reset signal is only input to the counter section, fAM at the external reset terminal does not increase.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of a shift register according to the invention, FIG. 2 is a diagram showing a second embodiment of a shift register according to the invention, and FIG. 3 is a diagram showing a third embodiment of a shift register according to the invention. 4 is a diagram showing a conventional shift register, FIG. 5 is a diagram showing the configuration of a 2'' base counter, and FIG. 6 is a diagram showing the operation of the first embodiment of the present invention. This is a timing chart for explanation. In the figure, 10.20 is a register, 30 is a first register, 31 is a second register, 12, 22.32 is a counter, 14.34 is a mask gate, 24.33 is a flip-flop with reset function, CK is a clock signal, DI
is input data, Do is output data, Y is output data, ■
indicates reset number 13, and C indicates no output signal. =g18 631=

Claims (1)

[Claims] A shift register that can be reset by an external signal, and includes a plurality of flip-flops connected in series, and each time a clock pulse is input, a signal input to the first stage flip-flop is sequentially transferred to a subsequent stage. a register section that transfers the data to the flip-flop of the terminal and outputs it from the flip-flop of the final stage; and a counter that has a reset function and outputs a predetermined signal after a predetermined number of clock pulses are input after being reset by the external signal. and an output control section that derives an output signal of the register section in response to the predetermined signal from the counter section.