JPS63298644A - Normal action confirming method for circuit to be tested - Google Patents

Abstract

PURPOSE:To decrease a manday by sampling a test object part in output data obtained by giving input data for test to a circuit to be tested at a selector latch circuit with a prescribed timing and collating the data of the result with the corresponding expected value data. CONSTITUTION:At the time of the test, a test program, an expected value data, etc., are loaded to a main memory 2, input data for test having a prescribed pattern are given to a tested circuit 3 and the output data are supplied through an interface part 9 to a selector latch part 7. On the other hand, a microprocessor 4 gives instruction data and timing from a test program in the memory 2 to a signal selecting instructing circuit 6, the circuit 6 samples the instruction data to a latch part 7 with a prescribed timing, collates the data of the result with the expected value data and detects automatically the error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for confirming the normal operation of a circuit under test, and particularly to a method for confirming the normal operation of a circuit under test in circuit simulation using digital calculation.

[Conventional technology]

In the conventional method of confirming the normal operation of this type of circuit under test, the data output by the circuit under test in response to test input data is output in the form of a time chart, and then the tester creates a time chart of the expected output value. It is checked to confirm its normality.

[Problem that the invention seeks to solve]

In the conventional method for confirming the normal operation of the circuit under test described above, as the circuit under test becomes larger and more complex, the types of test data patterns become enormous, so manually checking the time chart output requires a large amount of man-hours. The disadvantage is that you will have to spend a lot of money.

[Means for solving problems]

The method of confirming the normal operation of a circuit under test according to the present invention is to apply test input data having a preset pattern to the circuit under test of a simulation model, and send the output data in response to the test input data to the selector/latch circuit. In response to the control of the processor, the signal selection instruction circuit instructs the portion and timing of the test target in the output data to be sampled by the selector/latch circuit, and the sampling result data and the corresponding expected value are This is a method for automatically detecting errors by collating data and under the control of the processor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.9 FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a control unit 1 is connected to a main memory 2 for loading test programs for controlling simulation execution and subroutines for data confirmation, a circuit under test 3 that is a simulation model, and a microprocessor 4. be. Connected to the microprocessor 4 is a micromemory 4 into which microprograms are loaded.

FIG. 2 is a block diagram showing an example of the configuration of the control section 1 in this embodiment. A signal selection designation circuit 6 which instructs a signal to be saved in the main memory 2 in response to a signal arriving from the microprocessor 4, and an ink which relays the output signal of the circuit under test 3.

The re-output signal with the face section 9 is sent to the selector/latch section 7.
The output data of the selector/latch section 7 is saved in the main memory 2 via the memory write control section 8.

At the time of testing, the test program, expected value data, and data confirmation subroutine are first loaded into the main memory 2, and the test is started. The microprocessor 4 executes the test program loaded into the main memory 2 by referring to the microprogram in the micromemory 5.

When the test program specifies the signal to be checked and its timing, the microprocessor 4 provides instruction data to the signal selection instruction circuit 6 in response to the instruction, and the selector/latch section 7 samples the data to be checked. The sampled data to be checked is saved at an address specified by the program on the main memory 2 under the control of the memory write control unit 8. Thereafter, a data confirmation subroutine is started, the saved data is compared with the expected value data, and if an error is found, the information is written to a predetermined area of the main memory 2.

〔Effect of the invention〕

As explained above, according to the method for confirming normal operation of a circuit under test of the present invention, the output time chart I of the circuit under test is sampled at a specified timing, and errors are automatically detected by comparing expected value data. Therefore, there is an effect that a huge amount of manual checking can be omitted.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing embodiments of the present invention. 1...Control section, 2...Main memory, 3.
...Circuit under test, 4...Microprocessor, 5...
Micromemory, 6... Signal selection instruction circuit, 7...
Selector latch section, 8...Memory write control section, 9.
...Interface section.

Claims (1)

[Claims] Test input data with a preset pattern is given to the circuit under test of the simulation model, the output data in response is sent to the selector/latch circuit, and in response to the control of the processor, the data in the output data is The part and timing to be tested is instructed from the signal selection instruction circuit, the selector/latch circuit samples it, and the sampling result data and the corresponding expected value data are collated under the control of the processor and automatically performed. A method for confirming normal operation of a circuit under test, characterized by detecting errors.