JPS6329847B2 - - Google Patents

Info

Publication number
JPS6329847B2
JPS6329847B2 JP55072871A JP7287180A JPS6329847B2 JP S6329847 B2 JPS6329847 B2 JP S6329847B2 JP 55072871 A JP55072871 A JP 55072871A JP 7287180 A JP7287180 A JP 7287180A JP S6329847 B2 JPS6329847 B2 JP S6329847B2
Authority
JP
Japan
Prior art keywords
transistor
current
resistor
base
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55072871A
Other languages
Japanese (ja)
Other versions
JPS56169404A (en
Inventor
Yamato Okashin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7287180A priority Critical patent/JPS56169404A/en
Publication of JPS56169404A publication Critical patent/JPS56169404A/en
Publication of JPS6329847B2 publication Critical patent/JPS6329847B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34DC amplifiers in which all stages are DC-coupled
    • H03F3/343DC amplifiers in which all stages are DC-coupled with semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明はチユーニングメータ等の直流電流増巾
器に適用して好適であつて、トランジスタの直流
電流増巾率のバラツキを吸収すると共に動作点の
バラツキをも軽減するようにした電流増巾回路に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is suitable for application to a DC current amplifier such as a tuning meter, and absorbs variations in the DC current amplification factor of transistors and also reduces variations in operating point. The present invention relates to a current amplification circuit configured as described above.

従来、IC化した電流増巾回路は例えば第1図
のように構成されており、直流電流増巾率の変化
(通常50〜300)による出力電流のバラツキを小さ
く仰える為、トランジスタ2のベースにバイアス
供給用電源3と共に直列接続される抵抗器4とし
て直流電流増巾率hFEに対応して変化する第2図
のようなピンチ抵抗を使用する場合がある。尚、
ピンチ抵抗とは周知の如く、例えばP型の半導体
基板5上に成長させたN型半導体エピタキシヤル
層6にP型半導体のベース拡散領域7を形成し、
このベース拡散領域7内にN型半導体のエミツタ
拡散領域8を形成し、エピタキシヤル層6とエミ
ツタ拡散領域8とで挟まれた幅Wのベース拡散領
域7の部分にて形成した抵抗であつて、ベース拡
散領域7の両端に抵抗導出端子9,10が接続さ
れるものである。尚、6′,6″は分離層である。
これはトランジスタの構造の一部でもあり、トラ
ンジスタの場合にあつてはその直流電流増巾率
hFEはベース拡散領域7の幅Wの大小によつて殆
んど決定される。
Conventionally, a current amplification circuit implemented as an IC is configured as shown in Figure 1. In order to minimize variations in output current due to changes in the DC current amplification factor (usually 50 to 300), the base of transistor 2 is As the resistor 4 connected in series with the bias supply power source 3, a pinch resistor as shown in FIG. 2 may be used, which changes in accordance with the DC current amplification factor hFE . still,
As is well known, the pinch resistance is formed by forming a P-type semiconductor base diffusion region 7 in an N-type semiconductor epitaxial layer 6 grown on a P-type semiconductor substrate 5, for example.
An emitter diffusion region 8 of an N-type semiconductor is formed in this base diffusion region 7, and a resistor is formed in a portion of the base diffusion region 7 having a width W sandwiched between the epitaxial layer 6 and the emitter diffusion region 8. , resistance lead-out terminals 9 and 10 are connected to both ends of the base diffusion region 7. Note that 6' and 6'' are separation layers.
This is also part of the structure of the transistor, and in the case of a transistor, its DC current amplification rate
hFE is mostly determined by the width W of the base diffusion region 7.

第1図の基本回路を適用して直流電流増巾回路
を構成するとき、第3図に示す接続が考えられ
る。即ちベース・エミツタ間にダイオード11を
接続したトランジスタ12のコレクタをピンチ抵
抗13を通じて電源+Bに接続したものである。
この回路にあつては抵抗器13は上述したように
ピンチ抵抗にて形成されているので、その抵抗器
と同一の半導体基板5上において同時に形成され
る他のトランジスタの直流電流増巾率hFEのバラ
ツキをパラメータとしたとき入力電流Iと出力最
大電流IOとの特性は第4図の実線にて図示するよ
うに変化する。一方、抵抗器13を拡散抵抗に置
換えると、I−IO特性は破線にて図示するように
変化する。従つて、例えばチユーニングメータ1
7を電源+Bとトランジスタ2のコレクタが接続
される端子16との間に接続していわゆるチユー
ニング操作に便ならしめるとき、入力信号電圧
(dB)と出力最大電流IOとの特性は直流電流増巾
率hFEの変化により第5図にて図示するようにバ
ラついて変化してしまう。尚、第6図は拡散抵抗
の一例を示したものであり、第2図のピンチ抵抗
と略同様にしてP型半導体基板5上に形成したN
型半導体エピタキシヤル層6内にP型半導体のベ
ース拡散領域7を形成し、このP型半導体のベー
ス拡散領域7の両端に抵抗導出用端子9,10を
接続したものである。
When constructing a direct current amplification circuit by applying the basic circuit shown in FIG. 1, the connections shown in FIG. 3 can be considered. That is, the collector of a transistor 12 having a diode 11 connected between its base and emitter is connected to the power supply +B through a pinch resistor 13.
In this circuit, since the resistor 13 is formed of a pinch resistor as described above, the DC current amplification factor h FE of another transistor formed simultaneously on the same semiconductor substrate 5 as the resistor 13 is When the variation in is used as a parameter, the characteristics of the input current I and the maximum output current I O change as shown by the solid line in FIG. On the other hand, when the resistor 13 is replaced with a diffused resistor, the I- IO characteristics change as shown by the broken line. Therefore, for example, tuning meter 1
7 is connected between the power supply +B and the terminal 16 to which the collector of transistor 2 is connected to facilitate the so-called tuning operation, the characteristics of the input signal voltage (dB) and the maximum output current I O are as follows: As the width factor h FE changes, it varies as shown in FIG. 5. Incidentally, FIG. 6 shows an example of a diffused resistor, in which an N-type semiconductor substrate 5 is formed on a P-type semiconductor substrate 5 in substantially the same manner as the pinch resistor shown in FIG.
A P-type semiconductor base diffusion region 7 is formed in the P-type semiconductor epitaxial layer 6, and resistance lead-out terminals 9 and 10 are connected to both ends of the P-type semiconductor base diffusion region 7.

斯かる点に鑑み、本発明は上述の欠点を除去し
てチユーニングメータ等に適用して好適であつ
て、直流電流増巾率hFEのバラツキを吸収すると
共に動作点のバラツキをも軽減するようにした電
流増巾回路を提案せんとするものである。
In view of this, the present invention eliminates the above-mentioned drawbacks, is suitable for application to tuning meters, etc., and absorbs variations in the DC current amplification factor h FE and also reduces variations in the operating point. The purpose of this paper is to propose a current amplification circuit as described above.

以下に、第7図〜第9図を参照して本発明によ
る電流増巾回路の一実施例につき詳細に説明する
も上述した第1図〜第6図と対応する部分には同
一符号を付してその重複説明を省略する。
An embodiment of the current amplification circuit according to the present invention will be described in detail below with reference to FIGS. 7 to 9, and parts corresponding to those in FIGS. 1 to 6 described above are given the same reference numerals. The redundant explanation will be omitted.

本発明による電流増巾回路は、入力信号に対応
した電流が供給されるカレントミラー回路MKを
構成し、この回路MKを形成するトランジスタ1
2のコレクタとエミツタとに夫々ピンチ抵抗1
3,14を挿入し、この第1のトランジスタ12
のコレクタから取り出された出力電流を駆動電流
として第2のトランジスタ2のベースに供給する
ようになし、カレントミラー回路MKの夫々のピ
ンチ抵抗13,14、第1のトランジスタ12及
び第2のトランジスタ2を同一の半導体基板上に
て製造したものである。
The current amplification circuit according to the present invention constitutes a current mirror circuit MK to which a current corresponding to an input signal is supplied, and a transistor 1 forming this circuit MK.
1 pinch resistor on the collector and emitter of 2, respectively.
3 and 14, and this first transistor 12
The output current taken out from the collector of the current mirror circuit MK is supplied to the base of the second transistor 2 as a drive current, and the pinch resistors 13 and 14 of the current mirror circuit MK, the first transistor 12, and the second transistor 2 are manufactured on the same semiconductor substrate.

即ち、第7図においては入力端子1a,1bを
介して被測定信号が供給される第1のトランジス
タ12のベースをダイオード11及び電流制限用
拡散抵抗4を介して接地し、コレクタを第2のト
ランジスタ2のベースに接続すると共に上述と同
様にしてピンチ抵抗13を介して電源+Bに接続
し、エミツタをピンチ抵抗14を介して接地し、
第2のトランジスタ2のコレクタをチユーニング
メータ接続端子16に接続し、そのエミツタを直
接接地し、チユーニングメータ17を端子16と
電源+Bとの間に接続するようにしたものであ
る。
That is, in FIG. 7, the base of the first transistor 12 to which the signal under test is supplied via the input terminals 1a and 1b is grounded via the diode 11 and the current limiting diffused resistor 4, and the collector is connected to the second transistor 12. It is connected to the base of the transistor 2 and connected to the power supply +B via the pinch resistor 13 in the same manner as described above, and its emitter is grounded via the pinch resistor 14.
The collector of the second transistor 2 is connected to the tuning meter connection terminal 16, its emitter is directly grounded, and the tuning meter 17 is connected between the terminal 16 and the power supply +B.

上述した構成によれば、第1のトランジスタ1
2、第2のトランジスタ2及びピンチ抵抗13,
14は同一の半導体基板上にて製造されており、
第1のトランジスタ12のベースにダイオード1
1を介して拡散抵抗4が接続され、そのコレクタ
にピンチ抵抗13を接続し、そのエミツタにピン
チ抵抗14が接続されているので、同一基板上に
形成したトランジスタの直流電流増巾率hFEが変
動した場合にあつてもピンチ抵抗13,14との
抵抗値の比は一定であり、ピンチ抵抗14と拡散
抵抗4との比が変化するようになるので、入力電
流Iと出力最大電流IOとの特性はhFEが変化して
も第8図のようにさほどバラつくことなく、又同
様にして入力信号強度(dB)と出力最大電流IO
との特性もhFEが変化しても第9図のようにさほ
どバラつくことはない。
According to the configuration described above, the first transistor 1
2, second transistor 2 and pinch resistor 13,
14 are manufactured on the same semiconductor substrate,
A diode 1 is connected to the base of the first transistor 12.
1, a pinch resistor 13 is connected to its collector, and a pinch resistor 14 is connected to its emitter, so that the direct current amplification factor h FE of the transistors formed on the same substrate is Even when the resistance value varies, the ratio of the resistance values of the pinch resistors 13 and 14 remains constant, and the ratio of the pinch resistor 14 to the diffused resistor 4 changes, so that the input current I and the maximum output current I O The characteristics of h FE do not vary much as shown in Figure 8 even when FE changes, and in the same way, input signal strength (dB) and maximum output current I O
Even if h FE changes, the characteristics do not vary much as shown in Figure 9.

又、第2のトランジスタ2のhFEが大となつた
とするとピンチ抵抗13,14の抵抗値も大とな
るが、これにより第1のトランジスタ12、ピン
チ抵抗13,14、拡散抵抗4及びダイオード1
1にて構成されるカレントミラー回路MKの利得
は小さくなり、これによつて第2のトランジスタ
2のベースエミツタ電流が多く流れ、第2のトラ
ンジスタ2は導通状態が深まる。尚、ピンチ抵抗
13は第2のトランジスタ2の出力最大電流IO
即ちチユーニングメータ(図示せず)の最大電流
を決定している。
Furthermore, if the h FE of the second transistor 2 increases, the resistance values of the pinch resistors 13 and 14 also increase;
The gain of the current mirror circuit MK constituted by 1 becomes small, and as a result, a large amount of base-emitter current flows through the second transistor 2, and the second transistor 2 becomes more conductive. In addition, the pinch resistor 13 is connected to the maximum output current I O of the second transistor 2,
That is, the maximum current of the tuning meter (not shown) is determined.

斯くして、本発明による電流増巾回路によれ
ば、ピンチ抵抗と、第1及び第2のトランジスタ
とを同一半導体基板上にて形成することによつて
ベース拡散領域の幅Wを個々のICにおいては同
一の幅に規制することができて、直流電流増巾率
hFEに対応した抵抗値が得られるので、ICの製造
上における個々のICにおける直流電流増巾率の
バラツキによつて入力電流−出力最大電流の特性
がバラつくのを極力抑えることができ、率いては
動作点のバラツキをも軽減することができる。
Thus, according to the current amplification circuit according to the present invention, by forming the pinch resistor and the first and second transistors on the same semiconductor substrate, the width W of the base diffusion region can be made smaller than that of the individual ICs. can be regulated to the same width, and the DC current amplification rate is
Since a resistance value corresponding to h FE can be obtained, variations in the input current - maximum output current characteristics due to variations in the DC current amplification factor of individual ICs during IC manufacturing can be suppressed as much as possible. It is also possible to reduce variations in operating points.

尚、本発明による電流増巾回路は第2のトラン
ジスタのコレクタ側にメータを接続し、第1のト
ランジスタのベース側に被測定入力信号を供給す
ることにより、チユーニングメータの駆動回路と
して容易に適用できること勿論であるが、本発明
は上述の例に限ることなく他の種々の例に容易に
適用できる。
The current amplification circuit according to the present invention can be easily used as a tuning meter driving circuit by connecting the meter to the collector side of the second transistor and supplying the input signal to be measured to the base side of the first transistor. Of course, the present invention is not limited to the above-mentioned example, but can be easily applied to various other examples.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来における電流増巾回路の基本回路
図、第2図は第1図におけるピンチ抵抗の断面
図、第3図は従来における電流増巾回路の回路
図、第4図は第2図の入力電流−出力最大電流の
特性曲線図、第5図は第2図の入力信号電圧−出
力最大電流の特性曲線図、第6図は第2図におけ
る拡散抵抗の断面図、第7図は本発明による電流
増巾回路の一例の回路図、第8図は第7図の入力
電流−出力最大電流の特性曲線図、第9図は第7
図の入力信号電圧−出力最大電流の特性曲線図で
ある。 2は第2のトランジスタ、12は第1のトラン
ジスタ、13及び14はピンチ抵抗、MKはカレ
ントミラー回路である。
Fig. 1 is a basic circuit diagram of a conventional current amplification circuit, Fig. 2 is a cross-sectional view of the pinch resistor in Fig. 1, Fig. 3 is a circuit diagram of a conventional current amplification circuit, and Fig. 4 is a diagram of Fig. 2. Figure 5 is a characteristic curve diagram of input current vs. maximum output current, Figure 5 is a characteristic curve diagram of input signal voltage vs. maximum output current in Figure 2, Figure 6 is a cross-sectional diagram of the diffused resistor in Figure 2, and Figure 7 is A circuit diagram of an example of a current amplification circuit according to the present invention, FIG. 8 is a characteristic curve diagram of the input current-maximum output current of FIG. 7, and FIG.
FIG. 3 is a characteristic curve diagram of input signal voltage versus maximum output current in the figure. 2 is a second transistor, 12 is a first transistor, 13 and 14 are pinch resistors, and MK is a current mirror circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 第1のトランジスタのエミツタ及びコレクタ
に抵抗が接続されると共にベースには該第1のト
ランジスタのベースエミツタ間電圧に略等しいバ
イアス電圧を供給するために供されるダイオード
及び該ダイオードの電流を制限するための抵抗が
接続されており、上記ベースに入力信号が供給さ
れコレクタからこれに対応する信号が出力される
カレントミラー回路と該出力信号が供給される第
2のトランジスタを備える電流増巾回路におい
て、上記第1のトランジスタのエミツタ及びコレ
クタに接続される抵抗はピンチ抵抗で形成され、
上記ダイオードの電流を制限するための抵抗は拡
散抵抗で形成されると共に上記第1、第2のトラ
ンジスタ及び夫々のピンチ抵抗が同一の半導体基
板上にて製造されていることを特徴とする電流増
巾回路。
1 A resistor is connected to the emitter and collector of the first transistor, and a diode is provided to the base to supply a bias voltage substantially equal to the base-emitter voltage of the first transistor, and the current of the diode is limited. A current amplification circuit comprising: a current mirror circuit to which a resistor is connected, an input signal is supplied to the base and a corresponding signal is output from the collector; and a second transistor to which the output signal is supplied. , the resistor connected to the emitter and collector of the first transistor is formed of a pinch resistor,
The current increasing device is characterized in that the resistor for limiting the current of the diode is formed of a diffused resistor, and the first and second transistors and the respective pinch resistors are manufactured on the same semiconductor substrate. Width circuit.
JP7287180A 1980-05-30 1980-05-30 Current amplifying circuit Granted JPS56169404A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7287180A JPS56169404A (en) 1980-05-30 1980-05-30 Current amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7287180A JPS56169404A (en) 1980-05-30 1980-05-30 Current amplifying circuit

Publications (2)

Publication Number Publication Date
JPS56169404A JPS56169404A (en) 1981-12-26
JPS6329847B2 true JPS6329847B2 (en) 1988-06-15

Family

ID=13501810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7287180A Granted JPS56169404A (en) 1980-05-30 1980-05-30 Current amplifying circuit

Country Status (1)

Country Link
JP (1) JPS56169404A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0525655U (en) * 1991-03-14 1993-04-02 ウシオ電機株式会社 Incandescent light bulb

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0525655U (en) * 1991-03-14 1993-04-02 ウシオ電機株式会社 Incandescent light bulb

Also Published As

Publication number Publication date
JPS56169404A (en) 1981-12-26

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