JPS6329789A - Image display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an image display device, particularly a bitmap memory (
The present invention relates to a rask scan type image display device having a BMM).

[Prior Art] BMM is a two-dimensional image in which one bit (several bits in color) is assigned to each pixel, and each pixel is displayed as a raster on a display means such as a cathode ray tube (CRT). Ru. Although the present invention can be applied to a color image display device, for convenience of explanation, a monochrome image display device will be described. In the actual memory configuration of BMM, when using a random access memory (RAM) with 1 word = 16 bits as shown in Figure 9, in an image display device with a resolution of 1280 x 1024, one horizontal scanning line is 1280 ÷ 16 = 8.
Consists of 0 words. This BMM can be thought of as a two-dimensional array of 80x1024 in word units. Hereinafter, in this specification, the dimension of memory will be considered in units of words. Also, the terms 1-dimensional array and 2-dimensional array are
This refers to a memory management arrangement, not a physical arrangement.

FIG. 7 is a block diagram of a conventional image display device to which the present invention is applied. This device is a central processing unit (CPU)
'2, Read only memory (ROM) 4, RAM6,
An input device 8 such as a keyboard is connected to the CPU bus, and the CPU bus is further connected to the 8MM 12 via a display controller (for example, a CRT controller: CRTC) 10.

The contents of 8MM12 are displayed on the CRT display screen via the readout circuit 16.

As shown in the figure, the 8MM12 may have a capacity corresponding to a plurality of display screens, and each memory portion corresponding to the display screen is called a page. Each page 12a,
12b and 12c are assigned to a graphic screen, a character screen, etc., and each page can be displayed on the CRT 14 individually or in a superimposed manner as required. Usually, each page is distinguished by the upper bits of the memory address.

Recently, CRTClo has so-called BitBrit.
(BITBLT: Bit, Boun
There is one that has a function called daryBlock Transfer (abbreviation for daryBlock Transfer). For example, Hitachi, Ltd.
One example is the RT controller LSI HD63484. BITBLT is a function that transfers an arbitrary rectangular area in the display memory to another memory portion, and can perform high-speed data transfer using hardware (firmware). It is also called rask operation because it can perform logical operations bit by bit on the memory contents of the transfer source and the memory contents of the transfer destination.

Normally, in this BITBLT transfer rectangular area specification, B
Although there is no need to be aware of word boundaries in MM, especially when high-speed transfer is required, the specification of rectangular areas may be limited to word boundaries to simplify hardware (firmware) processing. For details on the BITBLT function, see Nikkei Electronics Magazine, July 29, 1985 issue No. 1.
See pages 41-161.

As one use of the BITBLT function, 1 of 8MM12
A page (for example, page 12b) is set as a hidden page, and the character pattern required for this page (as shown in Fig. 8) is set in advance.
Characters are written by writing the necessary characters (font) in advance and transferring the necessary characters in units of rectangular areas to a display page (for example, page 12a). Conversely, figure 17 written on page 12a is
Transfer it to B, store it, and read it later.

Considering the B I TBLT operation in units of memory words, as shown in FIG. 9, when transferring a rectangular area 20s of page 12b to a rectangular area 20d of page 12a, CRTC
For l0, specify the upper left word attribution/sn of the transfer source rectangular area 20s and the word width △X and height △Y (in this example, △X=2゜△Y=3), and , by specifying the address (81) of the upper left word of the destination rectangular area 20d, the address n, n+80 . n+
160. n+1. n+81. The data of n+161 is sequentially transferred to address 81°161.24 of page 12a in lJ terms.
1, 82, 162, 242. Note that each address also includes upper bits of the address for identifying the page. At this time, the instruction format for CRTClo is, for example, C0PY2, 3. It will be in the form n, 81. Even if the left and right boundaries of the destination rectangular area do not match the word boundaries, CRTC2a is sent before the BITBLT operation.
The command for transferring the rectangular area 22s of page 12b to the rectangular area 22d of page 12b can be expressed as C0PYI,4°79,m.

[Problems to be Solved by the Invention] However, the address control circuit of the BMM in CRTClo has an upper limit on addresses, and a large amount of display data,
For example, kanji data (JIS 1st and 2nd level kanji 6
000 or more) in one page. Of course, it is impossible to prepare kanji in various different sizes. Furthermore, since the stored display data is managed in two dimensions, it is difficult to efficiently manage a rectangular area of any size.

Therefore, the present invention provides an image display device that can manage a large amount of display data quickly and efficiently without being restricted by the address control circuit of the BMM.

[Means for Solving the Problem] The present invention provides a two-dimensional bitmap memory in which a plurality of words are two-dimensionally arranged, and a function for mutually transferring a rectangular area of a desired size between pages of the bitmap memory. In an image display device comprising a display controller and a central processing unit that controls the display controller, one of the pages includes a one-dimensional memory in which a plurality of words are arranged one-dimensionally, the one-dimensional memory and the buffer means including a one-word buffer that mediates between both data buses of the bitmap memory; and after an initial value is set by the central processing unit, the buffer means is incremented at least every read operation of the display controller. and an address generator for specifying the address of the one-dimensional memory.

[Function] According to the present invention, since there is no structural limit to the capacity of the one-dimensional memory, not only can a large amount of data such as kanji characters be handled as a target of BITBLT operation, but also the one-dimensional memory can be used for display From the controller's point of view, bitmap memory 1
It is equivalent to a page, and there is no problem with the BITBLT operation of the display controller.

Furthermore, a one-dimensional memory allows for efficient management of rectangular areas of any size.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6. FIG. 1 is a block diagram for explaining the present invention in detail. Since the image display device according to the present invention is mostly the same as the conventional device shown in FIG. 7, only the parts related to the differences are shown. The main difference between the image display device of the present invention and the conventional device is that one page (performed using high-order bit data), as well as
consists of a large-capacity one-dimensional memory 33 and a buffer means 26 including a one-word buffer, and the address of the one-dimensional memory 33 is specified by an address generator 27 separate from the CRTCIO. The initial address of the one-dimensional memory 33 is set in the address generator 27 by the CPU during a rectangular area transfer operation, and the address is incremented by 1 for each page X read/write (R/W) command. .

The upper limit of the address of page X is determined by the address generator 27, so by increasing the number of output bits of the address generator 28, the capacity of page . 1
Data exchange between page X of the dimensional memory and other pages (for example, page 1) of the two-dimensional memory is carried out via the buffer means 26, which serves as a so-called zero-dimensional window. CR
Page X seen from TClo is no different from any other page, and there is no change in the configuration of CRTCl 0.

FIG. 2 shows a block diagram of an embodiment of the present invention. 1st
Blocks that are equivalent to those in the figure are given the same reference numerals. In this embodiment, the buffer means 26 of FIG. 1 comprises a bidirectional three-state buffer 36.

This three-state buffer 36 mediates between the data bus of the one-dimensional memory 33 and the 8MM data bus of CRTClo. The upper bits of the 8MM address from CRTCl 0 are input to the decoder 34, and the page specified by that address is determined. If the upper two bits of the 8MM address are used for page designation, the number of pages is 22=4.

Decoder 34 enables only the specified page of memory. An enable signal 35 from the decoder 34 to page X is applied to an enable input terminal G of a three-state buffer 36. The data conduction direction of the 3-state buffer 36 depends on the BMM readout signal received at the DIR input terminal. Of course, if the connection relationship of both data buses is reversed,
A BMM write signal may be applied to the DIR input terminal.

One-dimensional memory 33 may include not only RAM but also ROM. Fixed display data can be written in the ROM in advance. If there is no need to rewrite or add display data, the one-dimensional memory 33 is composed of only a ROM. Each memory chip in one-dimensional memory 33 is selectively enabled by the upper bit of the output of counter 28.

The address generator 27 of FIG. 1 may be comprised of a counter 28. For example, if the total memory capacity of the one-dimensional memory is 4M words, a 22-bit counter is used as the counter 28. The initial address of the one-dimensional memory 33 is loaded into the counter 28 prior to rectangular area transfer. If the data bus width of the CPU is smaller than the number of bits of the counter 28,
Load it in two parts. The contents of the counter 28 are AN
It is stepped by the output of the D gate 38. AND gate 38 receives the output of OR gate 32 and the output 35 of decoder 34. The OR gate 32 outputs the BMM write/read signal (W/R
). However, if the one-dimensional memory 33 is only a ROM, it receives only the BMM read signal R. Therefore, the counter 28 will be incremented by the BMM page X write or read signal. The one-dimensional memory 33 disables the BMM write signal and is set to the read state except when this signal is in the active state. Of course, the BMM write signal is not applied to the ROM in the one-dimensional memory 33.

The operation of the embodiment shown in FIG. 2 will be explained with reference to FIG. The 5th A plan cloudy cloud transferred 1 word = 1 1
The stored contents of the display page 12a are shown. 1D memory 3
3 includes alphabetic fonts in two sizes, 8X16 and 16x32, as well as 16x16 and 32
It stores two sizes of kanji fonts: x32. 32
Since the x32 kanji font has a width of 2 words, it is stored separately on the left and right sides. It goes without saying that other font sizes can also be set arbitrarily. Now, in the apparatus shown in FIG. 2, the display page 12 a (7) rectangular area 90 shown in FIG. 5C
Transfer the small size TT A ++, "+C11" within the rectangular area 92, the large size ``'' Ar1 within the rectangular area 92, then transfer the small sized kanji ``special'' within the rectangular area 97, and then transfer the small sized kanji ``special'' into the rectangular area 97.
Assume that you want to transfer a large-sized kanji character "Toku" in 8. The procedure is shown below.

・Small size 'l A +1 to address B of page 12a
Transfer to the left half of the 16x16 rectangular area 90 starting at A1.

1) CR to mask the right half of the 16-bit word
Set the mask register of TCl 0.

2) Load N into address counter 28.

3) Instruction C0PYI, 16. PX, BAI to CRTCl
Granted to 0. (However, PX is an arbitrary address in page

1) Set the mask register to mask the left half of the 16-bit word.

2) Load N+32 into address counter 28.

3) Instruction C0PYI, 16. PX, BAIQ granted.

・Large size IT A11 starting with address BA+1 1
Write in a 6×32 rectangular area 92.

1) Cancel the mask setting of the mask register.

2) Load P into the address counter 28.

3) Instruction C0PYI, 32. Grants PX and BA1+1.

・Write "small size special" in the 16x16 rectangular area 97 starting at address BA2.

1) Cancel the mask setting of the mask register. (Unnecessary if it has already been released) 2) Load Q into the address counter 28.

3) Instruction C0PYI, 16. Grants PX and BA2.

・Write "large size special" in the 32x32 rectangular area 98 starting at address BA3.

1) Cancel the mask setting of the mask register. (Unnecessary if it has already been released) 2) Load R into the address counter 28.

3) Instruction C0PY2,32. Granted PX and BA3.

Regarding the operation of transferring small size II A +1, CR
When TCIO receives the C0PY command, it transfers a rectangular area of 16 words starting from address PX of page X to page 1.
It is understood that this is an instruction to transfer to a similar rectangular area starting at address BAI of 2a. CRTCl 0 then reads one word of page X at address PX. in fact,
Since there is no two-dimensional memory on page X, address P
The upper bits of X are simply used to enable tri-state buffer 36 so that the one word of one-dimensional memory addressed by address counter 28 is read through tri-state buffer 36 to CRTCl0. This one word data is then transferred to address BAI of page 12a.
will be written to. However, since the right half of the word is masked, only the left half is written. Since the address counter 28 has been incremented by 1 by the previous page X read signal, one word at the next address position (N+1) is read out and written one line below the previous write position on page 12a. If this kind of action is repeated 16 times, the small size IU
The A l+ BITBLT operation ends. Other BITs
The BLT operation is also similar except that the state of the mask and the size of Δx1ΔY are different. Transfer from page 12a to page X can be similarly performed by reversing the transfer source and transfer destination addresses of the C0PY instruction.

After loading the initial address into the counter 28, the address for reading a certain word in the one-dimensional memory 33 is specified in increments by the trailing edge of the read pulse of the immediately previous word.
The one-dimensional memory 33 has a long enough time to stabilize the data, and the one-dimensional memory 33 has a long access time
Low speed) and inexpensive memory can be used. this is,
This is especially useful considering that the one-dimensional memory 33 has a large capacity.

FIG. 3 is a block diagram of a second embodiment of the image display device according to the present invention. This embodiment differs from the first embodiment in that when character data is transferred from page X to page 12a, in order to enlarge the characters in the A frequency divider #72 that divides the step signal by 1/M and a data converter 68 that receives read data from the one-dimensional memory 33 are provided. Associated with this is a latch 70 that receives control data for the data converter 68. The bidirectional three-state buffer 36 also includes two unidirectional three-state buffers 64.6.
6, and AND gates 60, 62 are provided for each enable signal. In this example, CRTCl
Data is written from the 0 side to the one-dimensional memory 33 via a unidirectional three-state buffer 64. Conversely, reading from the one-dimensional memory is performed using the data conversion circuit 68 and the unidirectionality 3.
This is done via the state buffer 66. Expansion in Y direction is 1
This can be done by setting magnification data to the /M frequency divider 72 from the CPU. For example, when 1/2 frequency division is set by data from the CPU, the frequency divider 72 increments the counter 28 by 1 every time it receives two BBM read signals. This means that data at the same address in the one-dimensional memory 33 is transferred (read) twice in succession. As a result, the font read from the one-dimensional memory 33 is enlarged twice in the Y direction. When M=1 is set, it is equivalent to the case where there is no branching device 72.

Expansion in the X direction regarding the data conversion circuit 68 will be explained with reference to FIG.

Figure 4 shows data converter #! This is an example of I68.

In this example, the data conversion circuit 68 includes eight data selector chips 80a each including two 4-to-1 data selectors.
It consists of ~80h. Each data selector chip has the same configuration, and according to the data received at the control input terminals A and B, one signal from the input terminals ICO to IC3 is sent to the output terminal IY, respectively.
One signal from the input terminals 2CO to 203 is selectively applied to the output terminal 2Y. Table 1 shows the relationship between the input/output and control signals of the data selector.

Data LO and Ll from the latch 70 in FIG. 3 are applied to control input terminals A and B of each data selector. Data L
Table 2 shows the relationship between O, Ll and the functions of this data conversion circuit 68.

Table 1 Control input 1 Output BA IY2Y 0 0 l IC02CO 01l IC12C1 1011C22C2 11l IC32C3 Table 2 Ll, LOI B) (A) Function 00 1xl (no enlargement) 01 1x2 (left) 101x2 (right) 11 1 All O or all 1 Data selectors 80a to 80 to achieve this function
The input connection relationship of h is shown in Table 3.

Table 3 1 2c32c22cl 2cO1c31c21cl
1eO80al X D8 Do DOX D8 D
ODI80blXD9 old D2XD9 old D3 80e l XDIOD2 D4 XDIO
D2 D580d l XDII D3 D6
XDII D3 D780e l XD12
D4 D8 XD12 D4 D980f
l X DI3 D5 DIOX DI3 D5 D
l180g l X DI4 D6 DI2
X DI4 D6 D1380h l X DI
5 D7 DI4 X DI5 D7 DI5
(X is 1 when all 1s are present, and 0 when all 0s are present) Furthermore, Table 4 shows the relationship between input data DO to D15, output data XO to X15, and control data LO1L1 of the data conversion circuit 68.

Table 4 1 LILOLILOLILOLILOL 00
01 10 11 out I XI
x2 left x2 right 9 All 1 or OXOI Do
Do D8 XX1l DI D
OD8 XX21 D2 DI D9
XX31 D3 DI D9
XX4 l D4 D2 DIOXX5
l D5 D2 DIOXX6 l
D6 D3 Dll XX7 l
D7 D3 Dll XX8 1
D8 D4 DI2 XX9 l
D9 D4 DI2 XXl0I
DIOD5 DI3 XX1ll D
ll D5 DI3 XX121 D
I2 D6 DI4 XX131 D
I3 D6 DI4 XX141 D
I4 D7 DI5 XX151 D
I5 D7 DI5 X The function of the data conversion circuit can be easily understood from this table. That is, L1=L
When O=0, no expansion in the X direction is performed, and L1=0,
When LO=1, the left half of one word is enlarged twice in the X direction, and when L1=1 and LO=O, the right half of one word is enlarged twice in the Y direction.

When L1=LO=1, all 1 for filling
Or all O's to clear.

Referring again to FIG. 5, the enlargement operation of the apparatus shown in FIG. 3 will be explained. First, a large-sized TT A II character enlarged twice in the X direction is transferred to the rectangular area 94, and then a large-sized It AIt character enlarged twice in the X and Y directions is transferred to the rectangular area 94. 96.

・Enlarged twice in the X direction.

1) Unmask the mask register.

2) Load P into the address counter 28.

3) Set L1=0 and LO=1 in latch 70.

4) Set the branching unit 72 to M=1.

5) COPYI, 32. PX, BA1+2 with CRTCl
Granted to o.

6) Load P into the address counter 28.

7) Set L1=1 and LO=O in latch 70.

8) COPYI, 32. PX, BA1+3 with CRTCl
Granted to o.

・Enlarged twice in both the X and Y directions.

1) Unmask the mask register.

2) Load P into the address counter 28.

3) Set L1=0 and LO=1 in latch 70.

4) Set frequency divider 72 to M=2.

5) COPYI, 64. PX, BA1+4 with CRTCl
Granted to o.

6) Load P into the address counter 28.

7) Set L1=1 and LO=0 in latch 70.

8) COPYI, 64. PX, BA+5 to CRT Clo
Granted to.

Although not shown, it is also possible to enlarge only in the Y direction. Furthermore, large-sized Kanji characters can also be enlarged in the X and Y directions. For example, if you want a large size, you only need to repeat the C0PY command four times.If you use an 8-to-1 data selector for the data selector 68 instead of the 4-to-1 data selector shown in the figure, it is possible to expand the data by 4 times in the X direction. Table 3
Input data DO to D15 to each data selector shown in
By selectively switching the connection relationship using another data selector or the like, shifted data can also be obtained at the output terminal of the data converter 68. This makes it possible to specify the transfer destination character display position in units of pits.

Thus, according to the embodiment of FIG. 3 of the present invention, BIT
Since characters and figures can be enlarged by effectively using the BLT function, there is no need to prepare fonts of all sizes in the one-dimensional memory 33, which reduces the capacity of the one-dimensional memory 33 and allows you to enlarge various You can get the display font size.

Next, a third embodiment of the present invention will be described with reference to FIG. The main difference from the first embodiment shown in FIG. 2 is that an access port from the CPU is newly provided to the one-dimensional memory 33. That is, the data bus of the one-dimensional memory 33 is connected to the bidirectional three-state buffer 5 so that the content of the one-dimensional memory can be directly read and rewritten by the CPU.
4 to the CPU's data bus. To enable the buffer 54, the output 53 of the address decoder 52 of the CPU is applied to the G input terminal. Buffer 54
A CPU bus read signal R is applied to the DIR input to determine the direction of the CPU bus. In addition, in order to control the address path of the one-dimensional memory 33 from the CPU side, the CPU read/write
An OR gate 42 receives the write signal, an output 53 of the decoder 52, and an AND gate 4 that receives the output of the OR gate 42.
4.Furthermore, OR receives Ryokawa force of AND gate 38.44
A gate 48 is also provided.

This configuration not only allows the CPU to directly read and write the contents of the one-dimensional memory, but also allows the one-dimensional memory
3 can be shared as a memory for storing stroke kanji data.

The stroke kanji data is not character data as a font as shown in FIG. 5, but data in which relative coordinate information of the end points of each line segment forming a character is sequentially arranged one-dimensionally. Normally, the stroke kanji data memory is a one-dimensional memory arranged on the main memory space, and focusing on the fact that its hardware structure is the same as the one-dimensional memory 33, this embodiment uses a one-dimensional memory. The dimensional memory 33 can be shared as a stroke kanji data memory. The stroke kanji data is read by the CPU and based on this, line segment drawing information is given to the CRTC 10. Therefore, although the writing speed of characters to the BMM is inferior to writing by BITBLT transfer, since processing is performed by the CPU, expansion in the X and Y directions can be performed by any multiple, including non-integer multiples. This shared configuration greatly simplifies the device.

Although the preferred embodiments of the present invention have been described above, it will be obvious to those skilled in the art that various modifications and changes can be made without departing from the gist of the present invention. For example, buffer 36 may be an open collector buffer. It is also conceivable that the address generator 27 uses an accumulator instead of a counter. Furthermore, the number of bits in one word and the memory capacity are not limited to those described above.

[Effects of the Invention] As described above, according to the image display device of the present invention, by adding the one-dimensional memory 33, buffer means 26, and address generator 27, it is possible to display a large amount of character/graphic data without impairing the conventional BITBLT function. can be handled as a target of BITBLT operation.

Since the display data is managed one-dimensionally, a rectangular area of any size can be efficiently managed. Since the initial address of the one-dimensional memory is incremented and specified by the previous read/write command, an inexpensive memory with slow access time is used for the large-capacity one-dimensional memory 33, and the expansion in the direction is performed by using the row left and counter 28. By dividing the step input, it is possible to expand in the Y direction. Also, 1
By adding a CPU access port to the dimensional memory 33, it can be shared as a one-dimensional memory 33@stroke kanji data memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the present invention in detail, FIG. 2 is a block diagram of a first embodiment of the present invention, FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a block diagram of a second embodiment of the present invention. FIG. 3 is a block diagram of the data conversion circuit 68, FIG. 6 is a block diagram of a third embodiment of the present invention, FIG. 7 is a block diagram of a conventional image display device to which the present invention is applied, and FIGS. Figure 9 is BITBL
FIG. 3 is a diagram showing the data storage state and word structure of the BMM for explaining the T operation. In the figure, 10 is a display controller, 12 is a bit map memory (BMM), 26 is a buffer means, 27 is an address generator, and 33 is a one-dimensional memory. Patent applicant: Sony Tektronix Corporation rQ
l) A-year-old 5B mouth

Claims (1)

[Scope of Claims] A bitmap memory, a display controller having a function of mutually transferring a rectangular area of a desired size between pages of the bitmap memory, and a central processing unit that controls the display controller. In an image display device, one of the pages includes a one-dimensional memory in which a plurality of words are arranged one-dimensionally, and a one-word buffer that mediates between the two data buses of the one-dimensional memory and the bitmap memory. and an address generator which, after an initial value is set by the central processing unit, is incremented at least every read operation of the display controller to designate an address of the one-dimensional memory. An image display device characterized by: