JPS6329348B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a PCM signal processing device.

As an example of a PCM signal recording and reproducing device, a PCM signal is converted into a signal format similar to a television signal, and a VTR (video tape recorder) is used.
Devices that record and reproduce PCM signals are known.
In FIG. 1, 1 indicates a VTR, and 2 indicates a PCM signal processing device having an adapter configuration. VTR
Reference numeral 1 is, for example, a helical scan type having two rotating heads, and supplies a video signal from a video input terminal 3 to a rotating head (not shown) via a recording system 4, and records it on a magnetic tape. , a reproduction signal from the magnetic tape is supplied to a reproduction system 5, and a reproduction video signal is generated at a video output terminal 8 via one input terminal 7a and an output terminal 7c of a changeover switch 6. The selector switch 6 connects the input terminal 7a and the output terminal 7c only during playback, and connects the output terminal 7 during other recording and stop times.
c is connected to the other input terminal 7b,
It is switched in relation to the operating state of the VTR1. The other input terminal 7b of this switch 6 is connected to the video input terminal 3.

The PCM signal processing device 2 includes a video output end 9 and a video input end 10 connected to the video input end 3 and video output end 8 of the VTR 1, respectively. An A/D converter 13, an encoder 14, and a video amplifier 15 are inserted between the analog input terminal 11 and the video output terminal 9, and a synchronous separation circuit is inserted between the video input terminal 10 and the analog output terminal 12. circuit 1
6, a decoder 17, and a D/A converter 18 are inserted. Amplifier 1 for analog output terminal 12
A monitor speaker 20 is connected via 9. Actually, the stereo audio signal
Since it performs PCM modulation and PCM demodulation, it is composed of an A/D converter 13 and a D/A converter 18, respectively.
PCM modulators and PCM demodulators are provided for two channels.

The encoder 14 relates to the left and right channels.
Converts PCM data to an error-correctable code structure,
It also performs time axis compression processing to form a data missing period corresponding to a vertical blanking period in a video signal, and further performs processing to add a synchronization signal corresponding to a vertical synchronization signal and a horizontal synchronization signal. In this example, a parity code and interleave are used as error-correctable code structures, as will be described later. The decoder 17 performs error correction processing and time axis expansion processing.
Deinterleaving is performed for error correction.

FIG. 2 shows an example of the encoder 14, in which PCM data regarding the stereo signals of the left and right channels is supplied from the input end 21, and is supplied to the distributor 22, and the PCM data regarding the left channel and right channel are supplied.
The PCM data series is divided into SL and SR. The PCM data for the left channel is, for example, a series of 1 word Li with a length of 14 bits, and similarly the PCM data for the right channel is a series of 1 word Ri with a length of 14 bits. One word each is taken out from the PCM data series of these left and right channels and supplied to the adder 23 (mod.2) to form a parity data series SP consisting of a 14-bit parity word Pi (=LiRi). Ru. FIG. 4A emerges from the divider 22 and adder 23.
It shows the series of PCM data and parity data. These three sequences are interleaved by being delayed for different times. The left channel PCM data series is supplied as is to the synthesizer 25, and the right channel PCM data series is supplied as is to the synthesizer 25.
The data series is sent to the synthesizer 2 via the delay circuit 24a.
5, and the parity data series is supplied to a combiner 25 via a delay circuit 24b. The delay amounts of the delay circuits 24a and 24b are selected to have a difference of D and 2D (block time), respectively. As an example (D=2 block time)
Then, the time relationship of each interleaved data series is as shown in FIG. 4B. For each interleaved data sequence, three words occupying the same timing are processed by the CRC generator 26.
CRC code as an error detection code
A CRC code sequence SC consisting of C ₀ , C ₁ , C ₂ . . . is formed. This CRC code sequence SC is also
supplied to CRC (Cyclic Redundancy)
Check) is a type of error detection using cyclic codes.
Each bit of the code to be detected is used as a coefficient.
The polynomial on GF2 is divided by the generator polynomial, the remainder is added to the transmission code as a CRC code, and on the receiving (or reproducing) side, the presence or absence of errors is checked by dividing the transmission code and CRC code by the generator polynomial. It is.

The output terminal 27 of the synthesizer 25 has a PCM serialized for each transmission block as shown in FIG. 4C.
A signal (including a parity code for error correction and a CRC code for error detection) appears, and although not shown,
A synchronization signal similar to a television signal is added in a synchronization mixing circuit. A data missing period corresponding to the vertical blanking period in a television signal is provided, but even if both the time axis compression and the delay for the above-mentioned interleaving processing are performed using RAM (random access memory). good.

Further, the decoder 17 is configured as shown in FIG. PCM data from the synchronization separation circuit 16 is supplied from an input terminal 28 to a distributor 29, and each transmission block is divided into four sequences SL, SR ₁₁ , SP ₁ and SC. 2 words of PCM for each transmission block
The data, one word of parity data, and the CRC code are supplied to the CRC checker 30, which detects the presence or absence of errors in the transmission block.The one-bit pointer that is the result of the detection is sent to each word as shown in the path shown by the broken line. It is added every time. Distribution circuit 2
The time relationship of the reproduced data on the output side of 9 is similar to that shown in FIG.
The playback PCM data for the right channel is delayed by D (block time). The playback parity data is
Due to this deinterleaving, the time relationship of the reproduced data at the input side of the error correction circuit 32 becomes similar to that shown in FIG. 4A. In the error correction circuit 32, a syndrome is formed and a correction operation based on the syndrome is performed. Considering two words Li and Ri that form a certain parity word Pi,
If Pi is not mistaken, these two words Li,
If only one word of Ri is incorrect,
The syndrome can correct that error. The data regarding the left and right channels from the error correction circuit 32 is supplied to the correction circuit 33, and the output of the correction circuit 33 is supplied to the synthesis circuit 34, where it is made into one channel and guided to the output terminal 35.

Interleaving and deinterleaving have the advantage of minimizing the occurrence of two-word errors, and are effective against burst errors.
As an example, regarding the reproduced data, [L ₀ ,
Two consecutive sequences of R _-2 , P _-4 ] and [L ₁ , R _-1 , P _-3 ]
If one transmission block is detected as erroneous by the CRC codes C ₀ and C ₁ , then as a result of the deinterleaving process, these erroneous words are dispersed and, assuming there are no other errors, they are all 1. It becomes possible to correct a word error. Second
The burst correctable length when using the encoder and decoder shown in FIG. 3 and FIG. 3, respectively, is D (block time). In addition, the correction circuit 33 corrects erroneous words that cannot be corrected in the error correction circuit 32. The correction circuit 33 can correct erroneous words that cannot be corrected in the error correction circuit 32. There is a previous value hold that uses the level of the correctly located word as is.

As mentioned above, VTR1 and PCM signal processing device 2
When operating in combination with
When the VTR 1 is stopped from the state in which the reproduced PCM signal from the VTR 1 is being supplied to the PCM signal processing device 2, the connection state of the changeover switch 6 is automatically changed, and its input terminal 7b and output terminal 7c are connected. Ru. For example, if a microphone output is supplied to the analog input terminal 11 because the A/D converter 13, encoder 14, and video amplifier 15 of the PCM signal processing device 2 are operating, this microphone output is PCM-modulated. Since the PCM signal of the different type appears at the video output terminal 8 after the terminals 7b and 7c of the selector switch 6 are connected, the PCM signal is output as a PCM signal. A video input 10 of the processing device 2 is supplied. As shown in FIG. 5A, the reproduced video signal #1 of the VTR 1 is supplied to the video input terminal 10 until the timing indicated by t ₀ , and the changeover switch 6 is switched after passing through the signal loss section indicated by diagonal lines from t ₀ . , other video signal #2 as shown by the dashed line
is supplied to the video input terminal 10.

Due to the signal loss shown by this diagonal line, (D>d)
When a data error with the length of d block occurs, the PCM data series SL ₁₁ , SR ₁₁₁ with the relationship as shown in FIG. and parity data series SP ₁ are obtained, which are supplied to the error correction circuit 32. Therefore, in the period from timing t ₀ to 2D corresponding to the connection position, data #1 and data #2 coexist.
In this case, if there is no error other than signal loss,
CRC checker 30 error detection result (pointer)
is “1” when there is an error, so the detection output is the OR output of the pointer of each channel.
SD becomes as shown in FIG. 5C. The inverted detection output is shown in FIG. 5D.

Further, in conjunction with the error correction circuit 32, a syndrome is generated for correction. The syndrome is obtained by adding (mod.2) two words of PCM data and one word of parity data included in the same block as a result of deinterleaving. If there is no error, all bits of the syndrome will be "0". Furthermore, as described above, in a section where different types of PCM data and parity data coexist, all bits of the syndrome rarely become "0". Syndrome signal SS that becomes “1” when even this one bit is “1”
is shown in FIG. 5E. Then, when the AND output of the detection output and the syndrome signal SS is obtained, the result is as shown in FIG. 5F.

The period indicated by (t ₁ to t ₂ ) in Fig. 5 is the PCM
Since only the data series SR ₁₁₁ has a one-word error, the error correction operation is attempted to be performed using the correct words contained in the other PCM data series SL ₁₁ and parity data series SP ₁ . t ₁ after t ₀
Data errors in earlier sections are errors in parity data and are not corrected.
However, while parity data series SP ₁ was included in video signal #2,
Since the PCM data series SR ₁₁₁ and SL ₁₁ were included in the #1 video signal, if an error correction operation is performed using these different types of data, abnormal data that is far different from the original will be generated. Error correction circuit 3
2, and when this is D/A converted, it becomes a harsh noise. The occurrence of abnormal data due to error correction using such different types of PCM data can be detected by the rising edge of the AND output shown in _{FIG .} This can be prevented by prohibiting error correction operations in the section or blocking the transmission of PCM data.

However, in cases where there are multiple data errors before the connection point, the above method alone cannot solve the problem.
Unable to prevent abnormal noise from occurring. FIG. 6 shows such an example. As shown in FIG. 6A, signal loss occurs before and after the connection point, and after the connection point t ₀ the signal disappears as described above (D>d ₂ ), and a burst error _d1 occurs before the connection point _t0 .
When the data series including this burst error is deinterleaved, a relationship as shown in FIG. 6B is obtained. Therefore, the detection output SD and are respectively,
6C and D, the syndrome signal SS is as shown in FIG. 6E, and the AND output (.SS) is as shown in FIG. 6F. Here, in the interval (t ₁ to _{t 2} ) after the connection point t ₀ and before the AND output becomes "1", only the PCM data series SR ₁₁₁ has an error, and a correction operation is performed, causing an abnormality. Data will appear.

Further, even when signal loss occurs randomly and data errors caused by deinterleaving overlap each other, the above-described method cannot prevent abnormal data from occurring. FIG. 7A shows a case where signal loss randomly occurs before and after the connection point _t0 , and when deinterleaving is performed, each data series becomes as shown in FIG. 7B. The data error sections shown in the shaded area overlap each other, and the detection output
SD and remain at "1" or "0" as shown in FIG. 7C and D, respectively, and the syndrome signal SS and the detection output shown in FIG. 7E have the same waveform. For this reason, the AND output (.SS) does not become "1" in the section from connection point _t0 to _t3 , making it impossible to prevent abnormal data from occurring.

Furthermore, when a data error of length d satisfying the condition (D≦d<2D) occurs due to signal loss after the connection point as shown in FIG. 8A, the deinterleaved data sequence is As shown in B, the data error sections of each series are continuous, resulting in a waveform and detection output SD similar to the syndrome signal SS shown in FIG. 8E. For this reason,
The correction operation at (t ₁ to _{t 2} ) causes abnormal noise. This cannot be detected and prevented by using the AND output of the detection output and the syndrome signal SS. Note that the data error interval is
If it is 2D or more, it becomes a 2-word error and cannot be corrected, so abnormal data will not occur.

An object of the present invention is to provide a PCM signal processing device that reliably prevents abnormal noises caused by the above-mentioned causes. Further, the present invention is suitable for use when coupled to an existing VTR as an adapter, as in the configuration shown in FIG. In other words, the present invention eliminates the need to receive a system control signal or a special discrimination signal from the VTR side on a separate line.
This system is designed to prevent abnormal noise from occurring by using only the PCM signal.

In addition, in the above explanation, it was explained that the signal loss occurs due to the transient of the changeover switch 6, but at the same time, data loss may also occur because the phase to which the abnormal PCM signal is connected is not regulated at all. An error will occur.

An embodiment of the present invention will be described below with reference to FIG. In this example, the VTR
The present invention is applied to a decoder 17 included in a PCM signal processing device 2 connected to the PCM signal processing device 1. The pointer appearing in the output of the CRC checker 30 is the left channel PCM data series SL,
It occurs at the end of each block of the right channel PCM data series SR ₁₁ and parity data series SP ₁ , and becomes "1" when an error is detected and "0" when no error is detected. . In FIG. 9, the transmission paths for data and pointers are shown separately, but the pointer that appears at the output of the CRC checker 30 is a pulse-like one located at the end of each block, and is then deinterleaved. Later, the pointer is converted and transmitted so that it lasts for the length of each one block period.

The output of CRC checker 30 is AND gate 36
and a retrigger type monostable multivibrator (abbreviated as monomulti) 37. The output Pm of the monomulti 37 is supplied to an AND gate 36, and the pointer passed through the AND gate 36 is counted by a counter 38. The counter 38 is cleared while the output Pm of the monomulti 37 is "0". The counter 38 sets the pointer to N
When counting, a carry output is generated by CA. Since one pointer is generated in one block period, and the unit delay amount of interleaving and deinterleaving is set to D block periods, a carry output CA is generated even when (N=D). A monomulti 39 that is triggered by this carry output CA is provided, and a control pulse P _c2 that is "1" for a period of 2D after the carry output CA is generated is formed. This control pulse P _c2 is supplied to the OR gate 40 together with the control pulse P _c1 .

Further, each data series SL ₁₁ , SR ₁₁₁ , SP ₁ after being deinterleaved is delayed by D by each of the buffer memories 41a, 41b, 41c. Of course, the delay amount for deinterleaving may be 3D, 2D, or D. Then, a pointer (as mentioned above, this is a signal that continues for one block period) is taken out from each of the outputs of the buffer memories 41a, 41b, and 41c and is supplied to the NOR gate 42, which outputs a detection output.
SD occurs. At the same time, three words extracted from each deinterleaved data series are supplied to the syndrome forming circuit 43, and the syndrome is supplied to the error correction circuit 32 together with the data. Furthermore, when even one bit of the syndrome becomes "1", a syndrome signal SS is generated which remains "1" for one block period, and the syndrome signal SS
and the detection output are supplied to the AND gate 44. A monomulti 45 is provided which is triggered by the output of the AND gate 44, and a control pulse P _c1 which becomes "1" in the section D from the fall of the output of the AND gate 44 is generated. This control pulse P _c1 is supplied to the OR gate 40.

When either the control pulse P _c1 or P _c2 generated from the OR gate 40 becomes “1”, the error correction circuit 3
2 corrective action is prohibited. In the error correction circuit 32, if there is a one-word error in one block using a syndrome, a correction operation is performed and a pointer related to the corrected word is cleared. When the above-mentioned control pulse P _c1 or P _c2 is "1", this correction calculation operation and pointer clear operation are prohibited. Then, a correction circuit 33 performs a previous value hold correction operation in which a word that cannot be corrected by the error correction circuit 32 is replaced with, for example, a previous correct word. In this example, the correction circuit 33 is configured to automatically perform a correction operation when error correction is impossible. If not, the output of the OR gate 40 is supplied to the correction circuit 33 as shown by the broken line path, and the control pulse P _c1 or
It is configured to perform a correction operation when P _c2 is "1".

Note that before deinterleaving, buffer memories 41a, 41b, and 41c are provided to control pulses.
P _c2 may be added as a pseudo pointer to the parity data series or the PCM data series to convert the data error interval to 2D or more. Or,
When the output of the OR gate 40 becomes “1”,
The transmission of PCM data may be blocked.

The operation of the embodiment of the present invention described above will be explained. First, as shown in Figure 5 above,
When a data error of less than D occurs later from the connection position of the PCM signal, the fifth
A detection output similar to that shown in FIG. D is generated, and a syndrome signal SS similar to that shown in FIG. E is generated from the syndrome forming circuit 43. Therefore, the AND gate 44 generates an output similar to that shown in _{FIG .
1} occurs. This control pulse P _c1 inhibits the error correction operation in the error correction circuit 32,
It is possible to prevent abnormal noise from occurring in the section corresponding to (t ₁ to _{t 2} ).

Now, as explained with reference to FIG. 7, when a random data error occurs before and after the connection point t ₀ and deinterleaving is performed, when the data error section in each data series is continuous, the control pulse P _c1 does not occur. As an example, assuming (D=8 block periods), consider a case where a data error (indicated by diagonal lines) as shown in FIG. 10A occurs. The output of CRC checker 30 is
Corresponding to each error block, the error occurs as shown in FIG. 10B. In addition, the monomulti 37 is triggered by the output of the CRC checker 30 that occurs first, and by being retriggered, the monomulti 37 is
The output Pm shown in is generated. T _M is a delay time determined by the time constant of this monomulti 37. When eight outputs of the CRC checker 30 are counted by the counter 38, the carry output CA shown in FIG _. D
From the delayed t ₀ ', a control pulse P _c2 which becomes "1" is generated as shown in FIG. 10E. Since each data _series is delayed by D by the buffer memories 41a, 41b, and _41c , different types of PCM are
It is possible to prevent abnormal data from occurring in a section where data is mixed (section from _t0 to _t2 in FIG. 7).

Furthermore, as shown in Fig. 6, abnormal data may occur due to data errors occurring before and after the connection point _t0 , or as shown in Fig. 8 (D
The occurrence of abnormal data due to the occurrence of a data error of length ≦d<2D can also be prevented in the same manner as described above.

FIG. 11 shows the main part of another embodiment of the present invention, in which the output of the CRC checker 30 and the output delayed by D by the delay circuit 46 are supplied to the OR gate 47. The output is counted by a counter 38.
The counter 38 generates a carry output CA when it counts the number of pointers indicating errors corresponding to D, and the control pulse P _c2 is formed by triggering the monomulti 39 with this carry output CA. . This control pulse P _c2 performs the same control as in the above-mentioned embodiment. counter 38
has a delay time slightly longer than one block period, and is cleared when the output of the monomulti 48 triggered by the output of the OR gate 47 becomes "0". The other configurations are the same as in FIG. 9.

In this manner, other embodiments of the present invention using the delay circuit 46 of D can also effectively prevent the occurrence of abnormal data that occurs in the manner shown in FIG. 7 or FIG. 8.

As can be understood from the description of the embodiments described above, according to the present invention, abnormal noise is generated when the VTR changes from a state in which a PCM signal processing device is connected to a VTR and is playing back PCM to a stop operation. This can be reliably prevented. If VTR system control signals and the like can be separately supplied to the PCM processing device, it is possible to similarly prevent the occurrence of abnormal noise. However, the need for such a separate signal transmission line causes disadvantages such as detracting from the advantage of being able to easily add a PCM signal processing device to a VTR using an adapter configuration. According to the present invention, there is an advantage that generation of abnormal noise can be prevented using only the reproduced PCM signal.

Another encoding method to which the present invention can be applied will be explained with reference to FIG. 12 and subsequent figures. FIG. 12 shows an encoder, which is distributed by a distribution circuit 22a into PCM data series SL and SR of left and right channels, and these left and right channels are divided by a distribution circuit 22b into a total of 6 channels, 3 channels each. . For example, L _-2 , L _-1 , L ₀ , L ₁ , L ₂ , L ₃ ...
...and the PCM data series SL and R _-2 , R _-1 , R ₀ ,
The PCM data series SR continues as R ₁ , R ₂ , R ₃ , ..., the PCM data series SL ₁ of the first channel continues as (L _-2 , L ₁ , L ₄ ...), and (R _-2 , R ₁ , R ₄
...), the PCM data series SR ₁ of the second channel continues, the PCM data series SL ₂ of the third channel continues, (L _-1 , L ₂ , L ₅ ...), and (R _-1 ，
R ₂ , R ₅ ...) and the fourth channel
PCM data series SR ₂ and PCM data series SL ₃ of the fifth channel (L ₀ , L ₃ , L ₆ ...)
and (R ₀ , R ₃ , R _{6 .} . . ) and the subsequent PCM data series SR ₃ of the sixth channel.

One word of the PCM data series of each channel is supplied to the (mod.2) adder 23 to form the first parity data series SP, and the adjacent encoder 49 is supplied with
A second parity data series SQ is formed by supplying each word of the PCM data series.

For other channels except PCM data series SL ₁
The PCM data series SR ₁ , SL ₂ , SR ₂ , SL ₃ , SR ₃ are supplied to the delay circuits 24a to 24e, the first parity signal series SP is supplied to the delay circuit 24f,
The second parity signal series SQ is supplied to the delay circuit 24g. The delay circuits 24a to 24g are PCM
The delay circuits 24a to 24g are for temporally interleaving the data series and the first and second parity data series, and when the unit delay amount is D (block time), the delay circuits 24a to 24g are D, 2D, 2D, and 24g, respectively. 3D,
It is assumed that the delay amount is 4D, 5D, 6D, or 7D (block time). Delay circuits 24a to 24e
PCM data series SR ₁₁ delayed from the husband of
SL ₁₂ , SR ₁₂ , SL ₁₃ , SR ₁₃ occur, and the delay circuit 24
Delayed parity data sequences SP ₁ and SQ ₁ result from f and 24g, respectively. The PCM data series for 6 channels obtained in this way SL ₁ ~
Eight words are extracted from SR ₁₃ and parity data sequences SP ₁ and SQ ₁ and supplied to a CRC generator 26 to generate a CRC code for these eight words, and form a CRC code sequence SC consisting of these CRC codes.

The above PCM data series SL ₁ to SR ₁₃ , parity data series SP ₁ , SQ ₁ , and CRC code series SC are supplied to the synthesis circuit 25 to form a one-channel PCM signal series, which is further illustrated in the figure. The signal is also supplied to the time base compression circuit. At the output terminal of the time axis compression circuit, a signal sequence having a data missing period corresponding to the period in which the synchronization signal is added appears. In this case, six words of PCM data, two words of parity data, and a CRC code are located within one horizontal section. As an example, each delay circuit 2
PCM of (R ₁ , L ₂ , R ₂ , L ₃ , R ₃ ) in 4a to 24g
At the timing when the data and the parity data of P ₁ and Q ₁ are supplied, (R _1-3d , L _2-6d , R _2-9d , L _3-12d , R _{3- 15d} )
PC data and parity data of P _1-18d and Q _1-21d are generated at the outputs of delay circuits 24a-24g. The output signals of these delay circuits 24a to 24g and L ₁
A CRC code _C1 for a total of 8 words is formed.

The PCM signal generated by the encoder mentioned above is
As shown in FIG.
Data, two words of parity data, and a CRC code are arranged in sequence. In this example,
One word is 14 bits long.

FIG. 14B shows a signal waveform recorded and reproduced by a VTR.
The data 51 and the white level reference signal 52 shown in FIG. 1 are inserted into the waveform.

FIG. 13 shows a decoder corresponding to the above-mentioned encoder, in which data from the input terminal 28 is sent to a distribution circuit 29 into a 6-channel PCM data series SL ₁ , SR ₁₁ , SL ₁₂ , SR ₁₂ , SL ₁₃ ,SR ₁₃ ,
It is divided into SP ₁ , SQ ₁ and CRC code series SC, and error detection is performed by CRC checker 30 for each transmission block, and the detection result (pointer) is added to each word and sent to delay circuits 31a to 31g. Deinterleaving processing is performed using . After this deinterleaving, an error correction circuit 32 performs error correction, a correction circuit 33 further corrects the PCM data series, which is returned to one channel by a synthesis circuit 34, and appears at an output terminal 35.

Error correction in the above example will be explained. As an example, from the distribution circuit 22b L ₁ , R ₁ , L ₂ , R ₂ , L ₃ ,
When 6 words of R ₃ are generated, adder 23
The first parity data P ₁ generated from is P ₁ = L ₁ R ₁ L ₂ R ₂ L ₃ R ₃ , and the second parity data Q ₁ is Q ₁ = T ⁶ L ₁ T ⁵ R ₁ T ⁴ L ₂ T ³ R ₂ T ² L ₃ TR ₃ . The generation matrix T is formed by a d-order generation polynomial G(X) such that the same one does not appear in each of T, T ² , T ³ , T ⁴ , T ⁵ , and T ⁶ in the above equation. be.

Further, in the error correction circuit 32 of the decoder, the first
forming a syndrome based on parity data and a syndrome based on second parity data,
Error correction is performed by using syndromes based on the first and second parity data. By identifying the erroneous word using CRC, it is also possible to correct two-word errors within the same block. Therefore, the burst correctable length when using the encoder and decoder shown in FIGS. 12 and 13 is 2D (block time).

As described above, the present invention can also be applied to an encoding method in which a PCM data sequence is divided into six channels and uses first and second parity signals. FIG. 15A shows each deinterleaved signal sequence, and the solid line series in FIG. 15 is the data sequence included in the video signal #1, and the dashed line series is the data series included in the video signal #2. Each data sequence is expressed based on the parity data sequence SQ ₁ that has not been delayed during deinterleaving. If a data error with a length less than D, for example 1/2D, occurs as shown in the hatched area, the detection output shown in FIG. 15B can be generated in the same manner as described above. Also, the first
Syndrome signal SS ₁ based on parity data of
As shown in FIG. 15C, becomes "1" with a delay of D from the connection position, and the syndrome signal _SS2 based on the second parity data becomes "1" from the connection position, as shown in FIG. 15D. becomes. These syndrome signals SS ₁ and SS ₂ become "0" when 1/2D is added to the period in which different types of PCM data are mixed.

By supplying one syndrome signal, for example SS ₁ , and the detection output to the AND gate, the output shown in FIG. 15E can be obtained from the AND gate. By triggering the monomulti at the first rise of the output of this AND gate, a control pulse P _c1 that becomes "1" during a period in which different types of PCM data are mixed is formed, as shown in FIG. 15C. During the period of "1" of this control pulse P _c1 , error correction operation is prohibited or transmission of PCM data is interrupted.

D after the point where different PCM data are connected
The error correction operation in each of the periods TD ₁ to TD ₈ of each length is as follows.

TD ₁ , TD ₂ : There is no need for correction as these are parity data errors.

TD ₃ , TD ₄ , TD ₅ , TD ₆ , TD ₇ : A correction operation using different types of PCM data is performed due to a one-word error, and there is a possibility that abnormal data may be generated.
However, the correction operation is prohibited by the control pulse P _c , eliminating such a fear. Error words included in these periods are corrected by the correction circuit 33 at the next stage.

TD ₈ : PCM included in #2 video signal
Since there is only data, a normal correction operation is performed.

As is clear from this Figure 15, the first and second
Since it has parity data of 1, it is possible to generate two syndrome signals SS ₁ and SS ₂ . Therefore, the syndrome signal SS ₁ and the detection output
When detecting using SD, abnormal noise may occur if the data error sections of each series overlap after deinterleaving, resulting in two word errors within one block. Therefore, a 2-word error is detected by taking the AND output of the current output of the CRC checker 30 and its 1D previous output, and a counter is used to determine that this 2-word error continues N (=D) times. All you have to do is detect it. Another configuration is similar to that shown in FIG.
It is also possible to detect (=2D) consecutive occurrences using a counter.

As mentioned above, other embodiments of the invention also include
When the PCM signal is connected, it can prevent the occurrence of abnormal data, and it can also be used for playback.
There is an advantage that there is no need to use control signals other than PCM signals.

Note that the present invention may be applied to other methods that use a parity check as an error detection code or a full addition code as an error correction code.

Also, the phase where different types of PCM signals are connected is
generally not regulated. FIG. 16A shows, for example, the video signal #1, and FIG. 16B shows the #2 video signal.
, and the two are out of phase. These video signals have a data lack period DBL including a vertical synchronization signal VD and the like and a data period DTP as periods of one field (1V). In the first horizontal interval immediately before the data period DTP,
A pilot signal PS is inserted as shown by diagonal lines. The pilot signal PS has the same transmission signal form as the data shown in FIG. 4C or FIG. 14A. When deinterleaving the #1 video signal, write gate pulse WGP as shown in Figure 16C is used to separate the data period.
Write operations to RAM are performed only by DTP, and normally pilot signal PS is not written to RAM.

However, if the two video signals are connected at _t0 , the video input terminal 10 of the PCM signal processing device 2 will be supplied with a video signal as shown in FIG. 16D. As already mentioned, there is a possibility that an abnormal noise may be generated due to a data error near this connection point t ₀ . In addition to this, abnormal noise may also be caused by the pilot signal PS being treated as data. In other words, when a video signal as shown in FIG. 16D is supplied, the write gate pulse WGP is
6 As shown in Figure E, the vertical synchronization signal of the #2 video signal is synchronized with the previous #1 video signal.
After VD is obtained, it will be synchronized to the #2 video signal, and the data missing period DBL period will also be synchronized.
It will be written to RAM.

The vertical synchronization signal VD, etc. is determined by the CRC check result.
The pilot signal PS, which is detected as erroneous, is detected as correct if there is no transmission error. Since the pilot signal PS is determined to be a predetermined value regardless of the PCM data, there is a risk that abnormal noise will occur when it is D/A converted.

An example configuration for preventing this is shown in FIG. 17. A pilot signal detection circuit 53, an AND gate 54, and an OR gate 55 are additionally provided to the configuration shown in FIG. Pilot signal detection circuit 53
When a signal matching a predetermined bit pattern is detected from the video signal from the input terminal 10,
This is detected as a pilot signal PS. This detection output and the control pulse P _c2 formed in the same manner as described above are supplied to an AND gate 54, and the output of the AND gate 54 is supplied together with the output of the CRC checker 30 to an OR gate 55.

As mentioned above, when the control pulse P _c2 becomes "1", the correction operation is prohibited and the correction operation is performed. Therefore, in such a case, when the pilot signal PS is detected, the pseudo pointer appearing from the AND gate 54 on the output side of the buffer memories 41a, 41b, and 41c forces the erroneous data to be Convert to In this way, the pilot signal PS can be set to the correct PCM.
It is possible to prevent abnormal noises from occurring as a result of mistaking the information for data and using it for correction or correction.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of a PCM signal processing device to which the present invention can be applied, FIGS. 2 and 3 are block diagrams of examples of its encoder and decoder, and FIGS. 4, 5, 6, 7 and 8 are schematic diagrams used to explain the operation of the encoder and decoder,
FIG. 9 is a block diagram of an embodiment of the present invention, and FIG.
The figure is a time chart used to explain one embodiment of the present invention, FIG. 11 is a main block diagram of another embodiment of the present invention, and FIGS. 12 and 13 are diagrams of an encoder and a decoder to which the present invention can be applied. FIG. 14 is a block diagram of another example, and FIG. 14 is a schematic diagram showing transmission waveforms of another example of this encoder 14 and decoder. FIG. 15 is a schematic diagram used to explain another example of this encoder and decoder. FIG. 16 is a time chart used in still another embodiment of the present invention, and FIG. 17 is a block diagram of the main part of still another embodiment of the present invention. 1 is a VTR, 2 is a PCM signal processing device, 6 is a changeover switch, 14 is an encoder, 17 is a decoder,
23 is a (mod.2) adder, 24a to 24g are delay circuits for interleaving, 26 is a CRC generator,
30 is a CRC checker, 31a to 31g are delay circuits for deinterleaving, 32 is an error correction circuit,
33 is a correction circuit, 37 is a re-trigger type monomulti, 38 is a counter, and 43 is a syndrome forming circuit.

Claims (1)

[Claims] 1 Performs interleaving processing to delay PCM data and the error correction code for this PCM data by different times, forms blocks and transmits them, performs error detection on the receiving (or reproducing) side, and performs deinterleaving processing to cancel the delay. In a PCM signal processing device that performs error correction and error correction, a second different type of signal is
An error detection means that generates an output pulse when an error in each block is detected on the reception (or reproduction) side to which the PCM signal is supplied via the signal error section, and according to the unit delay amount for the interleaving and deinterleaving described above. counting means for counting the output pulses of the error detection means for a predetermined period of time, and generating an output signal when the count value reaches a predetermined value; and for prohibiting the error correction operation for a predetermined period by the output signal of the counting means A PCM signal processing device comprising a prohibition means to prevent abnormal data from occurring due to an error correction operation using different types of PCM data included in each of the first and second PCM signals.