JPS63292359A - Serial bus control circuit - Google Patents

Abstract

PURPOSE:To realize the parallel control of plural peripheral devices by using a serial bus divided into plural fields for each peripheral device to connect a central control unit and those peripheral devices in both directions where the ascending transmission direction from the central control unit is paired with the descending reception direction to the central control unit respectively. CONSTITUTION:1st-3rd peripheral devices 31-33 include 1st-3rd bus correspondence parts 51-53 which fetch the control data and send back the answer signals, and 1st-3rd processing parts 41-43 which process the control data respectively. In both ascending and descending direction states, three fields are prepared in response to the devices 31-33 respectively. Each field includes a 1-bit control signal, the N-bit control data and an answer signal and each bus correspondence part can fetch only its own field. Then a control bus 2 is switched alternately in a fixed cycle between the ascending and descending states. As a result, the control waiting time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control circuit in a communications switching network or an information processing device, and more particularly to a bus control circuit for controlling a plurality of peripheral devices.

(Prior Art) Conventionally, this type of bus control circuit connects a central control unit and a plurality of peripheral devices using a plurality of control buses consisting of an address bus, a data bus, and a control S signal. A device number is given to each peripheral device to distinguish it from one another, and each peripheral device is provided with a bus corresponding section for identifying its own device number.

Each central controller sends a device number signal on the address bus, a data signal on the data bus, and a control signal on the control bus.

The peripheral device reads the 9 device number signal sent by the bus corresponding section and inputs its own device number, and when the control signal indicates validity, it also receives the 9 device number signal sent from the central control device.
9. Takes in data signals and executes processing.

When processing of the data signal is complete, the peripheral device switches the data bus in the opposite direction toward the central controller and sends a response signal back to the data bus. When the central control unit reads the response signal, it finishes controlling one peripheral device and starts controlling the next one.

(Problems to be Solved by the Invention) In the conventional bus control circuit described above, the control bus is composed of a plurality of address buses, a data bus, and a control bus, and a plurality of peripheral devices are connected to the device via the address bus. It receives the number signal, takes in the data signal sent from the data bus, and executes the processing only when it is its own device number and the control signal is valid.

9. Since the configuration is such that control of other peripheral devices is proceeded after the processing of the data signal is completed and a response signal is sent back to the central control signal, the peripheral device specified by the device number signal The disadvantage is that peripheral devices other than those specified cannot be controlled until the specified peripheral device has been controlled.

In particular, when a peripheral device that takes time to process data signals is being controlled, control of other peripheral devices has to wait for a long time.

Furthermore, the conventional bus control circuit described above has the disadvantage that a plurality of control buses must be connected.

The object of the present invention is to:
A pair of two-way terminals are provided in the direction of reception to the central control unit.
A serial bus control circuit constructed of a serial bus divided into individual fields for each of a plurality of peripheral devices and equipped with 91 control buses to eliminate the above-mentioned drawbacks and shorten control waiting time. Our goal is to provide the following.

(Means for Solving the Problems) A serial bus control circuit according to the present invention includes a plurality of peripheral devices, a central control device, and a serial control bus.

Each of the plurality of peripheral devices includes a bus corresponding section that can recognize itself based on control data and send back a response signal, and a processing section that executes processing of the control data.

The central control device is a type of device that controls a plurality of peripheral devices by alternately switching between sending control data and receiving response signals in a time-sharing manner.

A serial-type control bus connects a central controller and multiple peripheral devices, and is bidirectional with upstream transmission from the central controller and downstream transmission to the central controller. It is used to transmit time-divided individual fields like peripheral devices.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a serial bus control circuit according to the present invention. In FIG.
The processing units 51 to S3 are IEI to eighth bus corresponding units, respectively.

FIG. 1 shows a central control device 1 and first to eighth peripheral devices 4.
1 to 43 are connected by one control busco.

The first to eighth peripheral devices 41 to 43 each have an IEI to an eighth peripheral device that takes in control data and returns a response signal.
bus corresponding units 81 to B3, and IIEI to eighth processing units 41 to 43 that execute control data processing are provided, respectively.

FIG. 2 is an explanatory diagram showing data formats of the control bus 2 in FIG. 1 in the upstream and downstream directions from the central control device 1. 8 corresponding to the 1st to ms and peripheral devices 31 to 33, respectively, both in the upward direction and in the downward direction.
It is divided into fll fields, and each field consists of one pit of control signal and N pits (N: !1 number) of control data and response signals, and each bus corresponding part can only take in its own field. is configured to allow
The control bus 2 is configured to alternately switch between upper and lower positions at regular intervals.

The control operation will be described below with reference to FIG. 1 and FIG.

For example, when the central controller 1 is in the upper direction, the control signal for the first peripheral device field of the control busco is enabled 1.
It shall be 1#. When the control data is sent at this time, the I! of the first peripheral device 31 is transmitted! The bus corresponding unit s1 of El confirms that the control a signal of its own field is valid %1#, takes in the control data, and executes the process by the first processing unit 41. When the processing of the data signal by the first processing section 41 is completed, the first bus corresponding section 81 returns a response signal with the control signal as valid 111 to the first peripheral device field in the downstream direction of the control bus 2. be done.

During processing of control data from the first processing unit 41, the control signal is set to valid %11 in the peripheral device field of the control bus 2 in the next upstream direction from the central control unit 1, and when the control data is sent, the second Bus compatible part S of wt2 of the peripheral device 32 of
In step 2, it is confirmed that the control ll@ number of its own field is valid %1#, the control data is taken in, and the second processing section 82 executes the process.

(Effects of the Invention) As explained above, the present invention connects a central control device and a plurality of peripheral devices by pairing the uplink in the sending direction from the central control device and the downlink in the receiving direction to the central control device. By connecting with a serial bus that is bidirectional and divided into multiple individual fields for each peripheral device, the advantage is that multiple peripheral devices can be controlled in parallel, and there is also a single KfllOil bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a serial bus control circuit according to the present invention. FIG. 112 is an explanatory diagram showing the format of data used in the control bus of FIG. 1. 1...Central control unit 2...Control buses 31-33...Peripheral devices 41-43---Processing units 51-S3...Bus corresponding unit

Claims (1)

[Claims] A plurality of peripheral devices constituted by a bus corresponding section that can each recognize itself based on control data and send back a response signal, and a processing section that executes processing of the control data, and a plurality of peripheral devices that transmit the control data. a central control device for controlling the plurality of peripheral devices by alternately switching reception of the response signal in a time-sharing manner; and a central control device for connecting the central control device and the plurality of peripheral devices; a serial-format control bus for bidirectionally transmitting individual fields time-divided for each of the peripheral devices by pairing an uplink in the sending direction from the device and a downlink in the receiving direction to the central control device; A serial bus control circuit comprising: