JPS63291467A - Manufacture of hetero-junction bipolar transistor - Google Patents

Abstract

PURPOSE:To improve the rapidity of a hetero junction bipolar transistor by forming an in layer between a GaAs layer and an InAs layer, and heat treating it in an As atmosphere to form a very preferable grading layer, thereby remarkably reducing a contact resistance. CONSTITUTION:A grading layer of an extremely thin In layer 107 is formed on an AlGaAs/GaAs layer 105 which constitutes an emitter layer, the layer is heated in an As atmosphere, an InGaAs layer 108 in which the molar ratio of InAs or In exceeds 0.5 is grown, and an ohmic contact is formed of a Ti/Au thin film on the layer 108. Thus, since its contact resistance is remarkably reduced, its rapidity can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a compound semiconductor.

(Prior Art) Heterojunction bipolar transistors using compound semiconductors, particularly GaAs, have attracted attention as next-generation high-speed devices and have been actively developed in recent years. FIG. 3 shows a layer-oriented heterojunction bibo-2 transistor (HBT) using an AjGaAs/GaAs heterojunction as an emitter-paste junction. Recent advances in MBE technology have made it possible to grow ultrathin film crystals. This has facilitated the growth of heterojunction bipolar transistors. However, compound semiconductors, particularly GaAs, have problems in forming ohmic contacts, and when HBTs are used to construct high-speed switching gates such as ECLs, the high ohmic contact resistance to the emitter greatly limits its performance. In order to construct an even faster circuit, it is necessary to reduce the ohmic resistance of the emitter! , conventionally used AuGe/Ni/Au
This requirement cannot be met by methods using alloys such as .

(Problems to be solved by the invention) With the conventional manufacturing method of heterojunction bipolar transistors, it was not possible to sufficiently lower the emitter contact resistance and to make full use of the high speed performance of heterojunction bipolar transistors in the midrange range. .

The present invention was made in view of these problems,
An object of the present invention is to provide a method for manufacturing a beterojunction bipolar transistor with improved high-speed performance.

[Structure of the invention]

(Means to Solve the Problem) In the present invention, the above problem can be solved by using AlG constituting the emitter layer.
After forming the entire K In layer on the aAs/GaAs layer and heating the top layer in an As atmosphere, an InGaAs layer with a molar ratio of In or In exceeding 0.5 is grown to make the ohmic resistance to the emitter extremely small. are doing.

(Function) Since the conduction band of n-type InAs is degenerated, no barrier potential is generated between the n-type InAs and the metal.

Contact resistance is therefore very small. Also, the molar ratio of In is 0
．． The same thing can be expected for InGaAs with a density exceeding 5.

However, GaAs and InAs or InGaAs
A heterojunction occurs between the two and a barrier potential is created. This barrier potential increases emitter resistance and reduces the meaning of forming an InAs or InGaAs layer on the surface. Therefore, in the present invention, Ga
An In layer is formed between the As and InAs layers, and this is heat treated in an As atmosphere to form a very good grading layer and to significantly reduce the contact resistance.

(Example) The present invention will be described in detail below using an AlGaAs/GaAs HBT as an example. FIG. 1 is a block diagram of a forward HBT embodying the present invention. As shown in this figure, a grading layer of an extremely thin In layer 107 is formed on the AlGaAs layer 105 constituting the emitter, and an n
A type InAs layer 108 is grown, and the InAs layer 10
An ohmic contact is made with a thin film of Ti/Au on top of 8.

Next, this embodiment will be explained in detail with reference to FIG.

After the semi-insulating GaAs substrate 101 is subjected to a well-known ordinary etching process, the GaAs substrate is mounted in a molecular beam crystal growth apparatus, and after preheating at 400° C., it is subjected to IX in a growth chamber.
While applying an arsenic beam of 10-' Torr, the temperature of the substrate was raised to 600°C and held for 30 minutes to increase the n of the GaAs substrate.
After removing aturaloxide, forward HBT was grown. The layer structure of HBT was grown in the following order (second
Cause (a)). Ga heem is 6 x 10-' Torr
, the substrate temperature is 580°C.

Further, the molar ratio of AJ is 0.3.

(Left below) 1 Job Job IIl Job -xxx xxx N Lee - Go to 1
Heli--10 After this, the temperature of the GaAs substrate was lowered to 450'O under an As beam, and after turning off the As beam, the temperature was lowered to 10~1 with an In flux of 107 x 10-'Torr.
5 atomic layers are formed on top of the GaAs emitter cap layer (Figure 2(b)'). Then, under the As beam, 520
Raise the temperature to °C and hold for 20 minutes. This forms an In grading layer. On top of this, Si was applied at 101 dopi with an In flux of 5 x 10' Torr and an As of 777 flux of 5 x 10' Torr.
An InAs layer 108 with a thickness of 30 OA was grown (Fig. 2
(C) ). Thereafter, using this substrate, the HBT element shown in FIG. 1 was fabricated by a well-known ordinary HBT process. At this time, ohmic contact 109 to the emitter
is Ti/ instead of the usual AuGe/Ni/Au 60.
Made using Au and non-alloy. H created in this way
The emitter resistance of an AT is, for example, several Ω for an emitter with a size of 2μ x 8μ, which has significantly decreased from around 50Ω, and in an ECL circuit configured with this element, Ni
The load resistance of Cr could be lowered to around 20Ω, and as a result, the switching time was 20γS, showing extremely high speed.

The present invention is also effective in reducing the collector resistance of reverse direction transistors.
It is also effective for As heterojunction bipolar transistors. Further, if the InAs layer has an In molar ratio of 0.5 or more, the contact resistance will be significantly reduced, so a similar effect can be expected.

〔Effect of the invention〕

According to the present invention, it is possible to provide a method for manufacturing a heterojunction bipolar transistor with improved high-speed performance.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an HBT produced by implementing the present invention, FIG. 2 is a diagram illustrating the present invention in detail, and FIG. 3 is a sectional view of an HBT according to the prior art. Agent Patent attorney Nori Ken Yudo Matsuyama Kosoku (a) Figure 2

Claims (2)

[Claims] (1) In a method for manufacturing an npn-type heterojunction bipolar transistor in which the base region is made of a semiconductor material with a smaller band gap than the emitter region, an In layer is formed on the top layer of the npn-type heterojunction layer using the MBE method. A step of stacking layers at a lower temperature than when forming a heterojunction layer, a step of heat-treating this In layer in an arsenic atmosphere at around the formation temperature of the heterojunction layer, and an InAs layer or a mol of In on the heat-treated In layer. A method for manufacturing a heterojunction bipolar transistor, comprising the step of forming a compound semiconductor layer having a ratio of more than 0.5 by an MBE method. (2) The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein the heterojunction is an AlGaAs/GaAs junction.