JPS63291464A - Switching device - Google Patents

Abstract

PURPOSE:To provide a switching device adapted for a memory cell which can be easily manufactured with a large capacity by forming a cooling semiconductor gate through an insulator on a superconductor on which electrodes are disposed at both ends, reducing the temperature of the face of the gate at a superconductor side to vary the temperature of the superconductor, thereby altering the conductivity of the superconductor. CONSTITUTION:When a word line 1 becomes a potential VDD, a potential difference of VDD is applied to a connecting material of both the ends of a semiconductor gate 4, and the lower surface of the gate 4 absorbs heat. Thus, the lower surface is cooled, and a high temperature superconductor 6 is cooled through an insulator film 5. When the temperature of the superconductor 6 falls from a T2 to a T1, its resistance is abruptly reduced from a very large resistance R to a resistance '0'. The temperature of the superconductor 6 drops from a critical temperature T0 to the temperature T1 lower than the T0 by this property, and the potentials of a bit line 2 and a capacity 3 are electrically conducted. Then, when the line 1 is set to a ground potential, the heat absorbing action of the lower surface of the gate 4 is stopped, the superconductor 6 becomes higher than the critical temperature, its resistance rises, and the line 2 and the capacity are insulated. This operation is repeated to operate as a storage element.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a switching device using superconducting materials and suitable for high-density memory or logic devices.

Conventional high-density memory devices mainly use semiconductor devices. That is, in dynamic RAM, 1
One memory cell consists of one MOS transistor and one capacitor.

Problems to be Solved by the Invention The distance between the source and drain of a MOS transistor, that is, the channel length, is a short channel effect.

Due to the flow channel effect, the current limit is about 0.3 μm, and for other areas, the limit is 50 μm due to the bunching effect.
There is a limit to realizing the switching characteristics of n and off.

Further, in a MOS transistor in a normal semiconductor integrated circuit, a step or the like exists in the gate portion, which prevents high density.

The present invention aims to solve all of these problems and to provide a switching element suitable for memory elements, logic circuit elements, etc., which has a large capacity and is easy to manufacture. This method uses a superconductor and a cooling semiconductor gate, and involves forming a cooling semiconductor gate (1) on the superconductor with electrodes arranged at both ends via an insulator, and passing a current through the gate.
This is a switching device that lowers the temperature of the superconductor side of the gate to change the temperature of the superconductor, thereby changing the conductivity of the superconductor.

The present invention forms a memory element in which an electrode at one end of the superconductor is connected to a charge storage capacitor, an electrode at the other end is connected to a bit line, and a semiconductor gate is connected to a word line.

According to the present invention, the semiconductor gate is cleaned at a low temperature, the superconductor's total critical temperature is changed from normal temperature conductivity to superconductivity, and the superconductor changes from a high resistance state to a resistance state where the resistance suddenly decreases to 0 resistance.
In turn, it becomes possible to realize a very simple switching device.

Embodiment FIG. 1 shows a switching element according to an embodiment of the present invention. Figure 1 shows dynamic random access memory (
DRAM). In FIG. 1, 1 is a word line in a DRAM and changes as a voltage signal from vDD to Ov. When the voltage is 00, this element writes a signal. 0' is the pit line, and when writing a signal,
A voltage corresponding to the signal "1" is applied. 3 is a capacitor for storing charge. Reference numeral 4 is a semiconductor gate formed in the form of a thin film, the lower surface of which is cooled when a voltage is applied. 5 is an insulating film S i02 .

Although a film such as SiSN4 may be used, an insulating film with good thermal conductivity is preferable. The film thickness is preferably 10 nm to 200 nm in consideration of insulation and thermal conductivity. 6 is a high-temperature superconducting material formed in the form of a thin film. Ceramic materials such as BaYCuO have a high critical temperature of 70 to 100 °C, and are materials whose resistance changes rapidly in a narrow temperature range. Reeds are particularly desirable for the present invention. Note that our superconducting material can be used as the superconductor used in the present invention. Reference numeral 7 denotes a wiring drawn from the word line and connected to one side of the semiconductor gate section 4. Reference numeral 8 denotes a wiring connected to the other end of the semiconductor gate section 4, and one side of the wiring 8 is connected to the ground potential. A wiring 9 is connected to one end of the capacitor 3, and is connected to the ground potential.

FIG. 2 shows a laminated thin film portion constituting the semiconductor gate section, and 10 is a metal such as AI! It is a connecting material that connects the wiring 7, which is typically made of metal, and the semiconductor gate 4. 11 is an N-type semiconductor, for example, Zn2Te5.

5i(N) etc. are used. 12 is a P-type semiconductor, Zn
2Te5(P), S1CP) is used and the semiconductor gate 4 is constructed with 11.12. Note that Bt 2 Te a or other semiconductors may be used as the thin film gate 4 .

13 uses the same metal as the connecting material 1o. These 10~
Thirteen layers are laminated on top of the insulating coating 5. By forming this laminated structure in FIG. 2, the end of the P-type semiconductor 12 absorbs heat due to the Peltier effect by passing a current between the connecting members 10 and 13, that is, through the semiconductor gate 4.
The other end of 12 generates heat. The lower surface that absorbs heat cools the high temperature superconductor 6 through the thin insulating film 5.

FIG. 3 shows a sectional view of the integrated structure in actual use, in which the memory shown in FIG. 1 is formed. In the figure, W (ringsten) 1o is attached to the end of an N-type semiconductor 11, and its heel is formed integrally with the wiring 7. On the other hand, the end of the P-type semiconductor 12 is connected to a W connecting member 13, and its line is formed integrally with the wiring 8.

On the other hand, the end of the high-temperature superconductor 6 is connected to the W wiring 14, and a thin oxide film 16 of around several hundred layers is formed at the bottom of this wiring, and this oxide film is made of W16 and is grounded. It is sandwiched between the wiring connected to the potential and forms a capacitor. All of the above device structures can be formed on the glass substrate 17 by means such as vapor deposition or CVD, and can also be realized with a thin film multilayer structure, requiring only a small amount of pattern formation and a step-like structure that integrates a large number of memory elements. This makes it possible to obtain a relatively simple integrated circuit structure with less noise. In this way, it is possible to form a memory integrated circuit using a superconductor and a semiconductor gate tf on a glass substrate. The capacitor and switch parts are, for example, 1 μm thick.
It is also possible to further reduce the thickness to 0.6 μm or less, making it possible to provide an extremely large amount of fibers and a high density device.

The operation of the memory device shown in FIG. 1.2.3 will be explained. When the word line 1 reaches the VDD potential, a potential difference of vDD is applied to the connecting material at both ends of the semiconductor gate 40, and therefore heat is absorbed at the lower surface of the semiconductor gate 4. This cools the lower surface, and the high temperature superconductor 6 is cooled down via the insulating film 5. High temperature superconductor 6 is the fourth
As shown in the figure, when the temperature drops from T to T, the resistance suddenly drops from a very large resistance R to OK.

In this case, the initial temperature is set near T2.

Due to this property, the temperature of the high temperature superconductor 6 is the critical temperature [To
Then the temperature drops to a low temperature T, and bit line 2
The potential of the capacitor 3 becomes electrically conductive, so that the signal on the bit line 2 is transferred to the capacitor 3. Next, when the word line 1 is brought to the ground potential, the heat absorption effect on the lower surface of the semiconductor gate 4 stops, and the high temperature superconductor 6 reaches a critical temperature or higher and its resistance increases, so that the bit line 2 and the capacitance are insulated. This means that charge is accumulated at one end of the capacitor 3. After that, in order to read out this accumulated charge, the word line 1 is set to VDD K and a voltage is applied to the semiconductor gate 4, the high temperature superconductor 6 is cooled, the resistance is lowered, and the charge is accumulated in the capacitor 3. The charge can then be read out via bit line 2.

By repeating this operation, it is possible to operate as a memory element. The specific temperature in FIG. 4 varies depending on the material of the high temperature superconductor used; 14A is Yo, and 4Ba0.6Cu03 is T.

is obtained at 80° and T2 at 95°.

Another application of the present invention is shown in FIGS. 5 and 6 as a conventional gate or inverter.

In FIG. 5, 4, 5.6 are the semiconductor gates and insulators.

It is a high-temperature superconductor, and its operating principle is the same as described above. 2
o is the input terminal and the input signal v changes from voltage vDD to 0.
iyu is applied. 21 is an output terminal from which an output voltage can be obtained, and 16 is a resistor whose one end is connected to the output vout and the other end to the power supply vDD. In the element configured at 4°6.6, one end of the semiconductor gate 4 is connected to the input voltage vio, and the other end is connected to the ground potential. One end of the high temperature superconductor 6 has an output voltage V. The other end of ut is connected to ground potential.

The operating characteristics of this device are shown in FIG. Figure 6 shows ■V for in. ut characteristic, output V for input voltage vin. Effects of the Invention The present invention has the following great advantages.

■ Compared to the conventional semiconductor MO8 type device which uses a silicon single crystal substrate, it can use an insulating substrate such as a normal glass substrate and can be made at a very low cost.

■ Conventional VLSIMOS memory has a channel length of 0.3
However, in the present invention, there is no size limit, and in fact, from the point of view of thermal efficiency, narrower elements are better. The value is low, and the advantage is great when the bit capacity is about 100M pits.

It can be applied to designs with design dimensions of 0.5 μm or less, making it possible to achieve ultra-high density and large capacity.

In particular, in the case of ordinary small-area MOS) transistors, the steps are severe and the mask process usually requires 20 or more masks.
The device according to the present invention has a simple structure and can be manufactured using a mask of 10 or less.

■ The wiring of the element in the present invention is extremely effective by wiring on an insulating substrate such as glass.
Therefore, for example, in the case of memory confectionery, it is possible to lower the wiring capacitance value, and therefore not only can it be formed in a small area, but also the step difference in trench capacitance, which is planned to be used in VLSI memory, can be reduced. , there is no need to adopt a process arrangement (structure, etc.) that is likely to cause leakage current.

As described above, the present invention greatly contributes to the realization of ultra-high-density switching confectionery that is easy to manufacture.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a memory element according to an embodiment of the present invention, FIG. 2 is a sectional view showing the semiconductor gate portion of FIG. 1, and FIG. 3 is a structure of the memory element portion of FIG. 1. 4 is a diagram showing the thermal characteristics of a high-temperature conductor element, FIG. 5 is a diagram illustrating the configuration of an inverter element according to another embodiment of the present invention, and FIG. 1... Word line, 2... Bit line, 3... Capacitive section, 4... Semiconductor gate, 6... Insulation. Film, 6...Superconductor, 11...N-type semiconductor, 12...P
type semiconductor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4

Claims (6)

[Claims] (1) A semiconductor gate for cooling is formed on a superconductor with electrodes arranged at both ends via an insulator, and by passing a current through the gate, the temperature of the surface of the gate on the superconductor side is lowered, and the superconductor is heated. A switching device characterized in that the temperature of the superconductor is changed to change the conductivity of the superconductor. (2) The switching device according to claim 1, characterized in that the temperature of the superconductor is lowered to below a critical temperature to change from room temperature conductivity to superconductivity. (3) The switching device according to claim 1, wherein the semiconductor gate has a temperature reduced by the Peltier effect. (4) An electrode at one end of the superconductor is connected to a charge storage capacitor, an electrode at the other end is connected to a bit line, a semiconductor gate is connected to a word line, and the word line controls the temperature reduction of the gate. 2. The switching device according to claim 1, further comprising a memory element that stores charge in said capacitor and reads charge from said capacitor. (5) The switching device according to claim 4, wherein an insulator, a superconductor thin film, a semiconductor gate, and a capacitor are integrated on the same substrate. (6) An inverter is formed by connecting a series connection body of a superconductor and a resistor to a power source, applying an input signal to a semiconductor gate, and obtaining an output signal from a connection point between the superconductor and the resistor. A switching device according to claim 1.