JPS63290007A - Tracking type reference power source - Google Patents

Abstract

PURPOSE:To obtain two output reference voltages to satisfy the relation of V1=-V2 at an optional precision by quantizing a signal V3, which is the sum of two output voltages V1, V2, into a binary digit according to its plus and minus, and controlling the gain of an inversion circuit by the integrated value of the said value. CONSTITUTION:The inversion circuit 1, the gain of which varies according to a control signal, and which inverts the polarity of an input signal, and an addition circuit 2, which makes the output signal of the inversion circuit 1 be the first input signal, and makes the input signal be the second input, and makes the sum of the first input and the second input be an output, and a comparison circuit 3, which quantizes the output of the addition circuit 2 into the positive and the negative binary digits, and an integration circuit 4, which integrates the output signal of the comparison circuit 3, are provided. Besides, the output signal of the integration circuit 4 is made to be the control signal of the inversion circuit 1, and the output terminal 7 of the inversion circuit 1 is made to be a first output reference voltage terminal, and the terminal 8, directly led from the terminal, to which the input signal is impressed, is made to be the second output reference voltage terminal. Thus, two reference voltages V1, V2 being in the relation of V1=-V2, can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tracking type comparison power supply, and particularly to a power supply that obtains two reference voltages having the same absolute value and having positive and negative signs.

[Prior Art] Conventionally, this type of power supply circuit that obtains two reference voltages with equal absolute values and positive and negative signs has been realized using one operational amplifier as shown in FIG. This will be explained below with reference to FIG. The resistance values of resistors 102 and 103 are respectively R
□ , R2. The potential V0 of the input terminal 104 and the potential of the terminals 105 and 106 from which the output reference voltage is obtained are respectively v.
Let it be l, v2. Here, if R1=R2 is selected, if the gain of the system amplifier 101 is set sufficiently large, the gain from vo to Vl is -l, so v,=-v. On the other hand, V2=V
0, so the output reference voltage Vl is 9v.

Two reference voltages with equal absolute values and positive and negative signs can be obtained.

[Problems to be Solved by the Invention] In the conventional power supply circuit described above, the accuracy of the two output voltages v1 and v2 depends on the accuracy of the resistance value R + R2. If R, = R2, then v, = = -v2, but when it is integrated into an integrated circuit, it is impossible to match the resistance values completely, and even if techniques such as trimming are used, factors such as temperature fluctuations Therefore, it is difficult to set R = R2 with high accuracy. Therefore, with high accuracy V, == −V
There is a problem in that it is difficult to obtain two reference voltages V□, V2 which are equal to 2.

The present invention provides a calibrating power source that overcomes these problems of the prior art.

[Means for Solving the Problems] According to the present invention; an inverting circuit whose gain changes according to a control signal and inverting the polarity of an input signal; and an output signal of the inverting circuit as a first input signal, an adder circuit that takes an input signal as a second input and outputs the sum of the first input and the second input; a comparator circuit that quantizes the output of the adder circuit into positive and negative binary values; an output of the comparator circuit. an integrating circuit that integrates a signal; an output signal of the integrating circuit is used as a control signal for the inverting circuit, and an output terminal of the inverting circuit is used as a first output reference voltage terminal;

A tracking type comparison power supply is obtained, characterized in that a terminal directly led from the terminal to which the input signal is applied is used as a second output reference voltage terminal.

[Example] Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 shows an example in which the nine inversion circuit 1 and the addition circuit 2 in FIG.

FIG. 3 shows a timing chart showing the timing of opening and closing the switches in the circuit of FIG. 2. The following description will be made with reference to FIGS. 2 and 3.

First, the inversion circuit 1 shown in FIG. 2 will be explained.

The capacitances of capacitors 31 and 32 are assumed to be C3 and C4. It is assumed that the capacitance of the capacitor 33 is changed according to the output of the integrating circuit 4 using a method described later. switch 35
(S s ), 37 (Sl.).

38 (Sll) is operated by the clock φ4 shown in FIG.

Switches 34 (Sy), 36 (S9), 39 ('5
t2) (operates with ri clock φ5. The operation will be explained below according to the time chart of FIG. 3.

At time t2, switches 3 s (S, ), 37 (
81G).

38 (Sit) is on, the charges stored in the capacitors 32 and 33 are discharged. The potential of the terminal 7 is 1=Q3/C3, where C3 is the charge stored in the capacitor 31 at that time (see FIG. 5).

Thereafter, at one time t4, the switch 34 (S7).

Since 36 (S9) and 39 (S2) are on and the other switches are off, the potential v1 of terminal 7 is
. Then, ■,=-Cv/(C3+04)·Vo (see FIG. 6). especially.

If Cvf:C3+C4 is selected, it becomes -Vo in V1, and an output obtained by inverting the input can be obtained. Fine adjustment is made using the method described after the CvO value. The value of vl can be adjusted by finely adjusting the value of Cv. Also, the electric charge Q3 stored in the capacitor 31 is as follows.

Since it is held even after time t3, the potential v0 of the terminal 7 is also held.

Next, the adder circuit 2 in FIG. 2 will be explained.

Let the capacitances of capacitors 11 and 12 be C1 and C2. The switch 13 (Sl) is operated by the clock φ in FIG. 2, the switch 14 (S2) is operated by the clock φ2, the switches 15 (S3) and 16 (S, ) are operated by the clock φ3, and the switch 17 (S5) is operated by the clock φ3. φ4. The switch 18 (S,) is activated by the clock φ5. The operation of this part will be explained below according to the time chart of FIG.

At time t1, switches 13 (Sl), 15 (33)-
Since capacitors 11 and 16 (34) are on, the charges stored in capacitors 11 and 12 are discharged (see FIG. 7). then 1
At time t2, switch 14 (S2) t 17 (S5)
is on and the other switches are off, so capacitor 11.
A charge of Q 1 ” C2v is stored in each terminal 12, and the potential V of the terminal 21 is V 3 =-Ql/C1
tonal (see figure i8).

At time t, switches 15 (S3) and 16 (S4)
Since the switch is on and the other switches are off, the charge in the capacitor 12 is discharged (see FIG. 9). At time t4, switches 14 (S2) and 18 (S6) are on, and the other switches are off. In this state, if the capacitor 12 is
A charge of 2=C2■ is stored in the capacitor 11, and a charge of Q
Charges of t + C2 = C2 ("1 +"2) are stored. At this time, the potential V3 of the terminal 21 is “3 = (C
1+C2)/C1=C2(Vl+V2)/C (see Figure 10).

When viewed through the nine inverting circuit 1 and addition circuit 2 described above, the respective potentials ■ of the terminals 6, 7, 8, and 21. *
What is the relationship between Vl 1 v2 y v3?

becomes. In particular, (3), if V1+V2>O, then V3<0, and if V, +V2<O, then v3>0, and the sign of the addition result is the capacitance C1 of the capacitor.

It has the property that it does not depend on the accuracy of C2.

Next, the operation of the comparison circuit 3 will be explained. Comparison circuit 3
is composed of an operational amplifier 50. The potential v4 of the output terminal 51 of the arithmetic amplifier 5o is such that the potential V3 of the terminal 21 is positive (V3
> O), then the negative constant voltage -VDD becomes (v4=-
vDD), if negative (“3 < o), then positive constant voltage v
It becomes DD (V4==V,,).

Next, the operation of the integrating circuit 4 and the control signal 5 will be explained.

The integrating circuit 4 is constituted by an up/down counter, and outputs a value obtained by integrating the potential 4 of the output terminal 51 of the comparator circuit 3 as a control signal 5 (v5). That is, v, = ΣtV
4+V,. (■5o is the initial value of the up/down counter)
Output. The value obtained by multiplying this V by a constant Δ (Δ>0) is defined as the fine adjustment difference in the capacitance C of the capacitor 33 of the inverting circuit 1. Namely.

C=Δ·■5+Cvo (Cvo is the offset of Cv).

FIG. 4 shows a method of adjusting the capacitance of the capacitor 33 using the control signal 5 (■5). In the example of FIG. 4, the integrating circuit,
1 consists of a 4-bit up/down counter, and the control signal 5 is a 4-pin parallel signal. Capacitor 33 has offset capacity: capacitor 60 with f C.
and capacitance Δ, 2Δ.

・Capacitors 61, 62, 63°64 with 1Δ and 8Δ
However, through the switches 45, 46, 47, 48,
The configuration is connected in parallel. switch 45,
(16, 47, and 18 are each bit bo of the control signal 5,
bl, b2 + b3 (bo is LSB, b3 is M
SB) is turned on and off depending on the value of 1.0. Thereby, the capacitance Cv of the capacitor 33 can be realized in accordance with the control signal 5 (V5)K.

Finally, it will be shown that by applying such feedback control, the potentials V, . Now, if IV□l>IV21, then Vl<0°V2
〉0, so ■3-(C2/CI) (Vl +V2
)>O, and v, = -V, D(<o).

The result V decreases by VDD compared to the value one cycle ago. Therefore, the value of the capacitance Cv of the capacitor 33 of the inverting circuit 1 also decreases by "VIll". As a result, V1=-Cv/
(C3+04)・v.

Therefore, the absolute value of vl, 1v11, is also Δ■DD/(
C3+C4)・Vo decreases. From the above, lv,
1>+V21, IVll is a constant value ΔVD, /(C
3+C4).

Conversely, in the case of lvt KIV21 (7), V3-(C2
/C1)(VI+V2)<O, V4=VDD(>o
), and +V5 increases by VDD compared to the value one cycle ago. Therefore, the Cvo value also increases by ΔVDD. As a result, the absolute value IV11 of ■ is also Δ'vDD/(c3
+C4) ・Increase by Vc.

From the above, Vl and ■2 are Δ・vDD even in the worst case
/(C3+C4)・■o within the error range te■, -v2
It can be seen that the following relationship is satisfied. By reducing Δ, this error can be made arbitrarily small.

Furthermore, as mentioned earlier, the accuracy of the potential v3 of the output terminal 21 of the adder circuit 2 is the capacitance C, , C2 of the capacitor 11.12.
It is determined by the accuracy of , but the positive/negative of . In the present case, only the positive and negative information of ■ is used, so
There is no need to consider the accuracy of the capacitance of capacitors 11,12.

[Effects of the Invention] As explained above, the present invention provides two output voltages V1,
By performing feedback control in which the signal V3, which is the sum of V2, is quantized into binary values (±■DD) according to the positive and negative values, and the gain of the inverting circuit is controlled by the integral value of the quantized value, V, A two-output reference voltage that satisfies the relationship =-V2 can be obtained. In addition, since there is no need to take into account the accuracy of the circuit constants of the adder circuit (capacitances CI and C2 of capacitors 11 and 12 in Figure 2), it is possible to avoid the effects of temperature fluctuations, which is a problem with conventional circuits. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of a tracking type comparison power supply according to the present invention; Fig. 2 is a block diagram of an embodiment in which the inverting circuit and adder of Fig. 1 are constructed with switched capacitor circuits; is a timing chart showing the timing of opening and closing of the switch of the switched cano E-shita circuit in Fig. 2;
The figure is an explanatory diagram of an example of the capacitor 33 whose capacitance value can be varied by a control signal in the inverting circuit of FIG.
2.14 is a diagram showing the operating state of the inverting circuit of FIG. 2; FIGS. 7, 8, 9, and 10 are respectively
Time t1 + t2 shown in the timing chart in the figure
A diagram showing the operating state of the adder circuit in FIG. 2 at +t3 *j4; FIG. 11 is a configuration diagram of an example of a power supply circuit according to the prior art that obtains two reference voltages with equal absolute values and positive and negative signs. . 1... Inversion circuit, 2... Addition circuit, 3... Comparison circuit. 4... Integrating circuit, 5... Control signal, 6... Input terminal, 7°8... Output terminal, 30... Operational amplifier, 3
1, 32° 33... Capacitor, 34, 35, 36,
37°38.39...Switch, 10...Operation amplifier, 11°12...Capacitor, 13,14,15.
16゜17.18...Switch, 21...Terminal, 5
0...Operation amplifier, 51...Terminal, 60, 61, 6
2,63°64... Capacitor, 65.66.67.
68... Switch, 101... Operational amplifier, 102
, 103...Resistor, 104...Input terminal, 105,
106...Terminal for obtaining the output reference voltage.

Claims (1)

[Claims] 1. An inversion circuit whose gain changes according to a control signal and inverts the polarity of an input signal; an output signal of the inversion circuit is used as a first input, and the input signal is used as a second input. an addition circuit whose output is the sum of a first input and a second input; a comparison circuit which quantizes the output signal of the addition circuit into positive and negative binary values; an integration circuit which integrates the output signal of the comparison circuit. ; The output signal of the integrating circuit is used as a control signal for the inverting circuit, the output terminal of the inverting circuit is used as a first output reference voltage terminal, and the terminal directly led from the terminal to which the input signal is applied is used as a second output. A tracking type comparison power supply characterized by using a reference voltage terminal.