JPS63288340A - Controller for memory access - Google Patents

Abstract

PURPOSE:To freely set the increment width of an address, and to simply execute processing of a horizontal/vertical conversion of a pattern, etc., by providing a bit for setting the increment width to a control register. CONSTITUTION:When an IW bit of a control register 1 is '00', the increment width is +1, as shown in the figure. When a start address of a memory address write register (MAWR) 2 is '0', a CPU 8 writes a transfer data in a V-RAM data write register (VWR) 4 and writes its upper byte. As a result, an address corresponding to a '0' address of a V-RAM 7 is computed by an address counter 6 and written in its address. When this write is ended, an address of said MAWR 2 is brought to an increment. Subsequently, it is computed by the address counter 6 of the VRAM 7 based on an address value '1' of the MAWR 2, and the next data of the VWR 4 is written in its address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device, and more particularly to a memory access control device in which the increment width of an address can be freely set.

[Conventional technology]

A conventional memory access control device specifies an address based on the count value of an address counter, writes data to the specified address, or reads data at that address and transfers it to another. The address is incremented by +1 as the address counter counts up, and the address that increases by 1 is accessed.

[Problem that the invention seeks to solve]

However, according to the conventional memory access control device, since the increment width of the address is fixed, the processing of the character image is unified, which results in a lack of interest. In particular, in recent video games, character images are sometimes required to undergo special processing, but since access methods cannot handle this, the reality is that other methods are used to handle this. It is.

[Means for solving problems]

The present invention has been made in view of the above, and in order to freely set the address increment width, for example, to freely select horizontal writing or vertical writing on the screen,
A memory access control device is provided in which a control register is provided with a bit for setting an increment width.

That is, the memory access control device of the present invention has the following means.

(1) Increment width setting means For example, the increment width is determined by a specific bit of a control register. Since the increment width is determined according to the contents of this bit, the increment width can be changed simply by changing the contents of the bit.

(2) Address setting means A memory address write register (for writing) or a memory address read register (for reading) is used to set an address for accessing the VRAM. It has a start address as an initial value.

(31 Control means adds the set increment width to the start address to set the next address to be accessed, and resets this to the address setting means. From then on, the increment width is added to the reset address and the next access is made. Based on these addresses, the VRAM is accessed to write or read data.

[Effect]

With the above configuration, for example, if the increment width is set to the number of addresses in the horizontal direction, a horizontal writing screen can be changed to vertical writing and stored in the VRAM. On the other hand, if the data is read out in the same way, it is possible to display the data written vertically on the screen based on the data written horizontally in the VRAM.

〔Example〕

The memory access control device of the present invention will be described in detail below.

FIG. 1 shows an embodiment of the present invention, in which a control register 1, a memory address write register (MAWR) 2,
Memory address read register (MARR) 3, VRA
M data write register (VWR) 4, and VRAM
A data read register (VRR) 5 is provided,
MAWR2 and MARR3 are connected to the address counter 6, and VR is determined by the address value of the address counter 6.
AM7 is accessed. Data is written to and read from the VRAM 7 by the CPU 8. Control register 1 has interrupt request permission and other control bits, but in particular, the increment width is set in bits 11 and 12! It has W bit.

FIG. 2 shows the relationship between the contents of the IW bit and the increment width, where "00" is +1. roll is +20 (hexadecimal number, same below), rlOJ is +40, and "11" is +80 increment width. In MAWR2, CPU8 is VR
MARR3 is used to set the start address for writing data to AM7, and MARR3 is used to set the start address for CPU 8 to read data from VRAM7. M.A.R.
When the upper byte (bits 8 to 15) is written to R3, it starts reading data from VRAM 7, puts the data into VRR 5, and writes ink according to the W bit. Also, VWR4 has CPU8 to VRAM7
When the upper byte is written, writing to the VRAM 7 is started, and upon completion of the writing, MAWR2 is incremented according to the IW bit. Furthermore, VRR5 stores the data read from VRAM7 according to the address set in MARR3, and transfers it to CPU8. Once this upper byte is read, reading of the next address begins.

The present invention will be explained in detail below.

(1) IW bit of control register 1 is “0”
0'', the increment width is +1 from FIG. MAWR2
Assuming that the start address of is "0", the CPU 8 writes the transfer data to the VWR 4, and by writing its upper byte, the address counter 6 calculates the address corresponding to address 0 of the VRAM 7, and writes to that address. Upon completion of this write, the address of MAWR2 is incremented by 1 and becomes "1". It is assumed that this writing in the VRAM 7 corresponds to address 0 of the virtual screen in FIG. Next, VR based on the address value “1” of MAWR2
The address of AM7 is calculated by the address counter 6, and the next data of VWR4 is written to that address. This becomes data corresponding to address 1 on the virtual screen. In this way, the horizontal θ of the virtual screen
Data corresponding to the addresses ~IF, 20~3F, 40~5F, . . . - are sequentially written into the VRAM 7.

(2) ■W bit of control register 1 is “0”
1, the increment width is +20 (hexadecimal) from FIG. Assuming that the starting address of MAWR2 is "0", the data of VWR4 is written to the address of VRAM7 calculated by address counter 6.

This corresponds to the data at address O on the virtual screen. Upon completion of writing, the address value of MAWR2 is incremented by +20. The address counter 6 calculates the address of the VRAM 7 corresponding to this address value, and writes the data of the VWR 4 to that address. This data becomes the data of address 20 of the virtual screen. As a result, the address value of MAWR2 is incremented by +20, and becomes +40. In this way, the data is written to the VRAM 7j by the address corresponding to the address 0.20.40.60-...- of the virtual screen. Therefore, the screen has been rewritten from horizontal writing to vertical writing.

On the other hand, if the increment width is selected as +40 or +80, the screen will be written vertically and enlarged twice or four times in the vertical direction. In addition, various screen modifications such as tilting and rotation can be performed by appropriately setting the increment width. In the above embodiment, from CPU8 to VRAM
This relates to writing to VRAM 7, but reading from VRAM 7 can be performed in the same way.

〔Effect of the invention〕

As explained above, according to the memory access control device of the present invention, since the control register is provided with a bit for setting the increment width, the increment width of the address can be freely set, and the horizontal and vertical conversion of the screen is possible. , and other screen processing can be done easily.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention. FIG. 2 is an explanatory diagram showing increment bits of a control register. FIG. 3 is an explanatory diagram showing a virtual screen. Explanation of symbols 1...Control register 2...--
Memory address write register (M A W R) 3.
...-Memory address read register (MARR)
・ 4--...-VRAM data write register 5
−・・−VRAM data read register 6・・−・−・
Address counter 7--VRAM 8--CPU

Claims (1)

[Scope of Claims] A memory access control device that accesses a memory based on an address in an address register, comprising: increment width setting means having an increment bit for incrementing an address; and address setting means having an address for accessing the memory. , comprising control means for starting an access based on the start address of the address setting means, updating the address of the address setting means according to the contents of the increment bit every time the access ends, and continuing the access using the updated address. A memory access control device characterized by: