JPS63287014A - Formation of embedded layer - Google Patents

Abstract

PURPOSE:To form a suitable embedded layer when a semiconductor is embedded flatly, by forming a mask layer, which has an opening having a width satisfying a specified expression of relation, on a substrate, forming a groove, which is wider than the opening of the film, and performing the vapor growth of the embedded layer in the groove. CONSTITUTION:When the width of an opening is W, the depth of a groove is (d) and an angle formed between a growing surface and a substrate is theta, a mask film, which has an opening with the width W satisfying the Expression in the Figure and comprises SiO2, is formed on a semiinsulating InP substrate 1 by a sputtering technology and the like. Then the opening 2A is formed. Thereafter, an (n) type active layer 6 as a ground, which is exposed in the opening in the mask film 2, is etched. At the same time, side etching is performed, and the groove, which is wider than the opening in the mask film 2 and has the depth (d), is formed. Then, an embedded layer 4 undergoes vapor growth in the groove. In this way, the surface of the embedded layer can be made flat even if the width of the groove forming the embedded layer is made wider than the opening of the mask film 2.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for forming a buried layer, in which the opening in a mask film for forming the buried layer is formed to an extent that would normally flatten the surface of the buried layer. By making the width of the trench wider than the width of the opening of the mask film, the trench for forming the buried layer can be formed with a wide width.

[Industrial application field]

The present invention relates to a method for forming a buried layer that can be applied to a case where it is necessary to flatly bury, for example, a semi-insulating compound semiconductor into a groove formed in a substrate, and which can produce good results.

[Conventional technology]

Currently, semiconductor lasers or optical integrated circuits (optoelectronic integrated circuits) using compound semiconductors such as InP are currently available.
c integrated circuit:0E
In IC), it is necessary to form a buried layer of semi-insulating semiconductor as a current blocking layer. In this case, it is preferable that the buried layer has a flat surface with no unevenness from the viewpoint of ease of processing.

In order to form such a buried layer, a technique is known in which a groove is formed in a substrate and a semi-insulating semiconductor is grown in the groove.

FIG. 8 shows a cutaway side view of a main part of a semiconductor device at a key point in the process to explain a buried layer formed by such a technique.

In the figure, 1 is a semiconductor substrate, 2 is a mask film for forming grooves and filling the semi-insulating semiconductor, 3 is a groove, and 4
denotes a buried layer made of a semi-insulating semiconductor grown in the groove, and L denotes the width of the groove 3, respectively.

The technology applied at this time is liquid phase growth (liquid phase growth).
Although it is easy to apply the d-phase epitaxy (LPE) method, it is difficult to use the vapor phase epitaxy (LPE) method due to the high purity of the grown semiconductor or selective growth.
It is preferable to employ the phase epitaxy (VPE) method.

However, when applying the VPE method, the embedding N
It is extremely difficult to make the surface of 4 flat.

The present inventors have previously provided a technique that can completely fill the groove 3 and flatten the surface if the width of the groove 3 is 10 (μm) or less. Kaisho 61-2
(See report 16495). An example of the application of this technology is the formation of a stripe structure for confining the laser current in a semiconductor laser, for example, 1 μm.
] A pair of grooves 3 having a width of 10 [μm] with an interval of
are formed facing each other, and the groove 3 is filled with a semi-insulating semiconductor.

Incidentally, if the above purpose is to be achieved, a buried layer 4 having a width of 10 (μm) is sufficient for practical use, but it is often insufficient for isolation between elements in, for example, 0EIC. Therefore, we have further improved the above technology and provided a technology that alleviates the restriction that the width of the trench 3 is 10 [μm] or less by supplying H(l) to the region where the semi-insulating semiconductor is grown. According to this technology, the width of the groove 3 is 10 [μ
It has become possible to grow a buried layer 4 with a flat surface even when the thickness exceeds 20 μm, for example, close to 20 μm.

[Problem that the invention seeks to solve]

As explained above, with improved technology, it has become possible to fill trenches 3 with a width of less than 20 [μm] with a flat semi-insulating semiconductor, but this limitation can now be overcome. Needless to say, this would be impossible if the groove 3 had a width exceeding that range.

The present invention aims to provide a technique that can substantially ignore restrictions regarding the width of the groove 3 when forming the buried layer 4 as described above.

[Means for solving problems]

The present inventors have already made detailed observations and have understood the mechanism of growth of the buried layer 4 when the width of the trench 3 exceeds the above-mentioned limit.

Figure 9 shows a cutaway side view of the main parts of the semiconductor device at important points in the process to explain the process, and symbols used in Figure 8 indicate the same parts or have the same meanings. Shall have.

In the figure, t indicates the thickness of the raised portion of the surface of the buried layer 4, and G indicates an arrow indicating the direction of growth. Note that the broken lines in the figures are shown for convenience of explanation.

As shown in the figure, when the groove 3 is filled and grown,
Initially, as shown by arrow G, diagonal growth from the corner of groove 3 is predominant, and upward growth is small. However, since the upward growth is not zero, when the edge of the buried layer 4 in the growing process reaches the edge of the mask film 2, the growth starts to swell upward, and the swollen portion when the trench 3 is completely filled. The thickness t becomes quite large, for example, groove 3
When the width is 30 Cμm] and the depth is 5 [μm], it reaches about 3 [μm].

As can be seen from the above description, when buried growth is performed, the upward growth is not very noticeable until the edge of the buried layer 4 reaches the edge of the mask film 2.

Therefore, even if the width of the groove 13 is wide, it is only necessary to fill most of the groove 3 before the edge of the buried layer 4 reaches the edge of the mask film 2.

FIG. 1 shows a cutaway side view of a main part of a semiconductor device at key points in the process for detailed explanation of the present invention, and the same symbols as those used in FIGS. 8 and 9 refer to the same parts. or have the same meaning.

In the figure, d is the depth of the groove 3, W is the width of the opening formed in the mask film 2, and θ is the angle between the growth surface and the substrate (bottom of the groove 3) when buried growth is performed. It shows.

As can be seen from the figure, in the present invention, even if the width of the groove 3 is made wide, the width W of the opening in the mask film 2 is made narrow, so that the mask film 2 has an eaves portion. By doing so, the surface of the buried layer 4 can be flattened.

That is, if the width W of the opening in the mask film 2 is appropriately selected in relation to the depth d of the groove 3 and the angle θ between the growth surface and the substrate, even if the width of the groove 3 is wide, the buried layer 4 The upward growth of the growth layer 4 is suppressed, and the surface of the growth layer 4 becomes flat.

By the way, the above-mentioned appropriate selection preferably satisfies the following two conditions.

tanθ By selecting W and d that satisfy this equation, the surface of the buried growth layer 4 can always be made flat.

Therefore, in the method for growing a buried layer according to the present invention, a substrate (for example, a semi-insulating 1nP substrate 1) is provided with d tan θ W: width of opening d: depth of groove θ: growth surface and substrate (bottom of groove). A mask film (for example, a mask film 2 made of silicon dioxide) having an opening (for example, an opening 2A) with a width W that satisfies the equation of the angle formed by
), and then etching the underlying layer exposed in the opening of the mask film, for example, an n-type ■nP active layer 6), and side-etching it to make it wider than the opening of the mask film. The method also includes a step of forming a groove (for example, groove 3) having a depth of d, and then a step of growing a buried layer (for example, buried layer 4) in the groove in a vapor phase with the mask film remaining. It is.

[Effect]

By adopting the above method, although the width of the opening formed in the mask film is limited to a width that can flatten the surface when forming the buried layer using conventional techniques, it is still possible to form the buried layer. Even if the width of the trench is wider than that of the opening in the mask film, the surface of the buried layer formed there can be made flat, so compared to the conventional technology, the temperature It is possible to easily form a buried layer with a wide width, and it is effective when applied to OBIC and the like.

〔Example〕

FIGS. 2 to 7 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. Note that the same symbols as those used in FIG. 1 indicate the same parts or have the same meaning.

See Figure 2 (11 metalorganic chemical vapor deposition).
c chemical vapor depos
By applying MOCVD technology,
A layer with a thickness of, for example, ~0.2 [μm] is placed on the semi-insulating 1nP substrate 1.
], and an n-type 1nP active layer 6 having a thickness of, for example, about 4 [μm] is grown.

In addition to the above-mentioned MOCVD technology, the film formation technology applied here includes liquid phase epitaxial growth (liquid phase epitaxial growth).
hase epitaxy (LPE) technology, vapor phase epitaxial growth (vapor phase epitaxy)
An appropriate technology such as taxi (VPE) technology can be selected.

See Figure 3 (2) By applying a film forming technology that is slightly inferior in terms of adhesion, such as sputtering technology, a thickness of 2,000 ml, for example,
A mask film 2 made of silicon dioxide (SiOz) having a thickness of about 100 ml is grown.

(3) By applying a normal photolithography technique, a striped opening 2A having a width of, for example, about 20 [μm] is formed.

Refer to FIG. 4 (Using a 41HCf-based etching solution, the n-type 1nP active layer 6 exposed in the opening 2A of the mask film 2 is etched. This etching is automatically stopped at the surface of the InGaAsP etching stop N5. Therefore, if etching is continued in this state, so-called side etching will occur, and an eaves portion will be formed in the mask film 2. It is natural that the width of the groove 3 exceeds 20 [μm], and here the eaves portion is ~5 [μm], so the width of the groove 3 is 30 [μm].
μm].

+5) Using an H2SO4-based etching solution, the InGaAsP etching stop layer 5 is etched using the n-type InP active layer 6 as a mask, and the semi-insulating InP substrate 1 is selectively exposed.

(6) With the mask film 2 remaining as it is, the VP
By applying the E technique, a semi-insulating InP filling N4 is grown to completely fill the inside of the trench 3. In this case, it goes without saying that the surface will be flat.

See Figure 7 The mask film 2 is removed by immersion in +71HF aqueous solution.

After this, various devices can be fabricated by applying conventional techniques.

As explained above, it will be understood that according to the present invention, a buried layer with a wide width can be formed extremely easily. The width of the opening 2A formed in the mask film 2 is within the range that can be filled flatly if there is no eaves part, for example, 20 mm.
μm] or less.

〔Effect of the invention〕

In the buried layer forming method according to the present invention, the opening in the mask film for forming the buried layer is made wide enough to flatten the surface of the buried layer, and The groove was made wider than the width of the opening of the mask film.

Due to this structure, the width of the opening formed in the mask film is limited to a width that can flatten the surface when forming the buried layer using conventional techniques, but the width of the opening formed in the mask film is limited to a width that can flatten the surface when forming the buried layer. Even if the width is wider than that of the opening of the mask film, the surface of the buried layer formed there can be flattened, so compared to the conventional technique, it is warm and wide. It is possible to easily form a buried layer with a wide width, and it is effective when applied to ORIC, etc.

[Brief explanation of the drawing]

FIG. 1 is a cut-away side view of the main parts of a semiconductor device at key points in the process for explaining the present invention in detail, and FIGS. 2 to 7 are at key points in the process for explaining one embodiment of the present invention. FIG. 8 is a cutaway side view of the main part of the semiconductor device at key points in the process for explaining the formation of a buried layer, and FIG. 9 is a cutaway side view of the main part of the semiconductor device for explaining the formation of the buried layer. 2A and 2B are cross-sectional side views of essential parts of a semiconductor device at important points in the process. In the figure, 1 is a semiconductor substrate, 2 is a mask film for forming a trench and filling the semi-insulating semiconductor, 2A is an opening, 3 is a trench, and 4 is a semi-insulating semiconductor grown in the trench. , and L indicates the width of the trench 3, respectively. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Shoji Aitani Representative Patent Attorney: Hiroshi Watanabe - Figure 3, Figure 4, Figure 7, Figure 8

Claims (1)

[Claims] The substrate has an opening with a width W that satisfies the following formula: W = 2d/tanθ W: Width of the opening d: Depth of the groove θ: Angle formed by the growth surface and the substrate (bottom of the groove) forming a mask film, and then etching the base exposed in the opening of the mask film and side etching to form a groove that is wider than the opening of the mask film and has a depth of d. 1. A method for forming a buried layer, the method comprising: forming a buried layer; and then vapor-growing a buried layer in the trench with the mask film remaining.