JPS63284933A - Echo cancelling circuit - Google Patents

Abstract

PURPOSE:To easily increase the number of taps of a canceller, by dividing the outputs of delay elements of (n) stages between input/output terminals to (m)(>2), selecting respective output of the element by a control circuit, storing it in a RAM, and adding it in order. CONSTITUTION:A shift register 4 of (n) stages is connected to the input terminal 1, and an input is delayed. The output of the shift register 4 is changed to n/m by dividing one sampling cycle to the (m) [(m) is integer >=2), and they are selected 21 in order, and are inputted to the RAM5. The outputs of the RAM5 are added 23 in order, and a pseudo echo (e) is outputted, and subtraction 7 between a signal 11 including an echo is performed. The output 12 of the subtractor 7 is inputted to the output terminal 2 and an updating circuit 6. The updating circuit 6 corrects the pseudo echo (e) by controlling the RAM5 so as to reduce the echo being left in the output 12. In such a way, it is possible to reduce the capacity of the RAM5 by increasing the (m) even when the (n) is large, and to realize a device with a large number of taps.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to an echo canceller circuit for performing bidirectional digital transmission using a pair of balanced lines.

(2) Prior art and its problems As a method of transmitting bidirectional digital signals using a pair of balanced lines, there is a method of using an echo canceller circuit. The echo canceller circuit cancels the echo of the transmitted signal into the receiving circuit. Echoes are caused, for example, by reflections from lines or by slight mismatches in 2-wire and 4-wire conversion circuits. Adaptive echo canceller circuits are used to connect to various lines with different characteristics and cancel echoes.

An example of the configuration of a conventional echo canceller circuit is shown in FIG.

In the figure, 1 is an input terminal for a transmitted signal, 2 is an output terminal for a received signal, 4 is an n-stage shift register, 5 is a random access memory (RAM), 6 is an update circuit, and 7 is a subtracter. The transmission signal data string (d
+: i=1. 2.

3...) are given to the shift register 4 as input signal data 3 of the echo canceller circuit. The shift register 4 is an n-stage shift register corresponding to the number n of taps of the echo canceller circuit, and stores the input signal data string 3. The input signal data string is outputted in parallel from this shift register 4 every sample period (T). This output is connected to the address line of RAM5. RAM5
has 2'' addresses to store the pseudo echo corresponding to the input data string stored in the shift register 4, and outputs the pseudo echo 10 stored at the address designated by the input data string. Further, the pseudo echo 10 enters a subtraction circuit 7 and is subtracted from the echo to the received signal.The output 12 of the subtractor 7 produces a residual echo signal, and the update circuit 6 uses this residual echo output 12 to subtract the pseudo echo from the received signal. Modify the value and supply the pseudo-echo lO to the stored address.

As a result, the next time the same input data string appears,
A modified pseudo-echo is output. Echoes are canceled by repeating this process adaptively, and it has the advantage of not requiring a multiplier and being able to cancel nonlinear echoes.

However, in the conventional configuration, the address of RAM 5 required to implement the echo canceller circuit is 2'', so as n becomes larger, the capacity of RAM 5 increases rapidly. All combinations of n input data strings are required for updating, and pseudo-echo updates for the same data string are only performed once every 2''', so if n is large, it may be difficult to converge at startup. The drawback was that it required time. Therefore, in reality, it is difficult to configure an echo canceller circuit with a large number of taps n.

(3) Purpose of the Invention The purpose of the present invention is to increase the RA as the number of taps n increases.
It is an object of the present invention to provide an echo canceller circuit which solves the drawback that the capacity of M rapidly increases.

(4) Structure of the invention (4-1) Differences between the characteristics of the invention and the conventional technology The present invention has n
In order to realize a tap echo canceller circuit, a selection circuit that divides the output of an n-stage shift register into m pieces (m is an integer of 2 or more) and selects each output, and a control circuit that controls the selection. The control output and the selection circuit output are used as RAM addresses, and an accumulator is provided for sequentially adding the outputs of the RAM, and the input signal data is divided into m pieces within one sample period of the input signal data. It is characterized in that all register outputs are selected and the corresponding RAM outputs are accumulated, and echoes are canceled by the output of the accumulator.

This differs from the conventional technology in that it includes the control circuit 1 selection circuit and an accumulator, and the address of the RAM is designated by the outputs of the control circuit and the selection circuit.

Examples of the present invention will be described in detail below.

(4-2) Example FIG. 2 is a block diagram of an embodiment of the invention.

Here, 21 is a selection circuit that selects input data input from input terminal 1 from the output of an n-stage shift register;
2 is one sample lap! A control circuit divides t, 11 (T) into m and controls multiplexing of operations. 23 is an accumulator that sequentially adds the outputs of the RAM 5 and outputs the result as a pseudo echo.

When the number of taps is n, the control circuit 22 divides one sample period (T) into m pieces (m is an integer of 2 or more) as follows.

The output of the control circuit 22 is connected to the selection circuit 21.

The selection circuit 21 selects the output ΔTi (i=
1 to m) (n/n) (if n/m is an integer, its value; if it is not an integer, it is the value rounded up to the decimal point) input data string di(+=1...m) Select d,
Output. The output of the 3A circuit 21 is (n/
It is connected to m3 address lines and specifies 2[~ addresses. Further, the output of the control circuit 22 is connected to other address lines of the RAM 5, and specifies m addresses. R
AM5 receives m2 [four addresses are specified by time ΔT and input data dm] through the address line,
Corresponding to that address, the pseudo echo Δ time for every ΔT is stored and output. The output of RAM 5 is connected to accumulator 23 . The accumulator 23 calculates the pseudo echo Δ remainder for every ΔT by I
Sequentially add over T and calculate the pseudo echo as f = +RΔ
Output as a group. This pseudo-echo portion becomes the pseudo-echo for the n input data output from the shift register 4. The output of the accumulator 23 is connected to a subtracter 7, and the pseudo echo gold is subtracted from 11, which is the sum of the received signal and the echo. The output of the subtracter 7 is connected to the output terminal 2 and the update circuit 6.

The subtractor output 12 contains the residual echo, by which the update circuit 6 corrects the pseudo echo 6 and supplies the Δ remainder to the stored address. As a result, the next time the same address is specified, the corrected Δ is output. By repeating this process, adaptive echo cancellation is performed.

FIG. 3 shows an example in which n=m=8.

This operation is as follows. The control circuit 22 divides one sample period (T) into eight into ΔTI to ΔT8. The control circuit 22 uses three address lines between 6110 and (0
, 0, 1) are output to the selection circuit 21 and the address line of the RAM 5. At this time, the number of selection circuits 22 is one (n/m
=1) data d is selected and output. RAM5 is A0
It has four address lines ~A, and 80...A2 is
A3 is specified by the output d1 of the selection circuit 21 according to the output (0°0.1) of the control circuit 22.The RAM 5 outputs the Δ remainder stored at the address (0°0.1.d,). This output is sent to the accumulator 23. Next, ΔT
2, the control circuit 22 outputs a signal of (0, 1, O), and the selection circuit 21 selects and outputs the data d2. Therefore, the address of RAM 5 is specified by (0, 1, O, ciz), and RAM 5 outputs Δnegative. Accumulator 23
adds Δnegative to the 6th case. The above operation is performed sequentially by ΔT
By performing up to 8, the accumulator 23 calculates f = product Δa and outputs the pseudo echo portion for each sample period (T). Table 1 shows an example of how to specify a RAM address. Hereinafter, as described in FIG. 2, adaptive echo cancellation is performed by repeatedly correcting the negative Δ.

Table 1 As explained above, the present invention can be configured with a RAM having m×2C~ addresses, so compared to the conventional echo canceller circuit which requires 2'' addresses,
When n is large, the capacity of the RAM can be significantly reduced by increasing m. As an example, n=m=1
6, in the conventional configuration, 2'n=6553
Although a RAM with 6 addresses (65 kbit) is required, the configuration of the present invention can be realized with a RAM with 16X 2 =32 addresses.

In addition, in the present invention, since the pseudo echo is updated once every 2NT, the convergence time can be shortened by increasing m, especially when n is large, compared to the conventional configuration in which the update is performed once every 21IT. can do.

(5) As described in detail, the present invention includes a selection circuit, an accumulator, and a
By providing a control circuit that controls time multiplexing of calculations within the sample period, the RAM address can be m x 2.
Since the number can be four, if n is large, the capacity of the RAM can be significantly reduced by increasing m.

Furthermore, since the pseudo echo can be updated once every 2 (9Q"["), there is an advantage that the convergence time at startup can be shortened.

By using the present invention, it is possible to configure an echo canceller circuit having a large number of taps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional echo canceller circuit, FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is a block diagram showing a specific embodiment of the present invention. 1...Input terminal, 2...Output terminal, 4...Shift register, 5...Random access memory (RAM)
, 6... Update circuit, 7... Subtractor, 21... Selection circuit, 22... Control circuit, 23... Accumulator.

Claims (1)

[Claims] When performing bidirectional digital transmission using a pair of balanced lines, an n-stage shift register is used to delay input signal data, and the output of the shift register is divided into m pieces (m is an integer of 2 or more). A selection circuit that selects each output, a control circuit that controls the selection, a RAM (random access memory) whose addresses are the output of the control circuit and the output of the selection circuit, and the RAM outputs are sequentially added. and an accumulator for selecting all of the m-divided shift register outputs and accumulating the corresponding RAM outputs within one sample period of the input signal data. an echo canceller circuit configured to cancel the .