JPS63283038A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS63283038A
JPS63283038A JP11977387A JP11977387A JPS63283038A JP S63283038 A JPS63283038 A JP S63283038A JP 11977387 A JP11977387 A JP 11977387A JP 11977387 A JP11977387 A JP 11977387A JP S63283038 A JPS63283038 A JP S63283038A
Authority
JP
Japan
Prior art keywords
power supply
wiring
polycell
grounding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11977387A
Other languages
Japanese (ja)
Inventor
Masako Hiroma
広間 政子
Hiroshi Ichikawa
浩 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11977387A priority Critical patent/JPS63283038A/en
Publication of JPS63283038A publication Critical patent/JPS63283038A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

PURPOSE:To make it possible to automatically make interconnection, by providing power supply wirings and grounding wirings around a block cell constructed by arranging and connecting a plurality of polycells, such that the distance between a pair of the power supply and grounding connection is equal to the distance defined between a power supply connection and a grounding connection of the polycells. CONSTITUTION:Several kinds of standarlized polycells 1 having a uniform thickness and respective predetermined circuit functions are aligned to form a polycell line 2 in combination. A power supply connection 3 is connected to one edge of each polycell 1 while a grounding conection 4 is connected to the other edge thereof. Such polycells 1 are arranged in a plurality of lines and in multiple layers to form a block cell 5, around which power supply wirings 6 and groundig wirings 7 are provided so as to form a rectangular closed circuit. Branches 6a and 7a are extended from these wirings toward the sides of the block cell. The distance between the branches 6a and 7a is equal to the distance defined between the power supply wiring 3 and the grounding wiring 4 of the polycell 1. In this manner, the power supply wiring and the grounding wiring of each polycell can be connected automatically to the corresponding power supply wiring and grounding wiring of the block cell 5, respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、標準化された複数個の回路セルを組み合せ
て得られる半導体集積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit obtained by combining a plurality of standardized circuit cells.

〔従来の技術〕[Conventional technology]

第4図はこの種の半導体集積回路の従来例における電源
および接地配線を示す説明図である。図において、1は
一定の厚みに揃えられそれぞれ所定の回路機能を有する
標準化されたポリセルであって、これらを複数種類組み
合せて所望の集積回路を設計する。2は複数個(ここで
は3個)のポリセル1を一列に接続して成るポリセル列
である。
FIG. 4 is an explanatory diagram showing power supply and ground wiring in a conventional example of this type of semiconductor integrated circuit. In the figure, reference numeral 1 denotes standardized polycells having a constant thickness and each having a predetermined circuit function, and a desired integrated circuit is designed by combining a plurality of types of polycells. 2 is a polycell row formed by connecting a plurality of polycells 1 (three in this case) in a row.

各ポリセル1にはその一端から他端に向は電源配線3お
よび接地配線4が一定の間隔を保って延設されているの
で、第4図の配置に示す如くポリセル列2を設計するこ
とで、実際の集積回路においては隣り合うポリセル1の
電源配線3同士および接地配線4同士が互いに接続され
る。5は複数個のポリセル1を複数列かつ多階層に配置
して構成されたブロックセルであって、その−辺に沿っ
て一端から他端に向は電源配線6が、また他辺に沿って
一端から他端に向は接地配線7がそれぞれ延設されてい
る。そして、上記ポリセル列2の一端をブロックセル5
の一端に突き合せてこれらを組み合せることにより半導
体集積回路が構成されている。
Since each polycell 1 has a power supply wiring 3 and a ground wiring 4 extending from one end to the other at a constant interval, it is possible to design the polycell row 2 as shown in the layout of FIG. In an actual integrated circuit, power supply wirings 3 and ground wirings 4 of adjacent polycells 1 are connected to each other. Reference numeral 5 denotes a block cell configured by arranging a plurality of polycells 1 in multiple rows and in multiple layers, and a power supply wiring 6 is provided along the - side from one end to the other end, and a power supply wiring 6 is provided along the other side. Ground wiring 7 is provided extending from one end to the other end. Then, one end of the polycell row 2 is connected to a block cell 5.
A semiconductor integrated circuit is constructed by assembling these against one end of the two.

従来の半導体集積回路は上記のように構成されているの
で、ポリセル列2とブロックセル5とを第4図に示すよ
うに互いの電源配線3,6問士が当接する配置に設計す
ると、これらの間の接続は製造プロセスにおいて自動的
に行なえるが、互いの接地配線4,7問士は当接しない
ので、これらの間の接続は最終的に人手によって配線処
理が行なわれることになる。またポリセル列2やブロッ
クセル5の配置の都合などによって、ポリセル列2に対
するブロックセル5の突合せの向きが第4図の状態から
例えば第5図に示すように90度変化すると、ポリセル
列2の電源配線3および接地配線4はブロックセル5の
電源配線6および接地配線7にいずれも当接しないので
、このときは電源配線3.6問および接地配線4.7間
ともに人手によって配線処理が行なわれることになる。
Since the conventional semiconductor integrated circuit is configured as described above, if the polycell row 2 and the block cell 5 are designed in such a manner that their power supply wirings 3 and 6 are in contact with each other as shown in FIG. The connection between them can be made automatically during the manufacturing process, but since the ground wires 4 and 7 do not come into contact with each other, the connection between them will ultimately have to be done manually. Furthermore, due to the arrangement of the polycell rows 2 and block cells 5, if the direction of the butt of the block cells 5 against the polycell rows 2 changes by 90 degrees from the state shown in FIG. Since the power supply wiring 3 and the ground wiring 4 do not come into contact with the power supply wiring 6 and the ground wiring 7 of the block cell 5, at this time, the wiring between the power supply wiring 3.6 and the ground wiring 4.7 must be done manually. It will be.

(発明が解決しようとする問題点) ′ 従来の半導体集積回路は上記のように、ブロックセ
ルとこれに突き合せるポリセルとの間の電源配線同士お
よび接地配線同士の一方が当接しなかったり、ポリセル
に対するブロックセルの突合せの向きによっては電源配
線同士および接地配線同士のいずれも当接しないなどし
て、これらの間の接続を自動的に行なえないため、人手
による配線処理に頼らなければならないという問題点が
あった。
(Problems to be Solved by the Invention) As mentioned above, in conventional semiconductor integrated circuits, one of the power supply wirings and the ground wiring between a block cell and a matching polycell do not come into contact with each other, or the polycell Depending on the direction in which the block cells are matched against each other, neither the power supply wires nor the ground wires may come into contact with each other, and the connection between them cannot be made automatically, so it is necessary to rely on manual wiring processing. There was a point.

この発明は、このような問題点を解消するためになされ
たもので、組み合される互いの回路セルの電源配線同士
および接地配線同士の接続を、回路セルの向きや配置に
関係なく人手に頼らず自動的に行なうことのできる半導
体集積回路を得ることを目的とする。
This invention was made to solve these problems, and allows connections between the power supply wires and the ground wires of the combined circuit cells to be made without relying on human labor, regardless of the orientation or arrangement of the circuit cells. The purpose of this invention is to obtain a semiconductor integrated circuit that can perform automatic processing.

〔問題点を解決するための手段〕[Means for solving problems]

この発明の係る半導体集積回路は、一定厚みに揃えられ
た各々所定の回路機能を有する複数の第1の回路セルを
配列接続して構成した第2の回路セルの端縁に、別の第
1の回路セルの端縁を突き合せ、第1の回路セルの電源
配線および接地配線と第2の回路セルの電源配線および
接地配線とをそれぞれ接続して成る半導体集積回路であ
って、第1の回路セルの電源配線と接地配線の間隔に合
せて、第2の回路セ、ルの各辺に向けて電源配線および
接地配線をそれぞれ延設したものである。
In the semiconductor integrated circuit according to the present invention, a second circuit cell is formed by connecting a plurality of first circuit cells arranged to have a constant thickness and each having a predetermined circuit function. A semiconductor integrated circuit in which the edges of the circuit cells of the first circuit cell are butted against each other, and the power wiring and ground wiring of the first circuit cell are connected to the power wiring and the ground wiring of the second circuit cell. The power supply wiring and the ground wiring are respectively extended toward each side of the second circuit cell in accordance with the interval between the power supply wiring and the ground wiring of the circuit cell.

〔作用〕[Effect]

この発明においては、第2の回路セルのいずれの辺に向
けて第1の回路セルを突き合せても、第1の回路セルの
電源配線および接地配線が第2の回路セルの電源配線お
よび接地配線にともに当接するので、これらの間の接続
を製造プロセスにおいて自動的に行うことができる。
In this invention, no matter which side of the second circuit cell the first circuit cell is butted against, the power wiring and ground wiring of the first circuit cell are connected to the power wiring and ground wiring of the second circuit cell. Since they abut the wires together, the connection between them can be made automatically during the manufacturing process.

〔実施例〕〔Example〕

第1図はこの発明の一実施例における電源および接地配
線を示す説明図であり、第1の回路セルであるポリセル
1、そのポリセル1の複数個の配列によって構成される
ポリセル列2、ポリセル1の表面に形成される電源配線
3、接地配線4については上記した従来の半導体集積回
路と同一のものである。また第2の回路セルであるブロ
ックセル5についても、従来の半導体集積回路と同様に
ポリセル1を複数列かつ多階層に配置して構成されてい
る。同図において、7は接地配線で、ブロックセル5の
周辺に沿って四角形の閉路をなすように形成されるとと
もに、その接地配線7の角部に近い個所ごとに対応する
各辺に向けれてそれぞれ分岐線7aが延設されている。
FIG. 1 is an explanatory diagram showing power supply and ground wiring in one embodiment of the present invention, including a polycell 1 which is a first circuit cell, a polycell row 2 constituted by a plurality of arrays of the polycell 1, and a polycell 1 The power supply wiring 3 and ground wiring 4 formed on the surface of the semiconductor integrated circuit are the same as those of the conventional semiconductor integrated circuit described above. Further, the block cell 5, which is the second circuit cell, is also configured by arranging polycells 1 in a plurality of columns and in a multilayer structure, similarly to a conventional semiconductor integrated circuit. In the figure, reference numeral 7 denotes a ground wiring, which is formed to form a rectangular closed path along the periphery of the block cell 5, and is connected to each corner of the ground wiring 7 toward each corresponding side. A branch line 7a is extended.

また接地配線7の外側には、電源配線6がブロックセル
5の周辺に沿って四角形の閉路をなすように形成される
とともに、その電源配線6の角部では対応する各辺に向
けてそれぞれ分岐線6aが形成され、それぞれの分岐線
6aと、これらと対をなす接地配線7の上記各分岐線7
aとの間は、ポリセル1の電源配線3と接地配線4との
間隔に揃えて設定されている。
Further, on the outside of the ground wiring 7, a power supply wiring 6 is formed to form a rectangular closed circuit along the periphery of the block cell 5, and at the corners of the power supply wiring 6, branches toward each corresponding side. A line 6a is formed, and each branch line 6a and each branch line 7 of the ground wiring 7 paired with these branch lines 6a.
A is set to match the spacing between the power supply wiring 3 and the ground wiring 4 of the polycell 1.

電源配線6が接地配線7の分岐1i17aと重なる部分
では、例えば第1図の符号A(7)個所を斜視図で示す
第2図のように、分岐線7aに対して電源配線6を立体
交差させて、電源配[16と接地配線7の短絡を避ける
ようにしである。この実施例では上記立体交差配線を行
なうために、電源配線6および接地配線7を同時に形成
するさい、接地配線7の分岐線7aと重なる電源配線6
の一部を省略して形成し、このあと少くとも分岐線7a
上に酸化膜を形成して、その上に積層形成する導電部6
bで上記分離形成されていた電源配線6間を接続するこ
とにより、分岐線7aと電源配線6の間の絶縁分離がは
かられている。
In the part where the power supply wiring 6 overlaps the branch 1i17a of the ground wiring 7, the power supply wiring 6 is crossed over the branch line 7a by an overpass, as shown in FIG. 2, which is a perspective view of the point A(7) in FIG. This is to avoid a short circuit between the power supply wiring 16 and the ground wiring 7. In this embodiment, in order to perform the above-mentioned three-dimensional crossing wiring, when forming the power supply wiring 6 and the ground wiring 7 at the same time, the power supply wiring 6 overlaps with the branch line 7a of the ground wiring 7.
is formed by omitting a part of the branch line 7a, and then at least the branch line 7a is formed.
A conductive part 6 on which an oxide film is formed and laminated thereon.
By connecting the separately formed power supply wirings 6 at b, insulation separation between the branch line 7a and the power supply wiring 6 is achieved.

この半導体集積回路は上記のように構成されているため
、ブロックセル5のどの辺に対してポリセル群2あるい
はポリセル1を突き合せるよう設計しても、必ずポリセ
ル1側の電源配線3および接地配線4をブロックセル5
側の電源配線6および接地配線7に当接させ接続するこ
とができる。
Since this semiconductor integrated circuit is configured as described above, no matter which side of the block cell 5 the polycell group 2 or the polycell 1 is designed to butt against, the power wiring 3 and the ground wiring on the polycell 1 side are always connected. 4 block cell 5
It can be connected by coming into contact with the side power supply wiring 6 and ground wiring 7.

言い換えればブロックセル5を90°ずつ回転させたい
ずれの場合でも、ブロックセル5およびポリセル1を突
き合せるだけで両者の電源および接地配線の相互接続が
可能となる。またブロックセル5を第1図の状態からミ
ラー反転した第3図の状態においても、図から明らかな
ように第1図の場合と同様に、ブロックセル5を90°
ずつ回転させたいずれの場合でも、ブロックセル5およ
びポリセル1を突き合せるだけで両者の電源および接地
配線の相互接続が可能である。
In other words, in any case where the block cell 5 is rotated by 90 degrees, the power supply and ground wirings of the block cell 5 and the polycell 1 can be interconnected by simply butting the block cell 5 and the polycell 1 together. Also, in the state shown in FIG. 3, in which the block cell 5 is mirror-inverted from the state shown in FIG.
In either case, the block cell 5 and the polycell 1 can be interconnected by simply butting the power supply and ground wiring between them.

なお上記の実施例では、ブロックセル5の電源配線6お
よび接地配線7として、ブロックセル5の周辺を一周す
る閉路状に形成した場合を示したが、これに限らず情の
配線パターンとの関係などを考慮して、配線の途中を分
断してもよい。また上記電源配線6と接地配線7とは、
ポリセル1の電源配線3と接地配線4の位置関係に応じ
て、外側と内側の位置を逆にしてもよい。
In the above embodiment, the power supply wiring 6 and the ground wiring 7 of the block cell 5 are formed in a closed circuit shape that goes around the periphery of the block cell 5, but the relationship with the other wiring pattern is not limited to this. In consideration of the above, the wiring may be divided in the middle. Furthermore, the power supply wiring 6 and the ground wiring 7 are as follows:
Depending on the positional relationship between the power supply wiring 3 and the ground wiring 4 of the polycell 1, the outer and inner positions may be reversed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、第1の回路セ
ルの電源配線と接地配線の間隔に合せて、第2の回路セ
ルにその各辺に向けて電源配線および接地配線を延設し
たので、第2の回路セルのいずれの辺に向けて第1の回
路セルを突き合せるよう設計しても、第1.第2の回路
セルの間で電源配線および接地配線を当接でき、これら
の間の接続を製造プロセスにおいて自動的に行なうこと
ができるという効果が得られる。
As explained above, according to the present invention, the power supply wiring and the ground wiring are extended to each side of the second circuit cell in accordance with the interval between the power supply wiring and the ground wiring of the first circuit cell. Therefore, no matter which side of the second circuit cell the first circuit cell is designed to butt against, the first. The advantage is that the power supply wiring and the ground wiring can be brought into contact between the second circuit cells, and the connection between them can be automatically made during the manufacturing process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例における電源および接地配
線を示す説明図、第2図は第1図の符号Aで示す部分の
斜視図、第3図はブロックセルを第1図の状態からミラ
ー反転した状態を示す実施例の説明図、第4図は従来の
半導体集積回路における電源および接地配線を示す説明
図、第5図はブロックセルの配向を第4図の状態から9
0度変えた状態を示す説明図である。 図において、1はポリセル(第1の回路セル)、3は電
源配線、4は接地配線、5はブロックセル(第2の回路
セル)、6は電源配線、6aはその分岐線、7は接地配
線、7aはその分岐線である。 なお、各図中同一符号は同一または相当部分を示す。
FIG. 1 is an explanatory diagram showing the power supply and ground wiring in an embodiment of the present invention, FIG. 2 is a perspective view of the part indicated by the symbol A in FIG. 1, and FIG. 3 shows the block cell from the state shown in FIG. 1. FIG. 4 is an explanatory diagram showing the power supply and ground wiring in a conventional semiconductor integrated circuit. FIG. 5 is an explanatory diagram of the embodiment showing the mirror inverted state. FIG.
It is an explanatory view showing a state changed by 0 degrees. In the figure, 1 is a poly cell (first circuit cell), 3 is a power supply wiring, 4 is a ground wiring, 5 is a block cell (second circuit cell), 6 is a power supply wiring, 6a is its branch line, and 7 is a ground Wiring 7a is its branch line. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] (1)一定厚みに揃えられた各々所定の回路機能を有す
る複数の第1の回路セルを配列接続して構成した第2の
回路セルの端縁に、別の第1の回路セルの端縁を突き合
せ、前記第1の回路セルの電源配線および接地配線と前
記第2の回路セルの電源配線および接地配線とをそれぞ
れ接続して成る半導体集積回路において、前記第1の回
路セルの電源配線と接地配線の間隔に合せて、前記第2
の回路セルの各辺に向けて電源配線および接地配線をそ
れぞれ延設したことを特徴とする半導体集積回路。
(1) An edge of a second circuit cell configured by arranging and connecting a plurality of first circuit cells each having a predetermined circuit function and arranged to have a constant thickness, and an edge of another first circuit cell. In the semiconductor integrated circuit, the power supply wiring and ground wiring of the first circuit cell are connected to the power supply wiring and ground wiring of the second circuit cell, respectively. According to the spacing between the ground wire and the second
A semiconductor integrated circuit characterized in that a power supply wiring and a ground wiring are respectively extended toward each side of a circuit cell.
JP11977387A 1987-05-14 1987-05-14 Semiconductor integrated circuit Pending JPS63283038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11977387A JPS63283038A (en) 1987-05-14 1987-05-14 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11977387A JPS63283038A (en) 1987-05-14 1987-05-14 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS63283038A true JPS63283038A (en) 1988-11-18

Family

ID=14769853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11977387A Pending JPS63283038A (en) 1987-05-14 1987-05-14 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS63283038A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124776A (en) * 1989-03-14 1992-06-23 Fujitsu Limited Bipolar integrated circuit having a unit block structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124776A (en) * 1989-03-14 1992-06-23 Fujitsu Limited Bipolar integrated circuit having a unit block structure

Similar Documents

Publication Publication Date Title
US5049969A (en) Customizable semiconductor devices
US20020081894A1 (en) Flat flexible circuit interconnections
JPH06260813A (en) Multilayer microstrip assembly with interlayer connection
JPS63283038A (en) Semiconductor integrated circuit
JPH0494556A (en) Integrated circuit cell layout method and cell structure thereof
JPH09134967A (en) Semiconductor integrated circuit device, and its manufacture
JP3018214B2 (en) Stripline filter
JP2714723B2 (en) Method for manufacturing semiconductor integrated circuit device
JPH0636385B2 (en) Flat cable connector
JP2002289785A (en) Semiconductor device
JPH04109661A (en) Layout structure for integrated circuit
JPH0644594B2 (en) Semiconductor integrated circuit
JPS6226186B2 (en)
JPS5935181B2 (en) Hybrid integrated circuit device
JPH03165062A (en) Semiconductor device
JPH0541452A (en) Standard cell system integrated circuit
JPH08250666A (en) Microelectronic integrated circuit including hexagonal cmos type nand gate device
JP2604720B2 (en) Semiconductor integrated circuit device
JPH10125775A (en) Interlayer connection device of multilayer interconnection semiconductor integrated circuit
JPS63161639A (en) Semiconductor integrated circuit
JPH0456355A (en) Semiconductor integrated circuit device
JPS60198845A (en) Semiconductor device
JPH0560666B2 (en)
JPH06291545A (en) Array antenna
JPS5886735A (en) Semiconductor device of multilayer structure