JPS63282888A - Image signal processing circuit - Google Patents

Abstract

PURPOSE:To omit a ROM by previously setting a filter factor in register by a CPU and executing vertical or horizontal filtering based on the specified factor. CONSTITUTION:An image signal Xn of an n-th line is outputted from a line memory 10 and inputted to a line memory 20 and an image signal Xn-1 of an (n-1)th line is outputted from the line memory 20. A multiplier 70 inputs a factor alpha previously set by the CPU and the Xn to execute the arithmetric operation of alphaXn. An adder 30 inputs the image signal Xn+1 of the (n+1)th line and the image signal Xn-1 of the (n-1)th line and executes the arithmetric operation of (Xn+1+Xn-1) and inputs the computed result to a multiplier 80. The multiplier 80 inputs the (Xn+1+Xn-1) and a factor beta previously set in a register 100 by the CPU and executes the arithmetric operation of beta(Xn+1+Xn-1). An adder 90 inputs the computed results of the multipliers 70, 80 and outputs the vertical filtering result of Yn=alphaXn+beta(Xn+1+Xn-1). Consequently, the ROM in an ordinary circuit can be omitted by setting the vertical and horizontal filter factors from the outside, e.g. the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing circuit for facsimiles and the like, and more particularly to a two-dimensional filter circuit for improving the image quality of line drawings such as characters.

2. Description of the Related Art Conventionally, one of two-dimensional filter circuits for improving the image quality of line drawings such as characters, for example a vertical filter circuit, was constructed as shown in FIG.

In FIG. 2, 10. X) is a line filter, 30 is an adder, 110 is a vertical filter calculation station, SO is R
OM60 is a selector. Input image signal (multivalue)
(representing the number of lines), and if the output of this vertical filter circuit is Yn, 'f'n = (i
The calculation n+β(xn-1+Xn+1) is executed, and image quality correction is performed using correlation in the sub-scanning direction. Here, Xn-1 represents pixels of n-/line, xn+1 represents pixels of n+/line, and α and β represent filter coefficients. At this time, the coefficients α and β are fixed.

Conventionally, when it is desired to integrate the filter characteristics, that is, the coefficients α and β, the coefficient α is placed outside the filter circuit.

A ROM in which a predetermined value of β was written in advance was used.

For example, when the filter circuit is made into an LSI and the aim is to downsize the filter circuit, the ROM remains externally attached, which hinders downsizing. The above drawbacks also apply to horizontal filters.

The present invention has been made in view of the above-mentioned conventional situation Vci12, and therefore, an object of the present invention is to provide a novel image signal processing circuit that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology. be.

Means for Solving the Problem In order to achieve the above object, both signal processing circuits according to the present invention include a first line memory that inputs pixels Xn+1 of n+/line and outputs pixels Xn of n line; , a line memory @λ that inputs the pixel Xn of the n line and outputs the pixel Xr1-1 of the n-/ line, and a register that holds arbitrary filter coefficients (assumed to be α and β) given by the CPLJ; jjlJ A first multiplier that inputs the pixel XnO image signal of the n line and the filter coefficient α and performs the operation CtXn, and the pixel signal of the pixel xn+1 of the Q+I line and the pixel Xn-1 of the n−/line. Xn as input
A first calculator that performs the operation +1,000Xn-4, the output of the first adder, and the filter system β are input, and β
(Xn+1+Xn-1); a second multiplier that performs an operation of (Xn+1+Xn-1);
n = axn+β(xn+.

+ ing.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a vertical filter of the present invention.

Referring to FIG. 1, 10. X) is a line filter.

30 is an adder, 70 is an axn arithmetic circuit, goba β(
x-, -40Xn+,) are shown respectively. 9
0 is a calculator and outputs Yn. Reference numeral 100 is a register, which serves to hold the filter coefficients α and β from the CPIJ.
Considering the case where the image signal Xn of the n+1th line is outputted from the line memory 10 and inputted to the line memory J, the image signal Xn of the n-th line is outputted from the line memory J. be done. Multiplier 7
0, the coefficients αp and X are preset by the CPU.
An operation axn is performed using n as input. The adder 3Q receives the image signal Xn+ of the n+/th line.

With the 2nd and n-th line image signals Xn-, as input,
An operation of n+1+Xn-1 is performed, and the result of this operation is input to multiplier Z0. In the multiplier 10, this Xn+1+X
An operation β(xn+, +Xn-1) is performed by inputting n-1 and a coefficient β set in advance in the register 100 by the CPU. And an adder? In O, the operation results of multipliers 70 and 10 are respectively input, and Yn wcffn+
A vertical filtering result β(Xn+1+Xn-1) is output.

As described in detail, according to the present invention, filter coefficients are previously set in the register from CPtJ.

By performing vertical or horizontal filtering using the specified coefficients, it is possible to provide arbitrary filter time characteristics.

This makes it possible to reduce the ROM required in conventional circuits. For example, when this part is integrated into an LSI, an external ROM is no longer required, resulting in a reduction in size.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional circuit.

Claims (1)

[Claims] A first line memory that inputs pixels X_n_+_1 of the n+1 line and outputs the pixels X_n of the n line; and a first line memory that inputs the pixels X_n of the n line and outputs the pixels X_n_- of the n-1 line.
a second line memory that outputs _1; a register that holds arbitrary filter coefficients (α, β) given by the CPU; a first multiplier that performs the operation X_n_+_1+X_n_-_1 by inputting the image signals of the pixel X_n_+_1 of the n+1 line and the pixel X_n_-_1 of the n-1 line; The output of the adder 1 and the filter coefficient β are input, and β(X_n_+_1+X_n_−_1
), Y_n=αX_n+β(
1. An image signal processing circuit comprising: a second adder that performs an operation (X_n_+_1+X_n_-_1).