JPS63280420A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately form the pattern of a resist in an opening by burying a first layer resist only in a trench, then coating it with a second layer resist to form a pattern, and opening a window. CONSTITUTION:A trench 12 is formed on a semiconductor substrate 11, the whole face is thereafter coated with a first layer resist 13, and the coating conditions are so optimized in response to the pattern, trench depth and resist type as to bury the resist in the trench. The resist 13 is ashed, and a section 12b in which the trench is not buried is so minimized that the resist does not remain on the substrate 11. A second layer resist 14 is coated. Even if the second layer resist is not so thick at this time, a flat surface can be obtained. The resist 14 is exposed, developed by a photolithography technique, and a window 15 opened to the first layer resist is opened. Since the resist 14 is thin in the shape of the window 15 at this time, the window is opened in the pattern like a mask pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a photolithography process before burying a trench structure, a photoresist is buried only in the trench, and then a photoresist is further applied to form a pattern.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, such as a DRAM trench capacitor, in which a single photoresist pattern is formed only in the opening of a trench.

[Conventional technology]

The wrench capacitor shown in FIG. 2 (a DRAM shown in a cross-sectional view of al) is a known one.
μ-〇 trench, 23 is an insulating film, 24 is a storage node (stora) formed of polysilicon that stores charge.
ge node), 25 is an insulating film, 26 is a polysilicon cell plate, 27 is an insulating film, 28 is a word line, 29 is an n" type diffusion layer, and 30 is a bit line. ) is an equivalent circuit diagram of a device.

In forming the above-described DRAM, it is necessary to expose the substrate only in the opening of the trench, and to form an n+ type wide diffusion layer there and to form a contact portion with a storage node.

[Problem that the invention seeks to solve]

In forming the DRAM mentioned above, pattern formation is required before filling the trench with a film deposited by CVD such as polysilicon or 5i02. Since the film thickness varies greatly from part to part, there are problems such as variations in pattern size and the inability to use it as a mask in ion implantation. Therefore, conventionally, a so-called multilayer resist method is used.

FIG. 3 is a sectional view for explaining a conventional example.

First, as shown in FIG. 3A, the trench 22 is filled with a lower resist 31 and planarized, and then an SiO2-based intermediate layer 32 is formed using spin-on-glass (SOG).

For this purpose, spin-coating a liquid SiO+-based material,
The intermediate layer 32 of 5i02 is obtained by drying. Next, an upper layer resist 33 is applied. Generally, the lower layer resist is applied to a thickness of 2 μm to several μm, and the upper layer resist 33 is applied to a thickness of 1 to 2 μm.

The reason why a thick resist (about several μm) is applied as described above is that when a thin resist is applied as shown by the broken line in FIG. 3(a), the resist becomes extremely thin at the opening 22a circled in the figure. (This is because it would be impossible to form an accurate pattern.)

Next, as shown in FIG. 3(b), the upper layer resist 33 is patterned, the intermediate layer 32 is etched using the pattern obtained, and then reactive ion etching (R
When IB) is performed, the lower resist that is not masked by the patterns of the upper resist 33 and the intermediate layer 32 is removed, the window 34 is opened, and the pattern of the lower resist 31 shown in the figure is obtained. In the figure, the upper resist layer removed by R[E is indicated by a broken line.

In the above-described process, there is a problem in that as the pattern becomes finer, the difference in pattern conversion from the intermediate layer to the lower resist layer increases. In Figure 3), if the width of the opening in the middle 132 is 1, and the ratio (aspect ratio) between -1 and the thickness of the lower resist becomes large, the lower resist will not be straight in the RIB. It is etched as shown by line a in the figure, and the width at the etched bottom part is -
There is a problem that 2 is larger than the required pattern width -1.

The present invention was created in view of the above points, and an object of the present invention is to provide a method for forming a resist pattern as designed in the opening of a trench formed in a semiconductor substrate. .

[Means for solving problems]

1(a) to (d) are cross-sectional views of an embodiment of the present invention, in which 11 is a semiconductor substrate, 12 is a trench formed in the same substrate, 13 is a first layer resist, and 14 is a second layer resist. resist, 1
5 is a window.

In the present invention, in the process of manufacturing a semiconductor integrated circuit having a trench structure, in the process of forming a resist pattern before burying the trench, only in the trench 12,
That is, after burying the first layer resist 13 without leaving any first layer resist on the semiconductor substrate 11, the second layer resist 13 is buried.
A layer resist 14 is applied and patterned to form a window 15.
Open the window.

[Effect]

By applying the first layer resist using the above method, removing it from the surface to the extent that it does not remain on the semiconductor substrate, and filling the trench and leaving a small space above it, the second layer resist will be very thick. Even if it is not used, the surface is coated evenly, and the window 15 is opened by patterning it.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Refer to FIG. 1(a): A trench 12 is formed in a semiconductor substrate 11 using a conventional technique, and then a first layer resist 13 is applied to the entire surface. Optimize coating conditions according to trench depth and resist type. Generally, its thickness is from 2 μm to several μm thick. In the figure, reference numeral 12a indicates a trench opening, and forming a resist pattern in this portion is an object of the present invention.

Refer to FIG. 1(b): The first layer resist 13 is ashed so that no resist remains on the substrate 11 and the unfilled portion 12b of the trench is minimized. Instead of ashing, if the resist is a positive resist, the entire surface may be exposed, and if it is a negative resist, it may be developed without exposure. In order to make the unembedded portion 12b small, a resist is selected that can be ashed or developed with good reproducibility.

See FIG. 1(C): A second layer resist 14 is applied using conventional techniques. At this time, since the portion of the trench 12 that is not filled with the resist is made as small as possible, a flat surface can be obtained without making the second layer resist very thick. In experiments conducted by the present inventors, the second layer resist was coated to a thickness of less than 1 μm, and a surface was obtained that was flat enough to not interfere with pattern formation.

Refer to FIG. 1(d): The second layer resist 14 was exposed and developed using a normal photolithography technique, and a window 15 was opened that reached the first rj resist, that is, opened to the first layer resist. At this time, it was confirmed that the shape of the window 15 was formed in the same pattern as the mask pattern since the resist 14 was thin as described above.

In the above process, the first layer resist 13 was a single layer, but
It may be a multilayer resist. For example, if a two-layer resist is used and the upper resist layer has good controllability and easy ashing, there is an advantage that the process described with reference to FIG. 1) becomes easier.

〔Effect of the invention〕

As described above, the present invention has the effect of accurately forming a resist pattern at the opening of a trench formed in a semiconductor substrate.
Limited to MII construction Tena <, C-MOS
The present invention can also be applied to the manufacture of LSIs having a trench structure (Si) for trench isolation of LSI wells without the risk of launch-up.

[Brief explanation of drawings]

Figures 1 (a) to (d) are cross-sectional views of embodiments of the present invention, and Figure 2 (
a) is a cross-sectional view of a DRAM wrench capacitor, the peak) is an equivalent circuit diagram of the device in figure (a), and Figure 3 (a)
(and middle) is a sectional view of a conventional example. In FIG. 1, 11 is a semiconductor substrate, 12 is a trench, 12a is a trench opening, 12b is an unfilled portion, 13 is a first layer resist, 14 is a second layer resist, and 15 is a window. Agent Patent attorney Akifuku Kuki Agent Patent attorney Yoshiyuki Osuga DRAM ←shi>f'+qrP>'I''I!II Figure 2

Claims (1)

[Claims] The trench (12) is filled with a first layer resist (13), and the first layer resist (13) remains in the trench (12) but not on the semiconductor substrate (11). The second layer resist (14) is applied to the entire surface so that it is flat to the extent that it does not interfere with pattern formation.
) A method for manufacturing a semiconductor device, comprising the steps of exposing and developing the second layer resist so as to open a window (15) reaching the first layer resist.