JPS63278468A - Decoding circuit for variable length code data - Google Patents

Abstract

PURPOSE:To prevent even the decoding of data with consecutive zero at a latter half from being performed accidentally, by deciding the number of bits of the data included in the final byte of a transmitted data string and the number of bits of dummy bits, bracketing the data and the dummy bit when a correspondence relation exists between them, and stopping the decoding behind the dummy bit. CONSTITUTION:A data segmenting part 12 segments each code data by inputting a reception data string of byte unit. At this time, the code length of each code data can be recognized simultaneously. The number of bits of the code data included in the final byte consisting of the reception data string by impressing and processing the code length on a bit number calculation part 13. Calculated number of bits are impressed on the input on one side of a dummy bit detecting part 14, and when the number of bits of a corresponding dummy bit exist in the reception data string at the dummy bit detecting part 14, the operation of a readout control part 11 is stopped. In such a way, it is possible to obtain a decode circuit by which the bracketing of the dummy bit and the data just before can be performed clearly.

Description

[Detailed Description of the Invention] [4 Required] When data O continues in the latter half, its transmission is omitted, and the data string of the variable length code output serially is replaced by the data string transmitted in byte units. It is a variable length code data decoding circuit that cuts out each variable length code data.
First calculates the number of data bits included in the final byte of the transmitted data string, determines the number of dummy bits that should be present at that time, and detects that there is a certain correspondence between these bit numbers. When this happens, data and dummy bits are separated and decoding after the dummy bit is stopped, thereby preventing erroneous decoding even of the latter half of the 0-consecutive data.

[Field of industrial use]

The present invention relates to a variable length code data decoding circuit.

Generally, when handling data, this is a code with a fixed bit length (
For example, it is usually expressed in 8 bits). However, if necessary, the data may be converted into a variable length code. - An example is the case of image data. In particular, when differential encoding such as DPCM is performed, the code with the shortest bit length is assigned to the data O with the highest degree of occurrence (when there is no change in image data from the same tube in the previous frame). , conversely, as the frequency of occurrence decreases, codes with gradually longer bit lengths are assigned. As a result, the bandwidth can be compressed and the transmission efficiency can be maintained at the same level.

[Conventional technology]

Variable-length code data is sent bit-serial as it is, even though the code length changes randomly, so the decoding circuit must reproduce each piece of data by cutting out data of different lengths from the received data string. Must be. This cutting is performed by identifying whether the pattern of each data matches a predetermined pattern. Therefore, in order to reliably reproduce each piece of data, it is a prerequisite that all data is supplied from the data source without omission.

However, taking the case of the above-mentioned image data as an example, in order to further improve band compression, transmission of specific data 0 is now omitted. To give a specific example, the data of each frame of a TV image is divided into many blocks and data is transmitted in block units, but if data 0 continues in the latter half of each block, the transmission is omitted. It has become common practice to do so.

On the other hand, when data transmission of each block is performed, this is done in byte units (for example, 10-odd bytes). This is because general processing circuits are designed to perform processing in byte units in most cases.

Then, when looking at the final byte of the series of bytes, a situation occurs in which the final byte is not filled with a predetermined number of bits due to the above-mentioned omission of consecutive 0 data. In other words, the final byte is not a complete byte in terms of the number of bits. Therefore, in such a case, a dummy bit is added to form the final byte, which is completed as one byte, and then transmitted to the decoding circuit side.

[Problem that the invention seeks to solve]

When a dummy bit is added to the final byte as described above, the decoding circuit does not clearly distinguish between the dummy bit and the real data, and the dummy bit that appears next to the final byte is treated as normal data. There was a problem with deciphering it. Such erroneous decoding naturally results in a data error, and in the above example of image data, it causes deterioration in image quality.

Therefore, in the present invention, when a dummy bit is added to continuous 0 data to complete one byte and this is supplied to the decoding circuit, the decoding circuit clearly distinguishes between the dummy bit and the immediately preceding data. The purpose of this invention is to propose a decoding circuit for variable length code data that can be used to decode variable length code data.

[Means for solving problems]

FIG. 1 is a block diagram showing the basic configuration of a variable length code data decoding circuit according to the present invention. In this figure, D i
n is a data string of variable length codes serially output from the code circuit side, and each code data D 611L is cut out by decoding the variable length code data. D o u
t is input to a decoding unit (not shown), and the original data is reproduced. However, the key point of the present invention is the code data D. u
It is in the deciphering to cut out L.

There is a read control section 11 at the input stage of the variable length code data decoding circuit 1O, which receives the input data string Di in units of bytes. The data cutting unit 12 receives the received data string in units of bytes as input and cuts out each code data. During this extraction, the code length of each code data is also known at the same time. By applying this code length to the bit number calculating section 13 and processing it, the number of bits of code data included in the final byte of the received data string is calculated.

This calculated number of bits is applied to one input of the dummy bit detection unit 14, and the received data string converted into each byte including each code data is applied to the other input in the data extraction unit 12. Ru. When the dummy bit detection section 14 detects that the number of dummy bits corresponding to the calculated number of bits is present in the received data string, the operation of the read control section 11 is stopped.

[For production]

FIG. 2 is a diagram showing an example of a pattern of variable length code data, which is variable length code data generated on the code circuit side. According to the example described above, 12 data a1 to a12 are generated in each block, and the second half data a6 to a
12 is a series of data 0, and these are omitted from transmission. Data string D in Figure 1! , 1 is the data a1~ in Fig. 2
It corresponds to a5 arranged in serial form. In this case, since transmission is performed in byte units, dummy bits (11 . . . ) are added when the final byte including data a5 is less than a predetermined number of bits constituting one byte.

FIG. 3 is a data pattern diagram used to explain the principle of the present invention, in which the data string Di is a serial data string al.
-a5 and dummy bits, and is separated by byte units I, ■, and ■. The final byte {circle around (2)} includes at least the data a5 immediately before the 0 continuous data and has a dummy bit.

The bit number calculation unit 13 in FIG. 1 calculates the number of bits of code data in the final byte (2). In the example in Figure 3, data a
Part of 4 (1) and all of data a5 (5) total 6 (=
1+5). In this example, one byte consists of 8 bits, so the number of dummy bits is 2 (
=8-6).

In other words, if there is a correspondence relationship of 6 vs 2, the 2
It can be determined that the bit is in dummy focus. This correspondence relationship is known in advance by the dummy bit detection unit 14.

Note that there are seven numbers of dummy bits from 1 to 7. The fact that the number of dummy bits is 0 means that the data string 11 is composed of an integer number of pitros, . . . ) without the dummy bits. In this case, since no dummy bits are originally added, there is no need to separate the dummy bits from the immediately preceding data.

If the dummy bit detection unit 14 detects a dummy bit,
After knowing that data will continue to be 0,
It is known that the reading of D4a should be interrupted for a6 to a12 in FIG. This is because data a6 to a12 are not being transmitted (during this time, the decoding circuit reproduces data 0 by itself). Note that the old block of the next block that is subsequently sent is stored in the previous stage buffer memory (not shown).

〔Example〕

FIG. 4 is a diagram showing an embodiment of the variable-length code data decoding circuit according to the present invention, and reference numbers 111 and 112 indicate the first
Similarly, 121.12 corresponds to the readout control unit 11 in the figure.
2.123 corresponds to the data extraction section 12, 131 corresponds to the bit number calculation section 13, and 141 and 142 correspond to the dummy bit detection section 14, respectively. Reference number 111 is an 8-bit register, which receives data in bytes under the control of clock control circuit 112. Figure 5 (8) - (E
) is a diagram representing the signals appearing in A to E of FIG. 4, respectively, and has the pattern of FIG. 5(A).1. , appears. The data shown in FIG. 5A is applied to the data rotation circuit 121 in units of bytes, that is, in units of columns in FIG. 5<A. Data rotation refers to sequentially switching the input 8-bit lines of the data rotation circuit 121 so that each code data is included in each byte (a detailed example of the data rotation circuit will be described later). The rotation setting circuit 12 determines this amount of rotation.
3, and includes, for example, a decoder (described later). The function of this data rotation circuit 121 is clear from the fifth [M (B), where data al, a2, a3, . a4. It is rearranged so that a5 and dummy bits appear.

The output from the data rotation circuit 121 (signal in FIG. 5(B)) is applied to the extraction circuit 122, where pattern matching is performed and each code data is extracted. The patterns to be matched are predetermined patterns such as al, a2, etc., and it is detected whether the patterns match from the beginning of each column in FIG. 5(B). If it matches the built-in pattern (0010), it is detected that it is data a1, and this is output as code data D 6 ++ t. Furthermore, if it matches the pattern (000), a4 is detected.

On the other hand, in the pattern matching, the code length of code data with matching patterns is also found at the same time.

For al, it is 4, for a2, it is 6, but in the other output (C) of extraction diagram H122, a code length expressed in 3 bits appears as shown in Fig. 5 (C) (for easy understanding, it is shown in decimal notation). ). The reason why it is 3 bits is because 1 byte is 8 bits. Note that the extraction circuit 122 can be configured with a decoder, for example.

The 3-bit code lengths are cumulatively added in the 3-bit adder 131 in the order of code lengths 4, 6.4, . . . in FIG. 5(C). Since it is a 3-bit adder, Figure 5 CD)
As shown in the figure, the addition proceeds while issuing a carry CR. This carry CR is sent to the clock control circuit 112.
It is given as a byte-separated synchronous control signal.

On the other hand, the cumulative addition value of the adder 131 changes as 4, 2.6, etc. when expressed in lO base as shown in FIG. 5(E). The first 4 is the code length of the determined data a1, and the data rotation circuit 121 is controlled to remove it and output the next data a2 at the beginning. This control is performed by a rotation setting circuit (decoder) 123. In other words,
Referring to FIG. 5(B), data al is pushed upward by 4 bits and the next data a2 is placed at the beginning. Once this data a2 has been determined, it is again shifted upward by 6 bits and the next data a3 is placed at the beginning. The same process is repeated below.

The last 6 of the cumulative addition value in Figure 5 (E) obtained in this way is
This indicates the 6 bits in the final pie (III) shown at the right end of FIG. 3, and indicates that data is validly present in this final byte (□) from the beginning to the 6th bit. To confirm this, look at the remaining 2 bits.

If these two bits are the dummy bits "11", it means that the final data a5 and the dummy bits have been reliably separated.

Therefore, the ROM (Rea) forming the dummy bit detection section 14
The pattern of the last byte in FIG. 5B when the above "6" is input to the X address input of the ROM 141 is input to the X address input of the ROM 141. In this case, since the dummy bit "11" (bit number 2) appears, the above-mentioned 6 vs 2 correspondence is established, and the ROM 141 outputs the dummy bit detection signal DM. Signal DM is clock control circuit 112
to stop. In the above case, even if "6" is given to the X address input, the dummy bit 111 is input to the X address input.
” is applied, the signal DM is not output. In other words, at “6” that appears at the beginning of FIG. 5 (F, ), the signal D
M is not output. Note that the signal DM is a 1-bit signal of "1" (correspondence exists) or "O" (correspondence does not exist).

The dummy bit detection section 14 also has a delay circuit 142. The output of the data rotation circuit 121 and the output of the adder 131 whose correspondence is to be seen are delayed by one byte. Therefore, a delay circuit 142 is provided in order to match the timings of both at the address input of the ROM 141.

FIG. 6 is a circuit diagram showing an example of the data rotation circuit in FIG. 4. A data string in bytes from the register 111 is input in parallel to eight selectors 61, 62, . . . , 68. In each selector, the order of output bits relative to input bits is shifted by one bit. This 1-bit shift is one unit of the data rotation amount, and one selector (61 to 68) corresponding to the desired rotation amount is activated. The rotation setting circuit 123 instructs which one should be activated.

〔Effect of the invention〕

As explained above, according to the present invention, even if dummy bits are added to form bytes, a variable-length code data decoding circuit that can separate the dummy bits from the valid immediately preceding data is provided. Realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of a variable-length code data decoding circuit according to the present invention, FIG. 2 is a diagram showing an example of a pattern of variable-length code data, and FIG. 3 is a data pattern used for detailed explanation of the present invention. 4 is a diagram showing an embodiment of a variable-length code data decoding circuit based on the present invention. FIGS. 5(A) to 5(E) are diagrams representing signals appearing at A to E in FIG. 4, respectively. FIG. 6 is a circuit diagram showing an example of the data rotation circuit in FIG. 4. In the figure, 10... variable length code data decoding circuit, 11... readout control section, 12... data cutting section, 13... bit number calculation section, 14... dummy bit detection section.

Claims (1)

[Scope of Claims] 1. Divide the serially output variable length code data string into byte units, and furthermore, the second half of the data string contains data 0.
When the 0 consecutive data is consecutive, transmission of the continuous 0 data is omitted and a dummy bit is added to make the data string of the variable length code the final byte, and after receiving the data string of the variable length code in units of bytes, In a variable-length code data decoding circuit that performs decoding for cutting out each variable-length code data in a data cut-out section (12), the code length of each variable-length code data detected by the data cut-out section (12); a bit number calculation unit (13) that calculates the number of bits of the code data included in the final byte by cumulatively adding the code data; and a bit number calculation unit (13) that calculates the number of bits of the code data included in the final byte; input the converted byte and the calculated number of bits, and determine whether or not the number of bits of the dummy bits in the converted byte and the calculated number of bits have a predetermined correspondence relationship. and a dummy bit detection unit (14) that detects that the dummy bit exists in the final byte when it is determined that there is a corresponding relationship.
and when the dummy bit is detected, the read control unit (
11) A variable length code data decoding circuit characterized in that the operation of 11) is stopped. 2. An adder (1) in which the bit number calculation unit (13) cumulatively adds the code lengths of each variable length code data extracted by the data extraction unit (12) while outputting a carry;
131), and the cumulative addition value is the calculated number of bits. 3. The dummy bit detection unit (14) uses a ROM (Read
Only Memory) (141), and the R
Claim 1, wherein the OM (141) stores in advance a correspondence relationship between the calculated number of bits and the number of bits of the dummy bits, which should be present when the dummy bits exist. decoding circuit.