JPS63278146A - Reading system for status register - Google Patents

Abstract

PURPOSE:To settle a status to avoid control defects, by continuously reading a status register set, based on precedence until read data coincides with preceding read data. CONSTITUTION:An interruption analyzing part 6 is started by an interrupt signal IRQ, and a status register 2 is read by a reading part 7, and an interruption request source is analyzed to start an interruption processing part 5. The reading part 7 reads the register 2 twice continuously and compares read data, and the reading part 7 reads the register 2 again in case of disaccord to compare this third read data with the second read data, and reading is repeated in case of disaccord. Each read data is compared with preceding read data, and read data is judged to be a true value in case of coincidence. There is very little probability that the status is updated at the read timing twice or more, and the status is settled by at least four times of read.

Description

[Detailed Description of the Invention] [Summary] This is a reading method for a status register, which is composed of multiple bits and in which multiple request signals are encoded and set based on priority, and the status register is read continuously and each time the status register is read. A status register reading method in which the data is compared with the previously read data, and if they match, that data is taken as the true value.

[Industrial application field]

The present invention relates to an improved method for reading status registers.

In a control device in which a status register (status notification register) that notifies the status of each part is updated asynchronously with the system clock, the status may be updated at the read timing of the processor.

In particular, when a status register consisting of a plurality of bits is updated by two or more bits, a problem arises in that the status is recognized as different from the status before and after the update, resulting in control failure.

Therefore, there is a need for a reading method that reads true status data.

[Conventional technology]

A conventional example will be described below using reading of an interrupt analysis status register as an example.

FIG. 5 is an interrupt circuit block diagram, and FIG. 6 is an operation flowchart.

In the fifth example, the priority encoder 1 has each input/output unit (101 to I
interrupt signals IR old to I output from
RQn (16 groups or less), selects a high-priority interrupt signal (priority is IRQI → lR11n), encodes it into 4-bit data that identifies that IO, and stores it in status register 2. Set to the lower 4 bits.

At the same time, the interrupt signals IRQI to IRQn are output to the OR circuit 3.
The signal is set to the most significant bit of the status register 2 via the signal IRQ, and is output to the processor 4 as an interrupt signal IRQ.

Now, assuming that the input/output unit IO is 16 sets and the status register 2 is 8 pins, when no interrupt occurs, the status register 2 will be set to, for example, the status SO (0111
1111) (7F, hexadecimal display), and if an interrupt cause occurs in any input/output unit ■0, the status (Fx
XXX) (However, XXX is priority encoder 1.
output).

Upon receiving the interrupt signal IRQ, the processor 4 activates the interrupt analysis unit 8, reads the status register 2, recognizes the input/output unit 0 that requested the interrupt, and activates the interrupt processing unit 5, as shown in FIG. and executes predetermined interrupt processing.

Note that the input/output unit 10, which has a low priority and cannot accept an interrupt request, remains in a state of waiting for processing while outputting the interrupt request.

[Problem that the invention seeks to solve]

If the status register 2 is configured to be written asynchronously, it may be updated by an interrupt request with a higher priority at the timing when the processor 4 reads the status register 2, and the read data may become undefined. In other words, it is unclear whether the bit is in the 0 state or the 1 state.

Therefore, when 2 or more bits of status register 2 are updated, the status is recognized as different from the status before and after the update, and interrupt processing is executed for input/output section 0 that does not generate an interrupt. Dots appear.

The above-mentioned problems will be explained below with reference to FIG. 7, which shows the reading timing of the processor, and FIG. 8, which explains the problems.

FIG. 7 is a diagram showing the read timing of the processor, in which a read signal is output in synchronization with the system clock,
During a predetermined period (ts+th) within the read signal, the value of the status register 2 is read on the condition that the data is fixed.

On the other hand, the status register 2 is set asynchronously to the system clock when an interrupt occurs, so if it is set during the data guarantee period (ts + th), either O or 1 is set. is read as .

When 2 or more bits of status register 2 are updated,
A problem as shown in FIG. 8 arises.

For example, if an interrupt occurs and the lower 4 bits are set to Sl (for example, lower 4 bits 1110), and then an interrupt with a higher priority occurs at the read timing of the processor 4 and S2 (1000) is set, SX (
1100 or 1010).

This corresponds to the input/output section (2)0, which does not receive an interrupt request, and an abnormal state occurs.

In the conventional method of reading the status register, one reading is used as true status data, so the above-mentioned problem is unavoidable.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a status register reading method for reading the true value of the status register.

Means for Solving Problem C] For the above purpose, the status register reading method of the present invention, as shown in FIG. ,
A reading section (7) is provided which compares each reading with the data read immediately before, and when they match, determines the data as a true value and finishes reading.

5 action] Press the status register twice! l! If the data does not match, the data is read a third time and compared with the data read the second time.If the data does not match, the data is read again, and each time the data is compared with the data read just before, the data is matched. The data read at that time is determined to be the true value.

It is extremely rare for a two-concave board to be updated at the reading timing, and the status is determined by at least four readings.

Normally, it waits until a request signal (for example, an interrupt request) is received, so interrupts occur in order of priority,
Moreover, even if we consider the case where all the signals occur at the reading timing, the maximum number of required signals is determined after 141 readings.

For this reason, if reading means are prepared n+1 times, erroneous reading can be eliminated, but if the reading is configured to end when there is a match, reading will actually be completed in about 4 times.

By reading the status register set based on the priority order as described above, the status can be determined by reading continuously until the data matches the previous read data, and control failures can be avoided.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

Fig. 2 is a block diagram of the interrupt circuit of the embodiment, Fig. 3 is a flowchart of the operation of the reading section of the embodiment, and Fig. 4 is a diagram showing an example of status. FIG.

In FIG. 2, reference numeral 6 denotes an interrupt analysis section that operates according to the present invention, which is activated by the interrupt signal IRQ, reads the status register 2 by the reading section 7, analyzes the interrupt request source, and activates the interrupt processing section 5. 7 is a reading unit that reads the status register 2 and determines the status; the same reference numerals represent the same objects throughout the figures.

FIG. 3 is a flowchart of the operation of the reading section of the embodiment;
This shows an example in which the reading status is determined (determined) after four readings. That is, (1) Read status register 2 twice consecutively, and read the first read data (
When #1) and the second read data (#2) match, #2 is set as the true value. (2) If they do not match, read the third time and set the third data (#3) as #2. If they match, #3 is taken as the true value; (3) If they do not match, the fourth reading is performed and the data (#4) is taken as the true value.

Note that when it is determined that it is a true value, the reading ends.

It is extremely rare for the above flow to be updated twice in a row at the reading timing, and it is determined at the fourth reading.

The first figure represents an example of status, and shows an example of determination based on the above flow.

This diagram shows that after the first interrupt occurs and the status S1 is set in the status register 2, the second interrupt with a higher priority is
This figure shows the timing when the interrupt occurs and the status S2 is set, and the transition of the status in that case. Sχ represents another status that can be misidentified.

As is clear from this figure, (1) Status■ In the case where the first reading is undefined, there are three reading statuses (SL, Sx, S2), and the first reading is SL.

If it is Sx, it is determined to be 82 by the second and third reading, and if it is S2, which is the first reading, it is determined to be 82 by the second reading.

As described above, the status ■ is confirmed after at least three readings.

(2) Status ■ The first reading is SL, the second reading is undefined (Sl, SX, S2), if the second reading is 51, it is confirmed with Sl; in other cases, the third reading is, and if the previous reading is 82. is determined in S2,
If the previous time was SX, read the fourth time and confirm with 32.

(3) Status■ Since the reading is 81 for both the first and second readings, it is determined to be 81 after two readings.

In the above example, the read status is determined by at least four readings, but to account for the possibility that the status changes with each reading, it is determined by reading a maximum of n+1 times (n is the number of states) as described above.

As shown in Figure 1, it is also possible to create a flow in which reading and discrimination are performed continuously until a match is made.The probability that an indefinite state will occur continuously is extremely low, so it will be determined at least on the fourth try, and the reading will be determined. finish.

As described above, since the status is determined when the data matches the previously read data, control failures can be prevented.

〔Effect of the invention〕

The present invention provides a method of reading the status register continuously and determining the status when the data matches the data read immediately before.The present invention has an extremely large effect in preventing control failures due to the status being undefined. be.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an interrupt circuit of an embodiment, Fig. 3 is a flowchart of the operation of the reading section of the embodiment, and Fig. 4 is a diagram showing an example of status. is a time chart, (n) is a diagram showing the status at the time of reading, Fig. 5 is an interrupt circuit block diagram, Fig. 6 is an operation flow chart, Fig. 7 is a diagram showing the read timing of the processor, and Fig. 8 is a diagram showing the read timing.
The figure is an explanatory diagram of the problem. In the figure, 1 is a priority encoder, 2 is a status register, 3 is an OR circuit, 4 is a processor, 5 is an interrupt processing section, 6.8 is an interrupt analysis section, 7 is a reading section, 50 is a request signal, and 50-1 is a The request signal with a high priority, IRQ, is an interrupt signal. 5 Greetings Figure 1 Flow chart for reading pickled crucian carp Figure 3 Interrupt circuit block diagram of the embodiment Figure 2 Status ■
-・(1) Time chart diagram (I[) Diagram representing status when reading Diagram representing status example Figure 4 Interrupt circuit block diagram Figure 5 Operation flow chart Figure 6 Explanation of problems

Claims (1)

[Scope of Claims] A request signal (50) with a high priority among a plurality of request signals (50) composed of a plurality of bits and output from each section.
50-1) is output, the request signal (50-1) is identifiably encoded into the plurality of bits and set, and the status register (2) is read continuously. A reading unit (7) is provided which reads the data and compares it with the data read immediately before each reading, and when they match, determines the data as the true value and finishes the reading, and continuously reads the status register (2). , a status register reading method characterized in that a value is determined to be a true value when it matches the immediately previous read data.