JPS63272114A - Alc circuit - Google Patents

Alc circuit

Info

Publication number
JPS63272114A
JPS63272114A JP10473487A JP10473487A JPS63272114A JP S63272114 A JPS63272114 A JP S63272114A JP 10473487 A JP10473487 A JP 10473487A JP 10473487 A JP10473487 A JP 10473487A JP S63272114 A JPS63272114 A JP S63272114A
Authority
JP
Japan
Prior art keywords
voltage
bias
self
input terminal
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10473487A
Other languages
Japanese (ja)
Inventor
Shogo Minami
南 省吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10473487A priority Critical patent/JPS63272114A/en
Publication of JPS63272114A publication Critical patent/JPS63272114A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To make a detector, a variable attenutor, etc., unnecessary by connecting a bias voltage controlled circuit at a frequency multiplier, comparing respectively the voltage of a resistance for a self-bias and a variable resistance for setting a level for the bias voltage control circuit and keeping constantly the voltage for the self-bias. CONSTITUTION:When a variable resistance 8 for setting a level is set to a prescribed resistance value and one input terminal voltage of an operational amplifier 6 is set to a prescribed voltage, the operational amplifier 6 compares the voltage of both edges of a resistance 9 for a self-bias, namely, other input terminal voltage of the operational amplifier 6. The gate voltage of an FET7 outputted from the output terminal is changed, the source drain current of the FET7 is controlled, and the control is executed so that other input terminal voltage can be coincident to one side input terminal voltage, namely, the prescribed level-set voltage. Consequently, the voltage at the resistance 9 for the self-bias, namely, a signal level at a diode 5 for multiplying can be stably kept to a set value. Thus, a variable attenuator, a detector and a variable attenuator control circuit are eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロ波帯信号発生回路に関し、特に出力信
号レベルを一定に保つALC(八utomaticLe
vel Control )回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microwave band signal generation circuit, and in particular to an ALC (automatic Lecture) circuit that maintains a constant output signal level.
vel Control ) circuit.

〔従来の技術〕[Conventional technology]

従来のマイクロ波帯のALC回路では、出力信号レベル
を一定とするために、出力信号レベルを検出するマイク
ロ波帯検波器と、検波器の出力電圧によって信号レベル
を制御するマイクロ波帯可変減衰器を用いていた。
Conventional microwave band ALC circuits use a microwave band detector to detect the output signal level and a microwave band variable attenuator to control the signal level based on the output voltage of the detector in order to keep the output signal level constant. was used.

例えば、第3図に示すように、マイクロ波帯発振器1か
ら周波数逓倍器2を経て出力端子4に至る経路にマイク
ロ波帯可変減衰器11及びマイクロ波帯検波器10を接
続し、更にこの検波器10の出力に基づいてマイクロ波
帯対可変減衰器11を制御するマイクロ波帯可変減衰器
制御回路12を接続している。
For example, as shown in FIG. 3, a microwave band variable attenuator 11 and a microwave band detector 10 are connected to the path from the microwave band oscillator 1 to the output terminal 4 via the frequency multiplier 2, and the detection A microwave band variable attenuator control circuit 12 is connected to the microwave band variable attenuator control circuit 12 which controls the microwave band variable attenuator 11 based on the output of the microwave band variable attenuator 11 .

そして、検波器10の検出出力に基づいて可変減衰器1
1を制御回路12が制御することにより、出力端子4に
おける出力信号レベルを一定に保つている。
Then, based on the detection output of the wave detector 10, the variable attenuator 1
1 is controlled by the control circuit 12 to keep the output signal level at the output terminal 4 constant.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のALC回路では、出力信号レベルを検出
する検波器10と、信号レベルを制御する可変減衰器1
1及びその制御回路12が必要となり、構成が複雑で高
価なものであった。
The conventional ALC circuit described above includes a detector 10 that detects the output signal level and a variable attenuator 1 that controls the signal level.
1 and its control circuit 12, the configuration was complicated and expensive.

本発明は簡単な構成でかつ安価に製造できるALC回路
を提供することを目的としている。
An object of the present invention is to provide an ALC circuit that has a simple configuration and can be manufactured at low cost.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のALC回路は、周波数逓倍器にセルフバイアス
用抵抗によりバイアス電圧を印加可能なバイアス電圧制
御回路を接続し、このバイアス電圧制御回路を、セルフ
バイアス用抵抗とレベル設定用可変抵抗の電圧を夫々比
較してセルフバイアス用抵抗の電圧を一定に保つように
構成して、出力信号レベルの一定化を実現する構成とし
ている。
The ALC circuit of the present invention connects a frequency multiplier to a bias voltage control circuit that can apply a bias voltage using a self-bias resistor, and uses this bias voltage control circuit to control the voltage of the self-bias resistor and the level setting variable resistor. The configuration is such that the voltage of the self-biasing resistor is kept constant by comparing them, thereby achieving a constant output signal level.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

1はマイクロ波帯発振器、2は周波数逓倍器であり、4
のマイクロ波帯信号出力端子から信号が出力される。そ
して、前記周波数逓倍器2にはバイアス電圧制御回路3
を接続している。
1 is a microwave band oscillator, 2 is a frequency multiplier, and 4
A signal is output from the microwave band signal output terminal. The frequency multiplier 2 includes a bias voltage control circuit 3.
are connected.

第2図は前記周波数逓倍器2の逓倍用ダイオードの部分
と前記バイアス電圧制御回路3の回路図である。図にお
いて、5は逓倍用ダイオード、6はオペアンプ、7は電
界効果トランジスタ(FET)である。前記オペアンプ
6の一方の入力端子にはレベル設定用の可変抵抗日を接
続し、オペアンプ6の出力端子はFET7のゲートに接
続している。また、オペアンプ6の他方の入力端子は前
記逓倍用ダイオード5に接続し、かっこの入力端子と前
記F E T 7のソースとの間にはセルフバイアス用
の抵抗9を接続している。
FIG. 2 is a circuit diagram of the multiplication diode portion of the frequency multiplier 2 and the bias voltage control circuit 3. In the figure, 5 is a multiplier diode, 6 is an operational amplifier, and 7 is a field effect transistor (FET). A variable resistor for level setting is connected to one input terminal of the operational amplifier 6, and an output terminal of the operational amplifier 6 is connected to the gate of the FET 7. The other input terminal of the operational amplifier 6 is connected to the multiplier diode 5, and a self-biasing resistor 9 is connected between the parenthesized input terminal and the source of the FET 7.

この構成によれば、レベル設定用可変抵抗日を所定抵抗
値に設定してオペアンプ6の一方の入力端子電圧を所定
電圧に設定すると、オペアンプ6はセルフバイアス用抵
抗9両端の電圧、つまりオペアンプ6の他方の入力端子
電圧との比較を行い、その出力端子から出力されるFE
T7のゲート電圧を変化させてFET7のソース・ドレ
イン電流を制御し、他方の入力端子電圧を一方の入力端
子 1電圧、つまりレベル設定された前記所定電圧と一
致するように制御を行う。これによりセルフバイアス用
抵抗9における電圧、即ち逓倍用ダイオード5における
信号レベルを設定値に安定に保つことができる。
According to this configuration, when the level setting variable resistor is set to a predetermined resistance value and the voltage at one input terminal of the operational amplifier 6 is set to a predetermined voltage, the operational amplifier 6 receives the voltage across the self-biasing resistor 9, that is, the operational amplifier 6 The FE output from the output terminal is compared with the other input terminal voltage.
The source/drain current of FET 7 is controlled by changing the gate voltage of T7, and the voltage of the other input terminal is controlled to match the voltage of one input terminal, that is, the predetermined voltage whose level is set. Thereby, the voltage at the self-biasing resistor 9, ie, the signal level at the multiplier diode 5, can be stably maintained at the set value.

この構成によれば、従来の可変減衰器、検波器及び可変
減衰器制御回路を用いなくとも出力信号レベルを一定に
保持でき、回路構成の前略化を達成できる。
According to this configuration, the output signal level can be maintained constant without using a conventional variable attenuator, a wave detector, and a variable attenuator control circuit, and the circuit configuration can be simplified.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、周波数逓倍器にバイアス
電圧制御回路を接続し、このバイアス電圧制御回路を、
セルフバイアス用抵抗とレベル設定用可変抵抗の電圧を
夫々比較してセルフバイアス用抵抗の電圧を一定に保っ
ているので、この回路を設けるのみで信号発生回路にお
ける出力信号レベルの一定化を実現でき、検波器や可変
減衰器等を必要としない簡単な構成でかつ安価なALC
回路を実現することができる。
As explained above, the present invention connects a bias voltage control circuit to a frequency multiplier, and connects the bias voltage control circuit to a frequency multiplier.
Since the voltage of the self-bias resistor is kept constant by comparing the voltage of the self-bias resistor and the voltage of the level setting variable resistor, it is possible to achieve a constant output signal level in the signal generation circuit just by providing this circuit. , a simple and inexpensive ALC that does not require a detector or variable attenuator, etc.
The circuit can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は本実
施例におけるバイアス電圧制御回路図、第3図は従来の
ALC回路のブロック図である。 1・・・マイクロ波帯発振器、2・・・マイクロ波帯逓
倍器、3・・・バイアス電圧制御回路、4・・・出力端
子、5・・・逓倍ダイオード、6・・・オペアンプ、7
・・・電界効果トランジスタ、8・・・レベル設定用可
変抵抗、9・・・セルフバイアス用抵抗、10・・・マ
イクロ波帯検波器、11・・・マイクロ波帯可変減衰器
、12・・・マイクロ波帯可変減衰器制御回路。 第1図 第3図
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a bias voltage control circuit diagram in this embodiment, and FIG. 3 is a block diagram of a conventional ALC circuit. DESCRIPTION OF SYMBOLS 1... Microwave band oscillator, 2... Microwave band multiplier, 3... Bias voltage control circuit, 4... Output terminal, 5... Multiplier diode, 6... Operational amplifier, 7
... Field effect transistor, 8... Variable resistor for level setting, 9... Resistor for self-bias, 10... Microwave band detector, 11... Microwave band variable attenuator, 12...・Microwave band variable attenuator control circuit. Figure 1 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)発振器と周波数逓倍器を備える信号発生回路にお
いて、前記周波数逓倍器にはセルフバイアス用抵抗によ
りバイアス電圧を印加可能なバイアス電圧制御回路を接
続し、このバイアス電圧制御回路は、前記セルフバイア
ス用抵抗とレベル設定用可変抵抗の電圧を夫々比較して
セルフバイアス用抵抗の電圧を一定に保つように構成し
たことを特徴とするALC回路。
(1) In a signal generation circuit including an oscillator and a frequency multiplier, a bias voltage control circuit capable of applying a bias voltage through a self-bias resistor is connected to the frequency multiplier, and this bias voltage control circuit is configured to control the self-bias An ALC circuit characterized in that the voltage of the self-biasing resistor is kept constant by comparing the voltages of the self-biasing resistor and the level setting variable resistor.
(2)セルフバイアス用抵抗及びレベル設定用可変抵抗
をオペアンプの各入力端子に接続する一方、前記セルフ
バイアス用抵抗を電界効果トランジスタのソース・ドレ
インに接続し、この電界効果トランジスタのゲート電圧
を前記オペアンプの出力で制御するように構成してなる
特許請求の範囲第1項記載のALC回路。
(2) A self-bias resistor and a level setting variable resistor are connected to each input terminal of the operational amplifier, and the self-bias resistor is connected to the source and drain of a field-effect transistor, and the gate voltage of this field-effect transistor is set to the 2. The ALC circuit according to claim 1, wherein the ALC circuit is configured to be controlled by the output of an operational amplifier.
JP10473487A 1987-04-30 1987-04-30 Alc circuit Pending JPS63272114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10473487A JPS63272114A (en) 1987-04-30 1987-04-30 Alc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10473487A JPS63272114A (en) 1987-04-30 1987-04-30 Alc circuit

Publications (1)

Publication Number Publication Date
JPS63272114A true JPS63272114A (en) 1988-11-09

Family

ID=14388724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10473487A Pending JPS63272114A (en) 1987-04-30 1987-04-30 Alc circuit

Country Status (1)

Country Link
JP (1) JPS63272114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0435048A2 (en) * 1989-12-23 1991-07-03 Alcatel SEL Aktiengesellschaft Broadband amplifier stage with controllable amplification

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0435048A2 (en) * 1989-12-23 1991-07-03 Alcatel SEL Aktiengesellschaft Broadband amplifier stage with controllable amplification

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