JPS63271514A - Switching circuit for clock signal - Google Patents

Abstract

PURPOSE:To secure pulse width and to prevent a system from malfunctioning at the time of the switching of a clock signal by providing a delay circuit which delays the output signal from a switching circuit and inputs it to a gate means. CONSTITUTION:The delay circuit such as a flip-flop controls the switching timing of the clock. Namely, the current output levels of clock signals 12 an 13 are equalized to the output levels at the time of switching and after the necessary pulse width of the level is secured, the switching is performed. Consequently, the pulse width of the level is secured and further the output width of the other level is secured as long as the pulse width of the clock signals 12 and 13. Then when plural clock signal sources suffice the rule of the pulse width of a CPU, the rule of minimum pulse width can be followed even at the time of the clock switching.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clock signal switching circuit used in a central processing unit (CPU) or the like.

[Conventional technology]

Figure 5 shows an example of a conventional clock switching circuit.
1.52 are clock signal sources, and one clock signal is selected by a selection gate 53 in response to a clock switching signal 55.

[Problem that the invention seeks to solve]

In this circuit, 51 clock signals are selected,
There is a possibility that the switching signal 55 switches to the clock signal 52 when it is at low level, and the clock signal 52 at that point is in the high level period. Therefore, the high level pulse width is There is a possibility that it will be shorter. Conversely, the low level pulse width also becomes shorter depending on the switching timing. Normally, the clock input to the CPU has a specified pulse width for high level and low level, and this clock switching circuit does not comply with the minimum pulse width specification, causing malfunction of the CPU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that eliminates the drawbacks of conventional clock signal switching circuits and ensures pulse width.

[Means for solving problems]

In the present invention, the current output level of the clock signal is made to be the same as the output level at the time of switching, and the required pulse width of the level is secured before switching. As a result, the pulse width of this level is secured, and the pulse width of the other level is also secured by the pulse width of the clock signal. The present invention is characterized in that if each of the plurality of clock signal sources satisfies the CPU pulse width regulations, the minimum pulse width regulations can be observed even in clock switching.

[Effect]

In the present invention, the timing of clock switching is controlled by a delay circuit such as a clip-flop.

〔Example〕

FIG. 1 is an embodiment of this patent. 7.8 is an independent oscillator which outputs a clock signal of 12.13. lO is the clock signal switching circuit of this patent and 12.1
It has a frequency dividing circuit for 3 signals, 12.13 signals and 12
．． The frequency-divided signal of signal 13 is switched and outputted to 17. 11 is an information device including a CPU, and a clock signal 17 is connected to the CPU.

FIG. 2 shows the ten circuit blocks of FIG.

12.13 source JA clock clock signals, respectively:
Output clock signal 27 from frequency divider 18.19
．． The circuit switches a total of 28 clock signals using 14.15 clock switching signals. 21
．． Gates 22, 23, and 24 fix each clock signal to low level, and when all gates are fixed to low level, the output of 17 becomes low level. 20 is a part that generates the control i1 signal that controls each gate, 14.15, an external synchronization signal (OR signal of the memory refresh signal and reset signal) of the clock switching signal 16, 12.13.27. Clock signal of 28, 17
A clock signal of 29, which is an inverted signal of the output clock signal of , is input.

FIG. 3, which generates the gate control signals of 30, 31, 32, and 33, shows the inside of 20 in the MS2 diagram, and the actual operation will be explained together with the timing chart of FIG.

38 in FIG. 3 is a circuit that takes in the clock switching signal of 14.15 using the external synchronization signal 16.

14 changes from low level to high level, and the selected clock signal 13 is switched to the clock signal 12. In the 4th ET1,
This signal, in which signal 14' changes from low level to high level, is input to the decoder 39 in FIG. 3, where it is decoded together with signal 15'. At T2, only 52 becomes low level, and 53 to 55 go high, due to the clock signal of 29. This indicates that the next clock to be selected is the clock signal 12. Before T2, only 53 was at low level, which indicates that the clock signal 13 was output. was. T2 is 2
Since it is synchronized with the clock of 9, it is possible to set 53 to high level when the output 17 becomes low level, and at this timing, the clock signal of 13 is fixed to low level, that is, the gate control signal of 32 is set to high level. Low level. Other gate control signals 30, 31, and 33 are also low,
The output clock No. 17 maintains a low level.

At T3, the low level of 52 is transmitted to 56, so
The gate control signal No. 30 is set to high level, and the fixation of the clock signal No. 12 to low level is released. Since this release timing is output in synchronization with the 12 clock signals in the flip-flop 40, it is possible to guarantee that the 12 clock signal levels are low level when the 12 clock levels are released from fixation at the T3 timing. ,
1 at T4 when the clock signal of 12 becomes high level.
7's output clock becomes high level again.
The period from 2 to T4 is the period in which the minimum value of the low level pulse width is guaranteed, and since the bipulse width is always determined by the source clock signal, relock switching that guarantees the minimum value of the high and low level pulse widths is possible. It becomes possible.

In addition, as the external synchronization signal in FIG.
In systems with AM as a storage device, a memory refresh signal may be used.

The memory refresh period is a dynamic RAM refresh cycle and no other operations are performed, so even if the clock cycle changes, there is no problem in a normal system.In addition, the system reset signal is also external. Can be used as a synchronization signal. Since the reset signal initializes the system, there is usually no problem even if the clock cycle changes.

[Effects of the Invention]' In the present invention, during system operation, there are operating cycles in which changes in the clock cycle are not allowed. A memory refresh signal, so that the clock signal can be switched during a memory refresh cycle or reset, which is not this operation cycle.
By setting the OR of the reset signal to 1 and using the external synchronization signal when taking in the clock switching signal for clock switching,
System malfunctions can be prevented when switching clock signals.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram including the circuit of this patent, 18
2 and 3 are circuit explanatory diagrams of the present patent, and FIG. 4 is a timing chart explaining the present invention in detail. FIG. 5 is a diagram showing a conventional example. 1.2...Clock signal source 3...Selection gate 4 using AND and OR gates
...Inverter 5...Clock switching signal 6...Output from clock switching circuit, 8...
... Clock signal oscillator 9 ... Clock changeover switch 10 ... Clock changeover circuit 11 ... Information equipment including CPU 12.13 Old ... Clock signal 14. 15... Clock switching signal 16...
...External synchronization signal 17...Output clock 18 of the clock switching circuit
・・・・・・12 clock signal frequency dividers and above Applicant: Seiko Epson Co., Ltd. Representative Patent Attorney Tsutomu Mogami and 1 other person 3rd day

Claims (1)

[Claims:] A circuit that selects and outputs one of a plurality of clock signals, comprising: a switching circuit for selecting one of the plurality of clock signals; and a signal from the switching circuit. 1. A clock signal switching circuit comprising: gate means for fixing the level of the clock signal; and a delay circuit for delaying an output signal from the switching circuit and inputting the delayed signal to the gate means.