JPH0467215A - System clock output circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of a CPU part, etc., by outputting a system clock having the prescribed pulse width and the continuity of clock phase assured even at switching of the system clock. CONSTITUTION:When a clock selection signal instructing the selective switch of clock signals is inputted to a clock signal selection circuit 11, the supply of the output of a system clock generating circuit 13 is discontinued to a circuit which receives the supply of the system clock synchronously with the input timing of the clock selection signal. Thereafter the output (system clock) of the circuit 13 is supplied to said system clock supplied circuit synchronously with a prescribed system clock received from the circuit 13. Thus the pulse width of the system clock supplied to the system clock supplied circuit satisfies the prescribed value even at switching of the system clock. Furthermore the continuity of the clock phase is assured.

Description

[Detailed description of the invention] Industrial application field> The present invention relates to a system clock supplied circuit used in a single-chip microcomputer, etc. The present invention relates to an improvement in a circuit supplied with a system clock that is capable of outputting a system clock in a switched manner.

<Conventional technology> FIG. 4 shows a conventional system clock supplied circuit.

In the figure, 1 is a clock signal selection circuit that selects and outputs one of two clock signals CKI and CK2 having different frequencies based on a clock selection signal S; Based on the selected clock signal CK outputted by the signal selection circuit 1), the system clocks φ, φ
This is a system clock generation circuit that generates a clock. The system clock φ2, which is the output of the system clock generation circuit 2, is supplied to, for example, a CPU section in a one-chip microcomputer. It should be noted that the system crawl generation circuit 2 is composed of a frequency dividing circuit and a logic gate. In the conventional system clock supplied circuit, two types of system clocks φ□ having different frequencies are generated by the clock selection signal S.

Switching output of φ2 is possible.

<Problems to be Solved by the Invention> However, the above conventional circuit has the following problems.

That is, in the conventional circuit described above, when the clock signal CKI is selected and is at the L level, the selection signal S switches it to the clock signal CK2, and if the clock signal CK2 is at the H level at that time, the system There is a possibility that the H-level pulse widths of the clocks φl and φ2 become shorter. The timing chart in FIG. 5 shows this situation.

Moreover, conversely, the pulse width of the L level may also be shortened depending on the switching timing of the black signal.

If such a system clock whose pulse width does not satisfy the specified width is supplied to the CPU section of a one-chip microcontroller, there is a possibility that the CPU section will malfunction.

The present invention has been made in view of the above-mentioned problems of the conventional circuit, and even when the system clock is switched, the pulse width of the output system clock satisfies the specified width and the phase difference is maintained. It is an object of the present invention to provide a system clock supplied circuit whose continuity is also guaranteed.

Means for Solving the Problems> A system clock supplied circuit of the present invention includes a clock signal selection circuit that selects and outputs one clock signal from among a plurality of input clock signals based on a selection signal; In a system clock supplied circuit comprising a system clock generation circuit that generates a plurality of system clocks based on a selection clock signal outputted from the signal selection circuit, the selection signal is sent to the clock signal selection circuit. stopping the supply of the output of the system clock generating circuit to the system clock supplied circuit in synchronization with the input timing of the system clock generating circuit; and after the stop, synchronizing with a predetermined system clock output from the system clock generating circuit The present invention is characterized in that means is provided for starting supply of the system clock generation circuit output to the system clock supplied circuit.

<Function> When the clock selection signal that instructs the clock signal selection switch is applied to the clock signal selection circuit, the supply of the system clock generation circuit output to the system clock supplied circuit is stopped in synchronization with the input timing. be done. Then, in synchronization with a predetermined system clock output from the system clock generation circuit, supply of the system clock generation circuit output (system clock) to the system clock supplied circuit is started. As a result, even when the system clock is switched, the pulse width of the system clock supplied to the system clock supplied circuit satisfies the specified width, and its phase and continuity are guaranteed. be done.

Examples Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Also, FIG. 2 is a timing chart showing the waveforms of each signal shown in FIG. 1 for the case of N=2. In FIG. The clock selection register is controlled by the clock switching instruction CI, and its contents change in synchronization with the system clock φ2'. 12 is the black 7 selection signal S
A plurality of black signals CKI with different frequencies are generated based on the
,...-, a multiplexer that selects and outputs one clock signal from CKNO, and 18 is a system clock that generates system clocks φl and φ2' based on the selected clock signal CK output from the multiplexer 12. This is a generation circuit. Above system clock φ1'
Supply or non-supply of +φ2' to the CPU section is controlled by OR gates 14 and 15 controlled by the system clock supply stop signal H.

That is, the system clock supply stop signal H is w Hw
At level D, the supply of system clocks φ1φ2' is stopped, and both φX and φ2 are fixed at H level. on the other hand,
When the system clock supply stop signal H is at the "L" level, the system clocks φ1, φ2' remain unchanged.
It is supplied to the CPU section as φ2.

In this embodiment, the contents of the clock selection register 11 are changed by the clock switching instruction CI, and at the same time the clock selection signal S is input to the multiplexer 12,
The system clock supply stop signal H is set to the qHw level to temporarily stop the system clock supply to the CPU section, and then the system clock φ2' based on the newly switched clock signal causes the signal H to be set to q Hw level. The system clock is returned to the L level and the system clock supply to the CPU section is started again at the timing φ2' at which phase continuity is maintained between before and before the supply was stopped.

In order to realize the above operation, Kurobuku selection register 1
A D-type flip-flop 16 is provided to catch a change in 1 (a circuit diagram thereof is shown in FIG. 3), and an R5S-type flip-flop 17 is set by the output of this D-type flip-flop 16. The output H' of the R5S type flip-flop 17 is ORed with the output of the R5S type flip-flop 18 for standby control of the one-chip microcomputer by an OR gate 19 to generate a system clock supply stop signal H.

The above R8S type flip-flop 17 is system black 1
It is reset by φ2'. As a result, the stem clock supply stop signal Hu returns to the "L" level.

The timing chart in FIG. 2 shows the case where the clock signal changes from CKI to CK2.

When the clock selection signal S changes, a narrow parnu appears in the output CK of the multiplexer and the system clock φ2', but at this time, the system clock supply stop signal H
Since the signal is at @H" level, it is not supplied to the CPU section. The system clock φ2 based on the newly switched clock signal returns the signal H to @L" level, and the system clock supply resumes. be done.

When the supply of system clock 1 is stopped, the system clock is stopped at the same phase as in standby mode, so there is no adverse effect on the operation of the CPU section.

<Effects of the Invention> As explained in detail above, the system clock supplied circuit of the present invention has a specified pulse width and ensures phase continuity even during switching. Since the system clock is output, malfunctions of the CPU section etc. are prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart showing the waveforms of each signal shown in FIG. 1, and FIG. 8 is a D-type flip-flop shown in FIG. FIG. 4 is a diagram of the circuit configuration of a conventional system clock supplied circuit, and FIG. 5 is a timing chart illustrating the problem of the conventional circuit (4). Explanation of symbols 11: Black 1 selection register, 12: Multiplexer,
18 System clock generation circuit, 14.15.19 Nior gate, 16: D-type flip-flop, 17.18
:R5S type Furi 1 Pf Flop.

Claims (1)

[Claims] 1. A clock signal selection circuit that selects and outputs one clock signal from a plurality of input clock signals based on a selection signal, and a selected clock signal output from the clock signal selection circuit. In a system clock output circuit comprising a system clock generation circuit that generates a plurality of system clocks, the system clock generation circuit outputs the system clock generation circuit in synchronization with the input timing of the selection signal to the clock signal selection circuit. The system clock is stopped from being supplied to the system clock supplied circuit, and after the stop, the output of the system clock generating circuit is synchronized with a predetermined system clock output from the system clock generating circuit to the system clock supplied circuit. A system clock output circuit characterized in that it is provided with means for starting supply.