JPS6327124A - Pll circuit - Google Patents

Abstract

PURPOSE:To accurately detect an unlock state even when a reference frequency is frequency-devided by a variable frequency division circuit discriminating a pulse representing a phase difference by a pulse obtained by retarding a pulse extracted from the optional output stage of a variable frequency division circuit. CONSTITUTION:In counting N-set of reference frequency signals fref decided by a preset data by a frequency division circuit 16, the output G0 of a gate circuit 19 goes to logic 1 and a frequency division output Ps goes to logic 1 at the trailing of the next (N+1)th signal fref. Thus, the output DS1 of a set FF 22 of a delay means 21 goes to 1 and a prescribed value is preset to the circuit 16 by a preset circuit 30. The output Q2 of the circuit 16 rises at the (N+5)th trailing of the signal fref, the output Q of a FF 23 goes to logic 1 at the leading of the output Q2, and a phase difference signal PE outputted from a phase comaprator circuit 14 is generated before and after the leading of a reference pulse R0(Q). Thus, when signals PE(A), PE(B) are generated, ti is discriminated to be an unlock state and when signals PE(C), PE(D) are generated, it is discriminated as a lock state.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a PLL circuit for obtaining a local oscillation frequency signal or a carrier wave signal in radio equipment such as a transceiver.

(b) Conventional technology Normally, in PLL circuits that can be used for transceivers, etc., there is a risk of non-standard radio wave emission when the PLL is unlocked, so it is necessary to detect unlocking of the PLL and prohibit transmission. Yes, and muting is required when selecting a channel for reception.

Therefore, a phase difference signal is derived from a phase comparison circuit to which the frequency division output of the variable frequency divider circuit that divides the oscillation frequency of the voltage controlled oscillator circuit and the frequency division output of the frequency divider circuit that divides the reference frequency are applied. , integrate this signal and discriminate the pulse width,
An unlock detection circuit is obtained by detecting that the phase difference has exceeded a predetermined value. However, when pulse width discrimination is performed using an analog method using a capacitor and a resistor, the accuracy is poor and the PLL
It has the disadvantage that it is not suitable for applying modulation to.

Therefore, conventionally, a PLL circuit as shown in FIG. 5 has been used. In Figure 5, (1) is a variable frequency divider circuit, (2
) is a crystal oscillator circuit, (3) is a frequency divider circuit that divides the reference frequency, (4) is a phase comparison circuit, (5) is a low-pass filter, (6) is a voltage controlled oscillation circuit, and (7) is an unlock circuit. The unlock detection circuit 7), which is a detection circuit, has a pulse PE indicating a phase difference applied to its input, and an intermediate frequency division output φ of the frequency division circuit (3) applied to a clock input CL.
-FF (8) and R-S F F (10), which is set by the output of D-F F (8) and reset by the output of the counter (9) that counts the divided output R0 by a predetermined number. ing. As is clear from the timing diagram of FIG. It is used as a criterion for discrimination. Therefore, accurate pulse width discrimination can be performed, and the discrimination width can be easily changed by changing the stage taken out from the frequency dividing circuit (3).

(c) Problems to be Solved by the Invention However, in the frequency dividing circuit (3) shown in FIG. 5, the frequency divided output R0 applied to the phase comparator circuit can be switched by changing the output stage; Since the frequency ratio is binary, it is not possible to obtain a free frequency division output. Therefore, if you want to obtain an arbitrary comparison frequency other than the binary value base using a general-purpose PLL circuit, or if you want to supply the reference frequency to another circuit (for example, a mixer circuit), the reference frequency is determined by that circuit. This can be handled by using a variable frequency dividing circuit as shown in FIG. 7 as the reference frequency dividing circuit. However, if the clock pulse φ for pulse width discrimination is taken out from an intermediate stage of this variable frequency divider circuit, the discrimination width will change depending on the value of data preset in the variable frequency divider circuit.

That is, in the timing diagram of FIG. 8, for example, the first, second, and third stages of the T-FF in FIG.
If you preset “110” and “100”, T-FF
If the output Q, is the clock pulse φ6, the discrimination width is 1
3" and rb", and further L' a
'', the discrimination widths before and after the frequency-divided output R6, which serves as a reference for phase comparison, are also different. Therefore, when a variable frequency dividing circuit is used as a frequency dividing circuit for dividing the reference frequency, there is a drawback that a constant clock pulse for pulse width discrimination cannot be secured.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a first frequency dividing circuit that inputs the first frequency signal and a second frequency signal that inputs the first frequency signal. a second frequency dividing circuit that receives input and has a variable frequency division ratio; and a delay means that delays the frequency divided output of the second frequency dividing circuit with a pulse taken out from an arbitrary output stage of the second frequency dividing circuit. and a phase comparison circuit to which the frequency division output of the first frequency division circuit and the output of the delay means are applied, and a pulse indicating the phase difference from the phase comparison circuit is applied to an arbitrary frequency division circuit of the second frequency division circuit. It is equipped with an unlock detection circuit that discriminates based on the pulse extracted from the output stage of the second frequency divider circuit or one or more pulses delayed by the pulse, and the discrimination is constant regardless of the data preset in the second frequency dividing circuit. This provides a PLL circuit that can obtain pulses.

(*) Effect: According to the above-mentioned means, the frequency divided output of the second frequency dividing circuit can be delayed by the delay means by the pulse taken out from any output stage of the second frequency dividing circuit. In order to use one or more of the pulses for or delayed by the pulses as pulses for pulse width discrimination, the second pulse is used as a pulse for pulse width discrimination.
When the frequency division output of the frequency division circuit is delayed and is not applied to the phase comparator circuit, the pulse cycle change due to the delay caused by data presetting disappears and returns to the normal cycle. The discrimination width remains constant. Further, since pulses for delay can be taken out from any output stage of the second frequency dividing circuit, the discrimination width can be arbitrarily selected.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The first frequency dividing circuit (11) is a voltage controlled oscillation circuit (V CO
) It is a variable frequency divider circuit that inputs the oscillation frequency signal from (12) and whose frequency division ratio can be varied according to the data applied from the preset circuit (13), and its frequency division output P is sent to the phase comparator circuit (14). Application is allowed. Phase comparison circuit (14)
The comparison output of is applied to the low-pass filter (15),
It is integrally converted and controls the oscillation frequency of the VCO (12).

The second frequency dividing circuit (16) is a variable frequency dividing circuit that inputs the reference frequency signal f' ref from the crystal oscillation circuit (17), and includes a presettable n-stage T-FF (18).
Gate circuit (1) to which the output of each T-FF (18) is applied
9) and D-FF (20), to which the output G0 of the gate circuit (19) is applied to the input, and the reference frequency signal f ref is applied to the clock input CL;
The output of the FF (20) is output as a frequency divided output P, and is also used as a preset control input P of each T-F F (18).
is applied to The delay means (21) includes D
-F F (22) (23), D-FF (2
The input of 2) is always connected to the ground potential "0", the set input S is connected to the frequency division output Ps of the second frequency division circuit (16), and each of D -F F (22) (23) The clock input CL is connected to the second stage output Q of the second frequency dividing circuit (16).
2 can be connected. That is, the output Q is a pulse for delay. D-FF which becomes the output of the delay means (21)
The output Q of (23) is the reference pulse R0 for phase comparison.
It can be applied to the phase comparator circuit (14) as follows.

Therefore, when the frequency division output P becomes 1'', D-FF (22
) is completed, and at the same time, the second frequency divider circuit (16) is preset with data that determines the frequency division ratio, but even if the period of the output Q changes due to the preset,
Since the output R0 from 23) becomes "1" when the output Q rises next, the cycle is in a normal state.

The unlock detection circuit (24) includes D-FF (25), R
-S F F (26), counter (27), OR
Consisting of a gate <28) and an inverter (29), D-
The phase difference signal PE that can be output from the phase comparator circuit (14) is applied to the input of the FF (25), and the output Q of the second stage of the second frequency dividing circuit (16) is applied to the clock input CL. be done.

The output Q of D-FF (25) is R-S F F (26)
The output Q of R-SFF (26) is output as the unlock detection signal UNLOCK. Further, the counter (27) resets the R-3FF (26) when the output of the delay means (21) is counted a predetermined number after the last unlock is detected. The discrimination width of this unlock detection circuit (24) is D −
F That is, since the D-FF (23) of the delay circuit (21) operates at the rising edge of the output Q2, the output Q2 before and after it operates.
The falling period is the discrimination period.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG.

When the second frequency dividing circuit (16) counts the number N of reference frequency signals fref determined by the preset data, the output G0 of the gate circuit (19) becomes "1", and the next N+1 As the reference frequency signal fref falls, the divided output P becomes "1". PS="1" sets the D-FF (22) of the delay means (21) and its output becomes "1", and the second frequency dividing circuit (
16), a predetermined value is preset from the preset circuit (3o). In the case of the timing diagram in Figure 2, Q1="1"
°”, Q, = “l11. Q.

= "0pa, and the periods of Ql+Q!+QB are changed by this data preset.

The next time the output Q2 rises is the reference frequency signal f r
This is the N+5th falling edge of ef, and this output Q,
Due to the rise of D −F F of the delay means (21)
The output Q of (23), that is, the reference pulse R0 becomes "1'', and the phase difference signal PE that can be output from the phase comparator circuit (14) is generated before and after the rising edge of this reference pulse R0. Therefore, , unlock detection circuit (24)
The D-FF (25) detects the phase difference signal PE="1'' at the falling edge of the output Q before and after the rising edge of the reference pulse R0. That is, in FIG.
The periods indicated by T, respectively, are the discrimination widths, and when phase difference signals indicated by PE(4> and PE(b)) are generated, it can be determined that the unlocked state is established, and PE(c) and P
When a phase difference signal expressed by E(2>) is generated, it is determined that the lock state is present.

In this way, the second frequency dividing circuit (16) is controlled by the pulse taken out from any output stage of the second frequency dividing circuit (16).
By delaying the frequency-divided output, it is possible to obtain a discrimination width that is not affected by periodic changes in the pulses to be discriminated.

FIG. 3 shows another embodiment of the invention. In the embodiment of FIG. 3, the delay means (21) shown in FIG.
31) (32) (33) (34), and the output Q of D-F F (33) is the reference pulse R.
, and the voltage is applied to the phase comparator circuit (14), and the D-FF (
32) and the output Q of D −F F (34) are each OR
It is applied to the clock input CL of the D-FF (25) of the unlock detection circuit (24) via the gate (35). This D-FF (25) outputs the data taken in at the rising edge of the clock input CL, and the discrimination width in this case is the rising edge of the output Q of the D-FF (32) and the rising edge of the D-FF (34). This is the period until the output rises. That is, as shown in the timing diagram of FIG.
The outputs of F (32), (33), and (34) are sequentially shifted by the output Q of the second stage of the second frequency dividing circuit (16), and are used as the reference pulse R.
Centering around the rise of the output of F (33), the period before and after it, indicated by T, becomes the discrimination width.

In the embodiment shown in FIG. 3, as is clear from FIG. 4, the period of the second stage output Q changes depending on the data preset to the second frequency divider circuit (16). However, there is no effect on the discrimination width.

In the embodiments shown in FIGS. 1 and 3 described above, the second frequency dividing circuit divides the oscillation frequency from the crystal oscillation circuit (17), but the first frequency dividing circuit ( 11) may be applied with the oscillation output of the crystal oscillation circuit (17), and the second frequency dividing circuit (16) may be applied with the oscillation output of the VCO (12). In this case, the second frequency dividing circuit (16)
The period of the second stage output Q, changes as the oscillation frequency, that is, the frequency division number, of vCO (12) changes, and naturally, T, which is the reference for pulse width discrimination, and T,
The period will also change. In other words, as the oscillation frequency of the VCO (12) increases, the frequency division number increases, and the loop gain decreases, the discrimination width also decreases in proportion to this, and the oscillation frequency of the VCO (12) decreases. As the loop gain increases, the discrimination width also increases proportionally.

Therefore, the allowable lock detection width is automatically adjusted in accordance with the loop gain.

(g) Effects of the Invention As described above, according to the present invention, even when the frequency dividing circuit that divides the reference frequency is a variable frequency dividing circuit, unlock detection can be performed accurately and freely, and furthermore, It is also possible to automatically adjust the discrimination width according to the frequency. Therefore, it is possible to improve the functionality and versatility of the PLL circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. 1, FIG. 3 is a block diagram showing another embodiment, and FIG. 4 is shown in FIG. FIG. 5 is a block diagram showing the conventional example; FIG. 6 is a timing diagram showing the operation of the circuit in FIG. 4;
Figure 7 is a block diagram showing the variable frequency divider circuit, and Figure 8 is the block diagram showing the variable frequency divider circuit.
FIG. 8 is a timing diagram when the variable frequency divider circuit of FIG. 7 is applied to the block diagram of FIG. (11)...First frequency divider circuit, (12)...Voltage controlled oscillation circuit, (13)...Preset circuit, (
14>...Phase ratio Kll path, (15)...Low pass filter, (16)...Second frequency dividing circuit, (17)
...Crystal oscillation circuit, (19>...Gate circuit,
(21)...delay means, (24)...unlock detection circuit, (30)...preset circuit. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 1 Figure 2 (a) "--j/NLock-1112--11" Supervisor-1 f116 Figure 7 Figure 8E5

Claims (1)

[Claims] 1. A first frequency divider circuit that inputs a first frequency signal, a second frequency divider circuit that inputs a second frequency signal and has a variable frequency division ratio, and a delay means for delaying the frequency division output of the frequency division circuit by a pulse taken out from an arbitrary output stage of the second frequency division circuit; and the frequency division output of the first frequency division circuit and the output of the delay circuit. is applied to the phase comparison circuit, and a pulse indicating the phase difference from the phase comparison circuit is extracted from an arbitrary output stage of the second frequency dividing circuit, or one or more pulses delayed by the pulse. A PLL circuit comprising an unlock detection circuit for discrimination. 2. In claim 1, the first frequency dividing circuit is a variable frequency dividing circuit that divides the frequency of a signal based on a voltage controlled oscillation circuit, and the second frequency dividing circuit is a reference oscillation circuit. A PLL circuit characterized in that it is a variable frequency divider circuit that frequency divides a signal based on . 3. In claim 1, the first frequency dividing circuit is a frequency dividing circuit that divides the frequency of a signal based on a reference oscillation circuit, and the second frequency dividing circuit is a voltage controlled oscillation circuit. P characterized in that it is a variable frequency dividing circuit that divides the frequency of a signal based on
LL circuit.