JPS6326893A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To strengthen the resistance to the variation of VCC, to suppress an unfavorable influences caused by the voltage drop of VCC and to allow a memory operation to be operated stably and at high accuracy by constituting the pattern layout of a power source voltage line in a semiconductor memory device with an output Tr, a front stage circuit and an another circuit independently. CONSTITUTION:A VCC line is divided to two systems, and wiring from a VCC bonding pad 7 is connected to a memory cell 1, a decoder 2, an address circuit 3 and a sense circuit 4, and wiring from a VCC bonding pad 8 is connected to an output Tr front stage circuit 5 and an output Tr 6. Accordingly, even when the VCC level is varied by the charging and discharging current of the outer Tr 6, it does not extend to an internal circuit. As the Tr 6 and front stage circuit 5 operate at the same level, even if the voltage drop of VCC is caused by an internal operation, the output H level of the circuit 5 is the same with the VCC level of the Tr 6, and the p-channel Tr of the Tr 6 is cut off sufficiently, and the leak of Tr 6 does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a pattern layout of a power supply voltage (Vcc'') vA thereof.

[Conventional technology]

Figure 2 shows the internal blocks of a conventional memory IC and the power supply voltage (
(2) It is a block diagram showing the layout of the cL) line, and in the figure, (2) is a memory cell, 2 is a decoder, 3 is an address circuit, 4 is a sense circuit, 5 is an output transistor pre-stage circuit, and 6 is an output transistor. Further, 7 is a CC bonding pad of the memory IC, and 9 is a Vcc line.

Next, the effect will be explained. The Vcc pattern layout is important for stable operation of the internal circuit of the memory IC. And, as an example of this ingenuity, ■.

Some have improved line width.

In other words, normally, considering the power supply current capacity, the ■ and c lines of circuits installed far away from the VCC bonding pad are relatively thin, but it is common to lay out the line width as thicker as the VCCCC pad gets closer. It is true. However, even if the above measures are taken, the Vcc line shown in Figure 2 is installed commonly for each circuit block, so if a voltage drop occurs for some reason in V((), all circuits will be Similarly, if the VCC level fluctuates, it will also have an adverse effect on the electrical characteristics.

FIG. 4 is an operational diagram showing the state of the output transistor when the internal circuit is operating. In the figure, when a current flows through the output transistors 18 and 19 to charge and discharge the output load circuit during function, its influence spreads to the sense circuit 4, affecting the output of memory data, for example, delaying access time. It may lead to etc.

As a countermeasure against this problem, there has been a method of separating the VCC line of the output transistor section 6 from the (2) and (c) lines to the internal circuit.

FIG. 3 is a block diagram showing an example of the above-mentioned conventional countermeasure. In other words, the wiring from the V((() pad is laid out in two lines, one for the output transistor section 6 and one for the internal circuit. With this method, even if VCC fluctuates, the wiring from the pad is not directly connected to the internal circuit. Since no influence is exerted, the adverse effect on electrical characteristics can be suppressed.

[Problem that the invention seeks to solve]

In the conventional improved semiconductor memory device, the power supply current increases due to the increase in the power-depleted memory capacity configured as described above, and the voltage drop in Vcc caused by the instantaneous current causes the electrical characteristics to change to the shape V (for example, the output Leaks) have become a problem.

In other words, in the conventional layout method, if a minute Vect pressure drop occurs due to the operation of the internal circuit, the sixth
As shown in the figure, the output transistors 18 and 19 are laid out independently from the bonding pad 20;
Although it is fixed at the cc level, the dropped voltage is directly applied to the VCC line of the internal circuit 21 and the output transistor pre-stage circuit 5. Therefore, the output transistor 18
．． A difference in VCC level occurs between the output transistor 19 and the circuit before the output transistor. That is, VCC lines 15 and 16 in FIG.
This creates a level difference. This means that the output transistor 18.
This poses a problem when turning 19 "off" (floating state B). In other words, one output transistor is turned off.
To make the output P-channel transistor 18
'' level, it is a condition that the N-channel transistor 19 is manually supplied with an ``L level''. However, the VCC level of the circuit before the output transistor is equal to the VCC level of the output transistor.
Since it is slightly lower than CC, the N-channel transistor 19
is no problem, but the °H level that turns the P-channel transistor 18 completely "off" cannot be output, and therefore the P-channel transistor 18 is slightly "off".
The transistor is in an "on" state. In other words, the transistor is in a leaking state.

And this state is ■. , while a voltage drop of a
Therefore, there was a problem in terms of stable operation of the IC.

This invention was made to solve the above-mentioned problems, and even if a voltage drop in VCC occurs due to internal circuit operation, no output leakage current will flow, and the VCC level at the output transistor will be reduced. An object of the present invention is to obtain a memory device that can suppress the influence on internal circuits even if the fluctuation occurs.

[Means for solving problems]

In the semiconductor memory device according to the present invention, the pattern layout of vcc&1 is such that the output transistor and the output transistor pre-stage circuit are shared as a dedicated line, and the internal circuit VCC line is separated to form two independent systems.

[Effect]

In the semiconductor memory device of the present invention, the pattern layout of the Vcc line is such that the output transistor and output transistor front stage circuit are common and dedicated lines, and the VCC line for the internal circuit is separated to form two independent systems. is not affected by fluctuations in the VCC level, and the output transistor and output circuit always operate under the same voltage, allowing stable memory operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a memory cell, 2 is a decoder, 3 is an address circuit, 4 is a sense circuit, 5 is an output transistor front stage circuit, 6 is an output transistor, 7 and 8 are VCC bonding pads, and 9 is a V6. It is cotton.

The vo line is separated into two systems, and the wiring from pad 7 is connected to memory cell 1, decoder 2, address circuit 3, and sense circuit 4, and the wiring from pad 8 is connected to output transistor pre-stage circuit 5. and is connected to the outboard Langistaro. Of course, in both vcclia systems, we have taken measures to reduce the power supply current capacity by increasing the wiring width closer to the pad.

Next, the operation will be explained. The first problem is that the voltage drop is <Vcc due to fluctuations in the VCC level due to charging/discharging current in the output transistor and internal circuit operation! be. First, regarding the effect that VCC level fluctuations have on the internal circuit, the VCC line level separates the output transistor and internal circuit systems, so even if the VCC level fluctuates due to the charging/discharging current of the output transistor, the internal circuit will not be affected. This prevents the delay in access time that would otherwise occur when the VCC level fluctuation spreads to the sense circuit.

The next problem is that of output leakage due to VCC voltage drop.In the present invention, by making the layout of the VCC line of the output transistor pre-stage circuit 5 the same as that of the output transistor pre-stage circuit 5, the output transistor vc, and vcc of the output transistor pre-stage circuit 5 always operate at the same voltage level. Therefore, ■ due to internal operation. ,
Even if a voltage drop occurs, the output "H" level of the output transistor front-stage circuit 5 will be the output transistor (■). ,
The P-channel transistor (18 in FIG. 5) of the output transistor is always sufficiently cut off. Therefore, there is no leak phenomenon in the output range.

Note that in the above embodiment, Vcc in the semiconductor memory device
I explained the pattern layout of i, but this is
NDi may be used, and the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the pattern layout of the Vcc line is made common to the output transistor and the circuit before the output transistor, and is made separate and independent from the V((line) for other circuits, so that fluctuations in Vcc In addition, it is possible to suppress adverse effects on electrical characteristics such as output leakage due to internal VCC voltage drop, and the device can operate stably and accurately.

[Brief explanation of drawings]

FIG. 1 is a block layout diagram showing a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 and 3 are block layout diagrams showing a conventional semiconductor memory device,
Fig. 4 is an explanatory diagram showing the electrical influence between the output transistor and the internal circuit, Fig. 5 is an explanatory diagram showing the electrical influence between the output transistor and the circuit before the output transistor, and Fig. 6 is an explanatory diagram showing the electrical influence between the output transistor and the output transistor pre-stage circuit. FIG. 3 is an explanatory diagram showing the electrical influence between the output transistor pre-stage circuit and the internal circuit. ■ is a memory cell, 2 is a decoder, 3 is an address circuit, 4
is a sense circuit, 5 is an output transistor pre-stage circuit, 6 is an output transistor, 7 and 8 are VCC bonding pads,
9 is the VCC line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor memory device configured on the same substrate, the pattern layout of the power supply voltage line of the semiconductor memory device is configured independently for the output transistor and output transistor pre-stage circuit and for other circuits. A semiconductor memory device characterized by: