JPS6326890A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor of high speed, high integration density and low power consumption by activating and controlling a first word line connected to plural memory cell groups by a second word line connected to it and the signals of a column selection system. CONSTITUTION:In case of accessing memory cells MCko-MCkl, the second word line 2WL goes to H level by a word line driving circuit WLD, and signals CD bar + phii of a column selection system goes to L level. Then, a P channel TrQ11 is turned on and transmits the signals of the 2WL line to 1WL line. In such case, a TrQ21 for a first word line non-selection is turned off, and does not form a DC path. When the 1WL line goes to H level, memory cells MCko-MCkl become active and output stored information to a bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to reducing power consumption of a memory device, and is particularly applicable to a large-capacity semiconductor memory device.

[Technical background of the invention and its problems]

A block diagram of a conventional storage device is shown in FIG. In this figure, only one row of memory cells arranged in a matrix in the row direction and column direction, that is, the memory cells connected to one word line, is submerged in oil. The word line νVL is connected to a drive circuit WLD for this word line, and when this port is selected, the word line is at 5V, for example, and when it is not selected, it is Ov. When selected, the information stored in the memory cells M Co to M Cn is output to the bit lines B Lo to B L n. Which information from BLo to BLn is sent to the output O is determined by the column selection circuit CDC. A large number of memory cells are connected to each bit line BLo to BLn, but only one memory cell among them is activated by the word line.
Information from multiple memory cells does not overlap on the bit line.

By arranging memory cells in a matrix as shown in Figure 1, it has become possible to integrate memory cells at high density. MCn is activated all at once.

When a certain memory cell becomes image-sensitive and outputs the information stored in that memory cell to a bit line, power is always consumed. Therefore, in the conventional method in which all memory cells connected to one word line and containing information that will ultimately not be used are also activated, a large amount of power is consumed in this part. For example, in a semiconductor integrated circuit memory having a complementary MOS configuration, this portion consumes more than 90% of the total power consumed within the memory chip. Since the problem of power consumption is the problem of heat generation, conventional methods have had difficulty in achieving high density and low power consumption.

[Purpose of the invention]

The present invention has been made to reduce power consumption, which has been a problem in the past.This invention enables high-speed semiconductor memory devices with high integration density and by appropriately distributing power consumption to other parts. The purpose is to provide the following.

[Summary of the invention]

The present invention provides a plurality of first word lines connected to a plurality of memory cell groups, a second word line connected to the plurality of first word lines, and a column selection system in which the second word line and the column selection system are connected. 1. A semiconductor memory device characterized by comprising: control means for controlling activation of the first word line according to a signal.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail according to examples. A basic configuration example of the present invention is shown in FIG. 1st word line IW
A relatively small number of memory cells MCo to MCi, MCj to MC, . . . are connected to Lo to IWLn, respectively. The second word line is driven by the word line drive circuit WLD driven by the row selection signal, and is driven to, for example, 5■ when activated, and to Ov, for example, when not activated. The speed can be increased if the second word line has a word line relay circuit WA, but it is not necessary. At the connection between the second word line and the first word line, a control means, such as a transfer controller, is arranged, which is controlled by column selection signals C8O to C8n. Specific examples of this transfer and gate portion are shown in FIGS. 3 to 9. As shown in FIGS. 3 to 9, the transfer gate is composed of n-channel or n-channel MOSFETs Q to Ql.

In these figures, column selection signal CD is applied to memory cell MCk connected to first word line IWLi.

~MCkl or MCki-MCkM is a signal that becomes high level when selected, and σl is a signal having an opposite phase potential with high level and low level reversed from CD. The signal ψi is a signal for unselecting the word line, and the first
Figure 0 shows a typical signal waveform.

Next, the embodiment shown in FIG. 3 will be described in detail. Third
In the figure, when it is desired to access memory cell MCkONMCkl, the second word @2WL is the word line drive circuit W
Raised to high level by LD. Further, the column selection signal CT+ψi falls to a low level. Then, the p-channel transistor QIG constituting the transfer gate
turns on and transmits the signal on the second word line to the first word line IWLi. At that time, the first word line non-selection transistor Q. is off, so no DC path is formed. Now, when the first word line becomes high level, memory cells ~1cko~MCk are activated, and stored information is output to pit lines (not shown) connected to the respective memory cells. In this embodiment, the first word line I
When WLi reaches 7X level, memory cell MCk
oNMCkl is activated, but vice versa, for memory cells that are activated at low level, p-channel, n
In addition to reversing the channels, it is sufficient to reverse the high level and low level of the signal waveform. Further, in this embodiment, a transistor Q1° drives the first word line 1WLi.

Q! . is attached to the end of this first word line, but the first
When the delay in the word line is comparable to the delay in the second word line, driving at the center of the first word line may result in less word line delay, as shown in Figures 6 to 9. be.

In the present invention, even if the second word line 2WL is selected, all memories connected to it.

The cell is not activated, and a small number (usually only one) of the many first word lines connected to its second word line is selected; Importantly, only directly connected memory cells are activated.

Now, it is the transistor Q that deselects the memory cell. It is. The gate of this transistor goes high when the memory cell goes unselected, and therefore the first word line I W Li which was previously at high level
is lowered to low level, memory cells MCko to MCkl
deactivation is achieved.

The operation of the embodiment shown in FIG. 4 is similar to that of the embodiment shown in FIG. In the embodiment shown in FIG. 5, the second word line 2W
L is a transfer gate, and a column selection signal CI) is input to the gate of B. This results in less total capacitance visible to the second word line and therefore less delay on the second word line. In this embodiment, as shown in FIG. 10, a 2WL signal having an opposite phase to the signal 2WL is used. In the embodiment shown in FIG. 6, transfer.

Gate Q13 is composed of an n-channel MO8FET. This transistor may be an enhancement type or a depletion type, but in the case of an enhancement type, a signal is provided to prevent the first word line IWLi from becoming lower in potential than the second word line 2WL by the dark value voltage. Sometimes I pull up CDs and make them level. This pull-up level is indicated by a dotted line in the 10th FjJ. When the depletion type is used, when the selection is switched to another second word line, the second word line 2WL becomes low level, so the charge on the first word line is changed to the second word line 'fr:
Since the signal drops to low level throughout, the delay can be reduced. In this embodiment, all the drive circuits for the first word line are composed of n-channel MO8FETs, so for example, if the memory cell is composed only of n-channel MO8FETs, complementary MO8FT>T
Eliminates the need to use unique wells and reduces surface planting. Also, the latch-up problem is solved. In the embodiment shown in FIG. 7, the first word line non-selection circuit is connected to the resistance element R1.
4, and since the resistor element R74 can be formed in layers with other elements, it is possible to further reduce the area.

This resistance element R, may be constructed using a MOSFET, or may be constructed using a polycrystalline silicon layer. Transfer gate Q14 is an n-channel enhancement type or depletion type transistor. When Q+a is of the enhancement type, the first word line IW is connected as in the embodiment shown in FIG.
The signal CD may be set to a pull-flop level so that the potential of Li does not become lower than the second word line by a four-value voltage. In this example, when the transfer gate is on and the second word line goes high, the transfer gate
A DC path is formed through the Q14W resistance element 17, but this is only at one location in the entire memory and chip, and is extremely small in terms of power. Furthermore, the discharge of the first word line at the time of column switching is performed through the resistor element it, but this does not need to be taken into account since the discharge period is traditionally much longer than the access time. , Therefore, regarding the value of the resistance element, the high level of the first word line is the transfer gate Q14.
The value may be determined by taking into account that the resistance ratio of the resistance elements 17 and 4 is determined. In the embodiment shown in FIG. 8, the discharge of the first word line IWLi is mainly caused by the transfer gate.
) through Qts, but this transistor Q
Only the four-value voltage +a is handled by the resistive elements 11+, . In the embodiment shown in FIG. 9, the control gate of transfer gate Q+a is connected to the second word line 2.
In this example, the source of WL is connected to the column selection line CI), and discharging is partially performed by the resistor element R27. In this embodiment, the signal 2WL shown in FIG. 10 is used.

Figure 11 shows a typical static R,AM memory.
It shows a circuit diagram of a cell MCkl.

The load elements 110 and 111 may be p-channel MO8F'ET or high/low, 4, or hyperpolycrystalline silicon. Load element 1
10゜111, If the remaining MOSFETs are configured, as shown in Figure 11, the dotted line indicates MOSFET 11.
Connected to the gate of 0.111. FIG. 12 is a plan view and FIG. 13 is a cross-sectional view of an embodiment of the present invention for a high resistance polycrystalline silicon memory cell format.

In FIGS. 12 and 13, parts corresponding to the circuit elements in FIG. 11 are given the same reference numerals. Here pit line BLk
x, BLk4 is not shown in FIG.
As shown in Figure 3, it is generally made of aluminum. Also, Fig. 12.

As shown in FIG. 13, the dotted lines surrounded by circles indicate transistors 112-115. The second word line 2WL is formed on the first word line IWL using a second layer of polycrystalline silicon. The second layer polycrystalline silicon thereby also forms a high resistance load 110° 111, but is partially diffused or coated with a third low resistance layer (e.g. a layer of Mo b r ).
The resistance is lowered by stacking the second word line 2WL.
It can be fully used as This allows for more memory than before.

It is possible to achieve low power consumption without increasing the cell area at all.

Further, as shown in FIG. 14, one second word line 2WLi
Two first word lines 1'TV L i on the side of j.

By arranging 1WLj, the 27th word line j42WLij can be shared by the two first word lines IWLi and IWLj, as shown in FIGS. 15 and 16.

In this embodiment, it is desirable to form the second word line wide as shown in FIG. 16 in order to reduce the resistance of the second word line and the delay of the second word line.

Although the above description shows the case where the second word line is formed of polycrystalline silicon, the present invention is not limited to this, and the second word line may be formed of a second aluminum layer. In this case, compared to the case where it is formed of polycrystalline silicon, the capacitance is reduced because it is further spaced from the first word line, and since aluminum has a low resistivity, it has the advantage of further shortening the delay time. .

〔Effect of the invention〕

As described above, in the semiconductor memory device according to the present invention, even if one second word line is selected, unlike the conventional case,
All memory cells connected to it are not activated. A number of first word lines connected to that second word line.
Among the word lines, only one first word line is selected and only the memory cells directly connected to that first word line are activated. .

Therefore, only the necessary memory cell information is output to the bit line, eliminating unnecessary memory as in the past.

There is no need to activate cells. Activating memory cells increases power consumption, but according to the present invention, since only some memory cells are activated, a memory with low Vt* power can be provided.

For example, in a static RAM with a 32 word x 8 bit configuration, conventionally the number of memory cells connected to one word line is 256 in a two word line division method, meaning 256 memories at one time.

It was necessary to activate the cells. According to the invention, the first
By connecting 8 memory cells to each word line, 8 bits of memory are required at one time.

Only the cell will be activated. i.e. 8/256
= Power consumption can be drastically reduced to 1/32. Since the power consumed around this memory cell accounts for 90% or more of the power consumed inside the entire memory chip, the present invention makes it possible to manufacture memories and chips with extremely low power consumption.

Given that the number of elements in very large scale integrated circuits is limited by thermal considerations, the present invention also enables the fabrication of memories with high integration densities. Moreover, by appropriately distributing the surplus power, it also contributes to speeding up the memory.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional semiconductor memory device, and FIG.
The basic configuration diagram of the semiconductor memory device according to the present invention, FIG.
A diagram showing a first embodiment of a semiconductor memory device according to the present invention,
4 to 9 are diagrams showing other embodiments of the semiconductor memory device according to the present invention, FIG. 10 is a waveform diagram for explaining the semiconductor memory device according to the present invention, and FIG. 11 is a waveform diagram for explaining the semiconductor memory device according to the present invention. A circuit diagram showing an embodiment of a memory cell of a semiconductor memory device according to the present invention, FIG. 12 is a plan view showing an embodiment of the semiconductor memory device according to the present invention, and FIG. FIGS. 14 to 16 are a cross-sectional view taken along line B-B' in a block diagram, a plan view, and a plan view showing other embodiments of a semiconductor memory device according to the present invention, respectively. It is a sectional view taken 1J. In the figure, IWLo to IWLn-...first word line 1MCo to MCi, MCj to MCn-memory cells, TRo to TRn...switch means 1WLD
...Word line drive circuit. Agent: Patent Attorney Noriyuki Chika! Take Hana Kikuo 1st I21 2nd figure 6÷φ to 3rd figure 4 figure CD+ψn CE) figure 5 Cf) figure 7 C'1 figure 9 figure 10 abuse EILK+ 11 figure times consecutively 1 Figure 112 Day L BL Figure 15

Claims (4)

[Claims] (1) A plurality of memory cell groups, a plurality of first word lines connected to the plurality of memory cell groups, and a plurality of MOSFETs whose drains are connected to the plurality of first word lines.
a second word line commonly connected to the gates of the plurality of MOSFETs; and a plurality of column selection signal lines connected to the sources of the plurality of MOSFETs. (2) The semiconductor memory device according to claim 1, further comprising means for setting the first word line to a different logic level when it is not selected than when it is selected. (3) A plurality of memory cell groups, a plurality of first word lines connected to the plurality of memories and cell groups, and a plurality of MOSFETs whose drains are connected to the plurality of first word lines.
a second word line commonly connected to the sources of the plurality of MOSFETs; and a plurality of column selection signal lines connected to the gates of the plurality of MOSFETs. (4) The semiconductor memory device according to claim 3, further comprising means for setting the first word line to a different logic level when it is not selected than when it is selected.