JPS63267931A - Camera - Google Patents

Abstract

PURPOSE:To prevent a failure caused by the misoperation of a camera by making an interval photographing means by a second switching means not actuate if a first switching means is OFF. CONSTITUTION:When the second switching means 25 is switched ON at the time of interval photographing, the time of an interval timer is displayed on a liquid crystal display part 38, for example with subtraction display, so as to execute the interval photographing if the first switching means 53 is ON. Meanwhile, since an interval photographing means does not start actuation if the first switching means 53 is OFF, the subtraction display is not executed on the liquid crystal display part 38, so that it is decided that the first switching means 53 is in an off-state. Thus, the failure that photographing is not executed by the misoperation of the camera can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a means for controlling an interval timer during interval photographing of a camera.

<Prior Art> Conventionally, in the interval timer of a camera equipped with a back cover data imprinting device, it was possible to set the timer time and start counting even when the main switch of the camera body was off. However, if the main switch on the camera body was turned off, the camera would not be able to take pictures.

<Problems to be Solved by the Invention> In the prior art described above, when the photographer forgets to turn on the main switch of the camera body and starts the interval timer, he later realizes that no pictures have been taken and regrets it. There was a problem with that.

In view of the problems of the prior art mentioned above, the present invention provides a camera that prevents the timer from starting if the main switch of the camera body is turned off during interval timer photography, thereby reducing the chance of failure in photography. The purpose is to

<Means for Solving the Problems> The configuration of the present invention for achieving the above-mentioned object will be explained (using FIGS. 1 to 3).

The present invention includes: a first switch means 53 that centrally controls each function of the camera; an interval photographing means that performs a shirt release operation based on a shirt release signal outputted from an interval timer circuit at predetermined intervals; and a second switch means 25 for starting the operation of the interval photographing means, and displays on a liquid crystal display section 38 the time from when the second switch means 25 is activated until the shirt release operation is performed. In the camera configured as follows, the first
When the switch means 53 is off, the second switch means 25 does not operate the interval photographing means.

Effects> When the second switch means 25 is turned on during interval photography, if the first switch means 53 is on, the interval timer time is displayed on the liquid crystal display 38, for example, by subtraction, and interval photography is performed. If the first switch means 53 is turned off, the interval m shadow means will not start operating, so the subtraction display will not be displayed on the liquid crystal display section 38, and the first switch means 53 will be in the off state. can be judged.

Therefore, it is possible to prevent failures such as not being able to take pictures due to camera operation errors.

<Embodiment> The system of the embodiment of the present invention will be described below with reference to FIGS. 1 to 18.
This will be explained based on the diagram.

First, FIG. 3 is a block diagram showing the circuit configuration of a data imprinting device with an interval timer function.

In the figure, the part to the right of the broken line is the control circuit inside the camera body. 1 is a microcomputer central processing unit N (hereinafter referred to as CPU) that sequentially controls the overall operation of this system, changes the watch and calendar, and controls the timer; 3 is where the camera battery 2 is inserted. This is a 100 circuit that generates a power-up clear signal.When this signal is input to the CPU1 reset (RE> terminal, the CPU
1 is reset. 4 is the reference clock pulse (CLK
), which is input to the CLK input terminal of CPtJl and at the same time synchronizes the entire circuit operation of this system. 5 is a frequency dividing circuit which divides the frequency of the CLK pulse, creates a 32H2 pulse in this embodiment, and outputs the 32H2 pulse of CPU1.
It is input to the ziNT terminal. 6 is a TRi timer that counts the lighting time of the data imprinting lamp 14, and when the count reaches 0, it inputs the TRi N7 interrupt signal of the CPUI. 7 is R that stores the program contents
OM, 8 is a RAM that inputs and outputs data.

10 is a monitor LCD, 11 is a data imprinting LCD, both of which are installed inside the back cover 45 of the camera as shown in FIG.
) terminal, common (COM> terminal, RFC terminal, and PIM terminal) based on the data imprinting contents, interval timer operation status, imprinting accuracy (REC) mark 37, and information (PIM) mark 36. Perform display, etc.

Next, the data imprinting circuit
The buffer 15 connected to the i terminal (TRi) is connected to the base of a transistor 12 and the emitter of a transistor 13 for driving the data imprinting lamp, and the collector of the transistor 12 is connected to the positive electrode of the power supply battery, and the emitter is The transistors 13 are connected to one terminal of the imprint lamp 14, respectively.
In order to drive the lamp 1 with a constant voltage, its base is connected to the output terminal of the constant voltage circuit 16, and its collector and the lamp 1
The other terminal of 4 is grounded.

Further, an N-channel MOS transistor 18 is connected to the iNT terminal of the I10 boat 17, and this MOS
When the transistor 18 turns on, the camera body 48
A low level can be given to the 5ELF terminal of the camera sequence control circuit 52 in the same way as when the side self-timer switch 50 is turned on, and the 5ELF terminal is pulled up when the MOS transistor 18 and the self-timer switch 50 are turned off. It is pulled up by a resistor 51 and given a high level.

19 is a serial interface circuit into which various information from the camera body 48 is input, and its chip select (C
8) The serial clock (SCK) terminal and the serial data input (SDI) terminal are respectively connected to the camera sequence control circuit 52, and when a serial code is input, the CPU 1 is connected to the CPU 1 in order to generate an interrupt. It is also connected to the 5iOiNT terminal.

Furthermore, the terminal So of the I10 boat 17.

Sl, 32.83.34, Ss are data imprinting mode selector switches 20. Imprint data and interval timer time correction switches 21, 22, 23, elapsed time imprint mode selection switch 24, and interval timer mode switch 25 are connected to pull-up resistors 26, 27, 28, 29, and 30, 31, respectively. Each is connected and pulled up.

Then, the CPU 1, TR + timer 6, ROM 7,
The RAM 8, I10 port 17 and serial interface 19 each have an address bus 32. They are connected by a data bus 33 for transmitting and receiving data and a control bus 34 for controlling their timing.

Note that 53 is a main switch of the camera body, which is pulled up by a pull-up resistor 54 when it is off, and is connected to the main switch (MS) of the camera sequence control circuit 52.
W) Connected to one child.

Next, FIG. 1 is a rear view of the camera, and FIG. 2 is a sectional view of its main parts.

Reference numeral 45 denotes a back cover, on which the monitor LCD 10 is arranged so as to be visible from the back side, and the switches 20 to
25 is operable.

This monitor LCD 10 has a film counter display section 35. A photographing status display mark 36 on the camera body, a data imprinting confirmation mark 37, and a display section 38 for checking imprinted data selected by the switches 20 to 25 are provided.

Further, on the inner side of the back cover 45, the data imprinting LCD 11 connected in parallel to the monitor LCD l0 is arranged, and the display data of the data imprinting LCD 11 is displayed by the imprinting lamp 14. Camera body 46
It is designed to be imprinted on the F side of the film on the side.

The operation of this embodiment with the above configuration will be explained.

First, the display section 38 for confirming imprint data is displayed.

An outline of the interval timer mode and elapsed time imprint mode will be explained.

First, regarding the display on the imprint data confirmation display 38, each time you turn on the data imprint mode changeover switch 20, the display 38 displays calendar data as 1 year, month, day, month, day, year. ``Day/Month/Year''``Day/Hour/Minute'' and ``Information imprinting mode for the number of film shots'' (hereinafter referred to as FC mode) are sequentially switched and displayed. This display section 38 has a segment arrangement that can display the abbreviations of nine English names, and when the switch 20 is turned on, it displays the numerical month (6th
In addition to the English text (Fig. 5), you can also selectively display the English text (Fig. 5).

In addition, the display may include "Year/Month/Day""Month/Day/Year""Day/
When displaying calendar information such as month/year and day/hour/minute, each display is changed to the imprint data correction switch 21.
．． Increment by turning on 22 and 23.

Next, regarding the interval timer mode, when the interval timer mode switch 25 is turned on, the display section 3
8, regardless of the previous data imprinting mode, the mode shifts to the interval timer mode, and the time Ti from when the release button is pressed until the release signal is output is displayed in hours and minutes (FIG. 9). This display is corrected by switch 22.2.
It can be fixed in 3.

In this state, the interval timer mode switch 25
When turned on, if the main switch 53 of the camera body 46 is turned on, the display adds a display in seconds as shown in FIG. 10 and starts operating as a subtraction timer. however,
When the main switch 53 of the camera body 46 is off, the display section 38 returns to the display form before entering the interval timer mode, and no countdown is performed. The display section 38, which operates as a subtraction timer, displays the display before entering interval timer mode 10 seconds before release!
! ! Returning to FIGS. 5 to 7, the circuit of the display section 38 sends a self-timer activation signal to the camera body 46.

When the release signal is input to CPtJl via the serial interface 19, the display unit 38 starts operating as a subtraction timer again while displaying the time Ti in seconds. If the release end signal is not input to the CPU 1 within a certain period of time from when the self-timer is activated, the display section 38 returns to the display form before entering the interval timer mode and the countdown is not executed. If a release signal is input to the circuit from the camera body side while the interval timer is counting down, or if the data imprinting mode switch 20 is turned on, the countdown will stop and the display unit 38 will display the display before entering the interval timer mode. Return to form.

Furthermore, elapsed time imprint mode (hereinafter referred to as rPA mode)
), when the elapsed time imprinting switch 24 is turned on, the display section 38 enters the elapsed time display mode regardless of the display state of the previous data imprinting mode.

When the switch 24 is on, the year, month, and day, which are the starting points for elapsed time calculation, should be displayed (Fig. 11).
4 is pressed, the starting point (year, month, Φ day) can be modified using modification switches 21 to 23.

If the year, month, and day can be displayed in the display format before entering PA mode, they will be displayed in that format. "Mode" For hours, etc., the year, month, and day are numbered first.
Display in the order shown in Figure 1.

When the switch 24 is turned off, the elapsed time (current date - starting date) 8T is displayed, and when a date signal is input from the camera body to the circuit of the display unit 38, ΔT is imprinted.

Needless to say, the elapsed time ΔT is updated at the same time as the current date is updated.

The display form of the display section 38 is as shown in FIGS. 12 to 14, when ΔT>12 months, "year/month" display (first
(Figure 2), if ΔT≦12 months, “month/day” display (first
(Fig. 3), and if ∆To≦0, then ∆Too is reached.
0 months, 0 days” (Figure 14).

Regardless of the display form of the display section 38, when the data imprinting mode changeover switch 20 is turned on, the display section 38 returns to the current date display form before entering the PA mode.

By using the above shooting number imprinting mode (FC mode), interval timer mode, and PA mode in combination, it is possible to imprint not only the date and time, but also the record number and the number of days elapsed on photos recorded at fixed time intervals. This makes it very easy to record and organize photos.

Next, a description will be given of the information input unit that is input from the camera body 46 via the serial interface 19 in the system of this embodiment.

In this embodiment, data imprint signals, film counter information, and various camera information are input from the camera body.
As shown in Table 1, each 4-bit unit from Do to D3 is 1 in total.
A 6-bit serial data transfer is being performed. DO and Dl
are the 10s digit and 1s digit B of the film counter, respectively.
These are C and D codes. Next, D2 indicates a data imprinting signal and various information. When b3 (MSB) is 1, it is a data imprinting signal, and the lamp lighting time for data imprinting is determined by the value of the lower 3 bits (b2.bl, bo). ga to-t
It can be changed to ylsec. On the other hand, when b3 of D2 is 0, the photographing information mark (PIM mark) is turned on when b2=1, and the PIM mark is turned off when b2-0. Further, in the case of b3=O, if b1=1, the main switch 53 of the camera is in the on state, and if bl-0, the main switch 53 is in the off state. These latches the previous state at b3-1. Note that D3 is 4 spare bits.

DODl HSB LSB HSB LSB
Rorororo Rorororo Counter 10 digit Counter 1 digit D2
D3 H3B LSB HSB
LSB[ A4 QXXX: Do not imprint 1000: to m5ec 1001: tlmsec 1010: t21msec 1011: t3msec 1100: t, tllsec 1101: t51sec 1110: temsec 1111: ty m5 ec QlXX: PIN mark 0N 00xx: PIN mark OFF □x1x: Main body main switch 53 ON state 0×O×2 Main body main switch 53 OFF state Table 2-2 RAM Table 2-3 RAM Table 2-4 RAM Table 2-5 RAM Table 2-6 RAM Next, the contents of the data memory of RAM8 are displayed. 2, the address label is shown on the left and its contents are shown on the right, as outlined below.

First, 5TATLISO(7)b2 (MSB)-1+
7) Hours indicate a display other than normal data imprint display, such as PA mode display or interval timer display, and the lower 3 bits b2 and bl.

bo indicates normal data imprinting mode and “00
0" is the imprint mode off, "001" is the year, month, day mode, "010" is the month, day, year mode, "011" is the day, month, year mode, "i o o" is the date, hour, minute, and "101n is frame counter copying. Indicates embedding mode.

At b3-1 of 5TATLISI, the TRi port is in the high (H) level output state, and at b2-1, the interval timer outputs the iNT port-H level until the main switch 53 status signal is input from the camera body 46. bl-1 indicates a timer operation state in which the interval timer performs a decrement Wij11 operation, and bo is unused.

5TATUS2 is switch 2 in Figure 1 when it is b3-1.
1 to 23 indicate a correction state in which some data is being corrected, b2 is unused, bl -1 indicates the reference date setting state of the PA mode, and bo -1 indicates the timer time setting state of the interval timer. show.

STΔTUS3 is a flag indicating a display request when a change occurs in the contents of the LCD display when it is bl-1.

5TATUS4 indicates that when b3-1 is set, it is in interval timer mode and the imprint content is in PA mode.
Lower 3 bits b2, bl, b.

is a bit that specifies the display state; when it is "010", it displays the reference date in PA mode, when it is "011", it displays the elapsed time in PA mode, and when it is "100", it displays the interval timer setting.
'101' indicates the interval timer subtraction display state.

5TATtJS5 is RFC boat = H when b3-1
Indicates the level output state, b2, bl, b.

is unused.

5TATUS6 is in the state where the interval timer has less than 10 seconds remaining when it is bl-1, and when it is bO-1, it is iNT
In the boat=H level output state, b3. b2 is unused.

Furthermore, 5ECONDO~YEAR1 stores the current time, the calendar's first digit of the second to the tenth digit of the year, and PDAYO
-PYEARl stores the first digit of the day to the 10th digit of the year of the reference date in the PA mode.

TRXMO~1- RX H1 is the minute 1st digit to hour 10th digit of the interval timer setting time, TR8ECO~
TR1-10UR1 indicates the first digit of the second to the tenth digit of the hour for the subtraction count of the interval timer.

When swxo is b3-1, switch 23 is pressed, b
When 2-1, the switch 22 is pressed, when b1=1, the switch 21 is pressed, and when bo-1, the switch 20 is pressed.

Similarly, in 5WYO, when b1=1, switch 24 is pressed, b
o −1 indicates the pressed state of the switch 25, and b3
．． b2 is unused.

5i03B~5tOOB are serial data C3~DO
4 bits each are read and stored.

5iOC is a counter that counts the number of clocks as the serial code is input.
, Dl, C2, C3) buffer (Si03B, 5i0
2B, 5i01B, 5iOOB) is reset to 0 when reading is completed.

C0UNTO and C0UNT1 are each 32H for 4 o'clock.
2 and 4 Hz counters, C0UNT3 and C0UNT4 are respectively 32H2 and 4]11 counters for interval timer, C0UNT5 and C0UNT6 are also 32H counters, respectively.
These are Hz and 4H2 counters.

i NTCNT is 32 when iNT boat-H level output
This is a counter that counts the iNT boat output time for each HziNT interrupt.

FRO and FRI each store the 1st digit and 10th digit in the frame counter mode of the data imprinting mode.

Next, the sequential operation of the microcomputer will be explained based on the flowcharts of FIG. 15 and FIGS. 16-1 to 16-18.

First, FIG. 15 shows an outline of the program. This program is roughly divided into four blocks.

First, the initial settings for A. After turning on the power and canceling the reset, clear the memory area and set the initial display data.
After finishing the part where display contents are arranged, the CPU 1 enters the I-I ALT state in which internal data is held. B
3211ZiNT is a processing sequence for interrupts that occur 32 times per second due to the 32H2 pulse output by the frequency divider circuit shown in Figure 3. Switches 20 to 25 are monitored, and when a switch is pressed, it corresponds to the pressed switch. When the above processing is performed and the number of interrupts is counted 32 times, a carry of 1 second is generated and the clock and calendar are incremented. The C5iOiNT lights up the data imprinting lamp and processes the input of camera information in the serial interrupt processing sequence that occurs when the serial code from the camera is input.

In the timer interrupt processing sequence that occurs when the RTiNTl and tTRi timers of D are counted up, the processing at the end of lighting the data imprinting lamp is performed.

Furthermore, this embodiment will be explained in detail according to the flowcharts shown in FIGS. 16-1 to 16-18.

When the Tl source 2 is turned on, the microcomputer is initially reset by a reset (RE) signal generated by the PUC circuit 3, and starts operating from step #OO1 of the program as shown in FIG. 16-1.

In #002, the memory area is cleared, and in #003, the initial display mode of the data imprint mode is set to
The mode is set to "month/day" mode, and the year, month, and day of the calendar is set to, for example, "January 1, 1987" in #004. Then #0
Clear the stack point area with 05 and #00
After enabling interrupts at step 6, the microcomputer enters the HALT state, which is a data holding state, at #007.

Next, when the 32t (ziNT interrupt signal) is input to the CPU 1, the operation starts from #101 as shown in FIG. 16-2. In #101 and #102, the status of each switch is read from the switch input port.

Next, #104. #105. #106. #107,
#108. #109 (9108 and #109 are shown in FIG. 16-6) and changes in the states of the switches 20 to 25 are determined, and if the switch states have changed, corresponding processing is performed. This process will be described later. On the other hand, if no switch status has changed, #109 to #201
(Figure 16-7).

Here, a case where each of the above-mentioned switches is pressed will be described.

First, the switch 20 is pressed, and when it is determined in #104 that the switch 20 is pressed, #129° #130. #
131. #132. #134. #135 and #2
Continuing to step 01, if it is determined in #129 that the display content is the elapsed time display in PA mode, or if it is determined in #130 that there are 10 seconds left in timer mode, the PA mode or timer mode is canceled in #132. subroutine RTCANCL is called. On the other hand, timer 1
If the state is not 0 seconds ago, it is further determined in #131 whether the display state is normal mode. If the mode is other than normal mode, press R at #132 in the same way as when the timer is 10 seconds before.
Call TCANCL. This timer cancel subroutine RTCANCL processing will be described later. After the timer cancellation process, the process moves to #201.

Now, if the display mode is determined to be normal mode in #131, 5TATUSO is incremented by 1 in <#133, thereby advancing the data imprinting mode by one. Next #134. When 5TATUSO-6 is determined in #135, set the data imprint mode to ``Year/Month/Day'' → ``Month/Day/Year'' by setting it to 5TATuso-o.
“Day/Month/Year” → “Day/Hour/Minute” → rFC mode” → “
It cycles through 6 modes: ``off mode''.

Next, a case where the correction switches 21, 22, and 23 are pressed will be described.

When it is determined in #105 that the state of the switch 21 has changed, the state of the switch after the change is determined in #105A, and if it is in the pressed state, b3- of 5TATLIS2 is determined in #140.
1 and set it to the modified state. Since the display contents changed in #141, in order to update the display, 5TATUS3's bl-
1 and a display request flag is set. Then #142
Based on the values of 5TATLISO and 5TATUS4, it is determined which data corresponds to the switch 21, and the corresponding data is corrected. Details will be described later. After the correction process is completed, the process advances to #201.

On the other hand, in #105A, if it is determined that the switch state after the switch state change is off, 5TATLJ is determined in #143.
The correction state is reset as b3-0 in S2, and the display request flag is set as bl-1 in 5TATUS3 in #144. Regarding switch 22゜23, #106. #10
The processing after the change in the state of each switch is confirmed in step 7 is the same as that for switch 21, and will therefore be omitted. switch 22.2
In the case of 3, the process also proceeds to #201 after the correction process.

Now, if the switch 24 is pressed next (16-6
In FIG. 10, when it is determined in #108 that the state of the switch 24 has changed, the state of the switch 24 after the state change is determined in #160. If it is determined that the switch 24 is on, the interval timer mode cancel subroutine RTCANCM is called at #170, and the interval timer is canceled. This subroutine RTCANCM will be described later.

Thereafter, in #171, the 5TATtJS@PA mode reference date setting state is set, and in #172, the display mode is set to PA mode reference date setting display. #173 is a subroutine EXT that displays modes other than normal display.
A DSP call is made.

After that, proceed to #201.

On the other hand, if the switch 24 is off after the state change in #160, it is determined in #161 whether the PA mode reference date is set, and if it is in the setting state, the PA mode is set to elapsed time display mode in #162, and in #163 (STATUS2) 1-0
and cancel the PA mode reference date setting status, #2
Proceed to 01.

Next, regarding the process when the switch 25 is pressed down, when it is determined in #109 that the state of the switch 25 has changed, it is determined in #110 whether the interval timer is already in an operating state.

Therefore, if it is determined that the interval timer is not in the operating state, it is further determined in #111 whether the interval timer is in the timer time setting state. If the interval timer is not in the time setting state, proceed from #121 → #201 #
At step 121, the program jumps to subroutine TRMS for setting the interval timer mode.

Therefore, the interval timer mode setting process will be explained first with reference to FIG. 16-11. 5TAT with #121
Set the US to the interval timer time setting state, and press #
In step 122, all digits from the first second digit to the tenth digit of the hour of the timer's counting watch are cleared to 0, and in step #124, the EXTDSP subroutine is called to perform display processing other than the normal mode. This subroutine will be described later. Next, in #124, it is determined whether the mode is interval mode and the data imprinting mode is PA mode, and if the data imprinting mode is other than PA mode, it is further determined in #125 whether the display state is PA mode elapsed time display. If the elapsed time is displayed, 5TAT is displayed in #126.
The third and second bits of tJS4 are set, and 5T
Set the ATIJS to the interval timer setting state and the data imprinting mode to the PA mode state. #1
The same holds true when it is determined that the third bit of 5TATUS4 is set at step 24. On the other hand, if the imprint mode is determined to be non-PA mode in #125, #127
is set to the interval timer setting display state.

After completing the interval timer mode setting, the process advances to #201. If it is determined in #111 that the interval timer time is set, #113. The process advances to #114, and the interval timer starts operating from then on. At #113, the 1NTACT subroutine that activates the INT vote is called.

The i-NTACT subroutine begins at #730 (Figures 16-18). In #731, iNT boat=H is output, and in #732, the iN lower boat output time is counted. i
Set the initial value of the NTCNT counter, #733
The iNT boat=H output status flag is set.

Next, in #114, the interval timer time setting state flag is reset, in #115, ST input ■US is set to the main switch state signal input wait state according to the serial code at the time of starting the interval timer, which will be described later, and in #116, the timer timer is set to the main switch state signal input wait state. It is set to operating state. Next, set the display request flag in #117, clear the interval timer's first and tenth digits to 0 in #118, and #
At step 119, the timer time from the first minute digit to the hour tenth digit of the interval timer setting time stored when the timer was started is copied to the RAM area where it is actually counted down. After that, proceed to #201.

Here, a method for determining each mode and correcting data when the above-mentioned correction switches 21, 22, and 23 are pressed will be explained in detail with reference to FIGS. 16-3, 16-4, and 16-5.

First, in the case of modification at switch 21, the 16th
In Figure 3, it is determined at #800 whether the MSB of 5TATIJSO is set, and if it is set, it is determined that the display is in a mode other than normal mode. On the other hand #80
1, if the PA mode is determined and the display format is "month, day, year", the corresponding digit of switch 21 is "
month'', the 9-digit PMONTH of the elapsed time reference date is incremented in #804. On the other hand, if the display format is "day/month/year", the corresponding digit is "day"
Then, in #805, the day digit of the elapsed time reference date PDA'
Y is incremented. Display format is "Month/Day/Year"
, if the state is neither "day/month/year", the reference date display format in PA mode will be "year/month/day", so the corresponding digit will be the year digit, and the year digit PYEAR will be incremented in #803. Ru. On the other hand, if it is determined in #800 that the display mode is the normal display mode, the process in #806. #807. #808, #
The display mode is determined in step 809, and the display mode is determined in step #811. #
812. #813. At #814, the corresponding digit of the switch 21 is incremented.

Next, regarding the correction process when the switch 22 is pressed, the first
5T at #820 in the same way as the process of switch 21 in Figure 6-4.
If the MSB of ATUSO is set, it is determined that the display content is outside normal mode, and if the display content in #821 is the interval timer time setting display, #825
The timer hour digit TRXHOUR, which is the digit corresponding to the switch 22 displaying the timer time setting, is incremented.

On the other hand, #823. #826 or #823-#824
The correction of the corresponding digit of the PA mode reference date by the switch 22 is the same as that for the switch 21.

On the other hand, when it is determined in #820 that the mode is normal display mode, the display mode is determined to be in #827 as in the case of the switch 21 described above. #
828. #829. The display mode is determined in #830, and the corresponding digit of the switch 22 is incremented in #831. #8
32. $833. This is done in #834.

Regarding the correction process when switch 23 is pressed in R violation, the 16th
-5 figure, #840. As in the case of the switch 22, the interval timer time setting mode is determined in #841, and the timer minute digit (TRXM i N) corresponding to the switch 23 is incremented in #845. On the other hand, #847 in case of normal display. #848.
#849° #850. Determine the display mode with #851,
#852, t$853. #854. #855. #856
The digit corresponding to switch 23 is incremented in the same manner as in the case of switches 21 and 22.

Next, when the monitoring process for each of the switches 20 to 25 described above is completed, the 32 Hz interrupt process continues to the watch increment process and the timer down count process starting from #201 (FIG. 16-7).

That is, in #201, it is determined whether the iNT boat is in an active state. If the iNT boat is active, #
202 is the iNT boat output time counter i NTCNT
Increment by 1 day and set this i NTCNT at #203.
-0 is determined, and if it is iNTCNT-0, the rNTSTP subroutine is called in #204 to set the iNT boat to L. This iNTSTP subrange will be explained from #750 in Figures 16-18.

In #751, it is set as iNT boat-H, and in #752, it is set as iNT boat-H.
Canceling NT boat active state. Here, the iNT boat output time is 1/32Hz x 7 times - 21 since the initial value of the 1NTCNT counter is 7.
It becomes 81sIBc.

Next, steps #205 to #210 perform watch and calendar increment processing for data imprinting. #
C0IJNTO of 32Hz counter for watch with 205
If it is #206T-COUNTO-8, it outputs a carry of 4H2, increments C0tJNT1 of the e207r4Hz counter by 1, and at the same time clears C0UNTO to O in #207A. Next, in #208, it is determined whether C0UNT1-4, and if it is 4, a carry of 1 second is output in #210, and in #210
The watch and calendar are incremented. #
In step 211, it is determined whether the timer is in operation, and if the timer is in operation, the determination in #212 as to whether the REC port is in the H output state is not performed. In other words, when the interval timer is operating, a separate counter is used to count down the timer setting time, and when the data imprinting confirmation mark (REC boat) is output, it is not output. It is used to count the time that
If the interval timer is operating or the REC port is outputting daily output, do not count from #213 onwards.
Jump to steps after 250. Here, if the interval timer is operating or the REC port-H is being output, a separate 32
Increment Hz counter C0UNT3 by 1 and set #2
14? Determine if 'C0LJNT3-81' is present 16°C0
If LJNT3-8, 4 H2(7) Kit' I)
Q Raw L, the 4Hz counter C0UNT4 is incremented at #215 in Figure 16-8, and the 32Hz counter C0UNT3 is cleared to O at #216. Next, #218
, d3 at #219, it is determined whether the counter content of C0UNT4 is 4 or more, and if it is 4 or more, the timer generates a carry of 1 second. In this state, #22
If the value is 0, it is determined whether the interval timer is in operation. If the interval timer is in the operating state, it is determined in step #221 whether the main switch state is the main switch state or the signal input wait state according to the serial code when the timer is started. If it is not in the wait state, the process advances to #222, and after the display request flag is set, the subroutine RLTi performs countdown processing of the interval timer in #223.
MER is called. Next, this RLTiMER will be explained with reference to FIG. 16-10. RLTiMER starts processing from #301, and since the timer counter generates a 1 second carry in #219 mentioned above, #301
In case of 2, 1 is subtracted from the first digit of the second TR8ECO of the interval timer, and in #303, the first digit of the second is determined, and in the case of O, 1 is subtracted from the 10th digit of the second. next,
In #304, it is determined whether or not the microcomputer's zero flag is set as a result of subtraction from the 10th digit of the second. If it is set, J3 is analyzed in #305, and if the zero flag is set as a result of the analysis, the time is determined. Digits are decremented sequentially. Next is #306. #307. #308, minute digit - ○, hour digit - ○ and 10th digit of seconds - 1, 1st digit of seconds - 0,
In other words, it is determined whether it is 10 seconds before the interval timer count up, and if it is 10 seconds before, the iNT activates the aforementioned iNT boat in #309.
The ACT subroutine is called. For example, if the self-timer of the camera body is 10 seconds, the self-timer starts counting by determining 10 seconds ago and setting the iNT boat to H level.

Next, in #310, set 5TATUS so that the interval timer has less than 10 seconds remaining, and in #311, set 5TATUS
By resetting the third bit (83B) of IJSO, the display of the data imprinting contents is returned from the display of the countdown of the interval timer. Next, since a change occurs in the display contents, a subroutine MDCLR for clearing the data display area is called in #312.

This MDCLR processing is #395 in FIG. 16-15. #3
96, a display request flag is set in #395, and a blank is output to each display digit in #396 to clear the display area.

On the other hand, it is determined whether C0UNT4 of the #225rJHz counter is greater than 8. If it is, a 2-second carry occurs as shown in #226, and a data imprinting confirmation mark is output in #227! (RFC boat-H), #2
At #28, the RFC port is set to L, the RFC mark 37 is turned off, and at #229, 5TATUS is reset to the data imprinting confirmation mark output state flag. Next, #250
It is determined whether it is C0UNTO-0 (Figure 16-9), and if it is not 0, the state of the display request flag is checked in #251, and if the request flag is set, 5TATUS is determined in #259.
The display mode is determined based on the states of O and 5TATUS4, and display contents according to the mode are output to the LCD driver 9. In that case, reset the display request flag in #260,
Enters HALT state at #280. On the other hand, if C0UNTO=O in #250, a carry of 4H2 occurs, and in #252 it is determined whether the interval timer has less than 10 seconds left, and if it is within i oou, then in #253 Further, it is determined whether the interval timer is counting down, and if it is not counting down, the first second digit TR8ECO of the timer is incremented by one in #254. Next, TR8ECO at #255
It is determined whether the value has become 8, and if it is 8, the 10th digit of the timer is incremented by 1 in #256, and at the same time, in #25
Cleared TR8ECO at 6A.

In #257, it is determined whether this TR8ECI is greater than 1'O, and if it is greater than 10, more than 20 seconds have passed since the timer counted up (4Hz x 80 counts), so the interval timer is canceled in #258. The RTCANCM subroutine is called. RT
The CANCM subroutine will be described later. 5 in #259 after interval timer mode is cancelled.
The mode is determined based on the value of TATUSO, 5TATLJS4, a display is made according to each mode, and then the HALT state is entered. If the display request flag is not set in #251, the display contents are not changed and a HALT state is entered.

Next, the process when a serial code is input from the camera body will be explained with reference to FIGS. 16-12.

When the serial interrupt signal of CPtJl is input, the program starts the processing operation from S i Oi NT#501. At #501, it is determined whether the content of the 5iCNT counter that counts the number of pulses of the serial synchronization clock is 16 or not. If it is other than 16, the serial data input at that time is invalidated and enters the T state. On the other hand, if the number of clocks is 16 and the data is valid, divide the contents of each serial buffer into 4 parts of 4 bits each in #502.
The pit portion is Sioo, Siol, Si02. S
i.

3iCNT in each RAM area in #503.
The contents of the counter are cleared. Next, in #504, the state of the 3 bits (MSB>) of 5iD2 is determined, and if it is 1, it is determined that it is a data imprinting signal, and in #550, the imprinting lamp 14 is turned on, and the subroutine is executed.
call.

Here, this lamp lighting process will be explained with reference to FIGS. 16-13. #601. #602. In #603, it is determined whether the lamp is already lit (TRi boat-H), the data is being corrected using the correction switch, or the PA mode reference date is set (switch 24 is pressed), and if any of these conditions is present, the lamp is prohibited from lighting. and does not turn on the lamp.

Next, in #604, it is determined whether 5TATtJS has less than 10 seconds remaining on the interval timer. If it is less than 10 seconds, it is determined in #630 whether the data display mode is off mode, and if it is off mode, the next A subroutine PH0TOEND is called to perform preparation processing for starting interval time counting, and if the mode is not off, the process proceeds to the actual lamp lighting processing from #608 onwards.

Next, the aforementioned subroutine PH0TOEND will be explained with reference to FIGS. 16-14. At PH0TOEND,
First, in #661, clear the 1st digit of seconds and 10th digit of the interval timer counter to 0, and in #662, enter the interval time setting time stored at the start into the area where the actual countdown is performed from the 1st digit of minutes. Copying up to the 10th digit. Next, in #663, a subroutine EXTDSP is called which performs display processing other than normal data imprinting content display.

EXTDSPt' is T#350 in Figure 16-16.
In #351, 5TATUS is set to a display state other than normal mode. In #352, the display contents are changed, so the display request flag is set. In #353, a blank is output to each digit of the display area and the display is changed. Clear.

After the next GCEXTDSP processing, #665M TSTA
The IJS interval timer remaining 10 seconds or less state is reset, and the flag is set again in #666 to the interval timer countdown operating state. Next, #6
In 67, it is determined whether the data imprinting mode is the elapsed time display of the PA mode, and if it is the elapsed time mode, #
Proceeding to step 668, 5TATUS is set to interval timer mode, data imprint mode is set to PA mode, and a flag is set to display a down count while the timer is operating. On the other hand, if the data imprinting mode is not PΔ in #667, only a flag is set to indicate that the display content is the down count of the timer. This completes the PH0TOEND process and returns to the original process. Further, if the data imprinting mode is the off mode, the CPU 1 enters the 1-I ALT state returned from the LAMPON subroutine.

Next, if the interval timer is not within 10 seconds in #604 in the LAMPON subroutine,
#605. In #606, it is determined whether 5TATUS is in the process of counting the interval timer or setting the time of the interval timer, and if either state is in progress, cancel processing of the interval timer mode is performed in #6.
Do it after 20. This process will be described later. next#
If it is determined in steps 605 and #606 that neither of the above states exists, it is determined in #607 whether the data imprinting mode is off mode, and if it is off, the data imprinting lamp lighting process is not performed and HAL returns after returning.
Enter T state. On the other hand, if it is determined in #607 that the mode is not off, the process proceeds to #608, and the lower three of 5iD2
The time of the TRi timer is set according to the pit value, and the timer starts counting. Next, TR at #609
By setting the i-boat to H, the lamp 14 actually starts lighting from this time. In #610, 5TAT
Set IJS to TRi boat = H output state, #61
At #1, the REC mark 37 is lit, and at #612, the RFC boat-date output state is set, and the lamp lighting process is completed. Thereafter, it returns to 3iQiNT and enters the HALT state.

On the other hand, #605 first. If the interval timer is operating or setting the interval timer time in #606, 5TAT is determined in #620.
It is determined whether the US is an interval timer and the data imprinting mode is PA mode, and the means for canceling the interval timer is divided into two. First of all, set the data imprinting mode to PA mode using the interval timer.
In other words, if the MSB of 5TALJS4 is 1, #
Proceeding to 621, the M subroutine is called to RTC8N. In the RTCANCM subroutine, the interval timer operating state flag is reset in #391 in FIG. 16-15, and the interval timer time setting state flag is reset in #392. Next, in #393, the process returns with the interval timer remaining 10 seconds remaining status flag also reset.

Next, in #622, the display after canceling the interval timer is set to display the PA mode elapsed time, and in #623, since a change has occurred in the display contents, a flag for display request is set. After calling the aforementioned subroutine MDCLR to clear the display area in #623,
Return from the AMPON subroutine. On the other hand, #
#640 if the MSB of 5TATUS4 is 01 in 620, that is, the data imprinting mode is other than PA mode.
In this step, a subroutine RTCANCL is called which performs processing for canceling the interval timer mode. In the subroutine RTCANCL, #381 is shown in Figure 16-15.
At this point, the MSB of 5TATUS and 5TATUSO are reset to return to the normal data imprinting contents. Here, even if the interval timer mode or PΔ mode is entered and the MSB of 5TATUSO is set, the values of the lower 3 pits will not change, so if you cancel the interval mode or PA mode, you can always reset the lower 3 pits by resetting the MSB. By determining the value of the pit, it is possible to return to the state (display) of the data imprinting mode before entering the interval timer mode or the PA mode. Next, the RTCANCL subroutine is
After jumping to TCANCM and resetting each of the 5 TATLJS flags in the interval timer mode as described above, the program returns from the LAMPON subroutine and enters the HALT state.

Next, regarding the 5iOiNT interrupt processing, Section 16-1
In Figure 2, if it is determined in #504 that it is not a lamp lighting signal, in #505 the PIM mark port is set to rHJ or r depending on the state of the 2nd bit of 5iD2.
#506 to LJ. It is set in #507. Next #50
At step 8, the state of the first bit of 5iD2 is determined, and the processing is divided depending on the state of the main switch 53 of the camera body. When the main switch 53 is initially turned on,
#509. In #510, it is determined whether 5TATUS is in the operating state of the interval timer and in the state signal input wait state of the main switch 53 based on the serial code. If it is in the wait state, clear the first and tenth digits of the timer counter in #511 and return 5TATUS.
The wait state is reset in #512, the interval timer is set to the operating state in #513, and the next three
The timer is set to start counting down from the time of 2H7 interrupt processing. Next, in order to notify the camera body of the end of the wait state, in #514, the iNTSTP subroutine is called to set the iNT boat to L, and then the camera enters the HALT state.

i NTSTP subroutine #7 in Figures 16-18
In step 51, the iNT boat-L is output from the I10 boat 17, and in step #752, the iNT boat active flag is reset for 5TATUS.

Next, if the main switch 53 is determined to be off in #508, it is determined in #515 whether the interval timer is in an operating state, and if it is in an operating state, the above-mentioned LAMPON subroutine (16th-13th Figure) #6
20. #621. #622, #623. Similar to #624 or #620° #640, #516. #51
7. #518, #519. The interval timer cancellation process is performed in two steps depending on whether the data imprinting mode is the PA mode or not in the order of #520, #516, and #530. After the interval timer cancellation process, it enters the HALT state.

Next, timer interrupt processing (RT i NT) that occurs when the TRi timer counts up will be explained with reference to FIGS. 16-17.

When a timer interrupt occurs, the CPU 1 starts operating from #701. At #701, the TRiRi boat is set and the lamp lighting is ended. Then 5 TATU in #702
S is reset to the TRi boat=day output state, and in #703 it is determined whether there are 10 seconds or less remaining on the interval timer. If the remaining time is not 10 seconds or less, the RT i NT process ends and the HALT state is entered. On the other hand, if it is determined in #703 that the interval timer is in a state of 10 seconds or less, a subroutine PH0TOEND is called which performs preparation processing for counting the next interval time. P HOT
Regarding the OE N D subroutine, see 5iOi above.
This is as explained in the NT process. Next, #7
In step 05, clear the 1st digit of the second and 10th digit of the interval timer counter to 0, and in step #706, write the values from the 1st digit of the minute to the 10th digit of the hour to the RAM area where the interval timer setting time stored at the start is actually counted. Copying up to the digit. Next, in #707, subroutine E performs display processing other than normal data imprinting content display.
Calling XTDSP. The processing of EXTDSP is as described above.

The sequence then enters the HALT state.

Next, a method for monitoring the state of the main switch 53 of the camera when starting the interval timer will be outlined.

Since the camera release method using a timer during interval timer operation is configured to start a self-timer, the camera ill 111 circuit uses (1) a timer start signal, (
It is necessary to distinguish between 2) a timer release signal and (3) activation of a self-timer by a self-switch. FIG. 17 shows the circuit configuration of the connection between the iNT port terminal of the interval timer and the 5ELF terminal of the camera control circuit in this embodiment, and the left half inside the broken line shows the configuration inside the control circuit on the interval timer side. , the right half shows the control circuit configuration on the camera body side.

In the figure, 40 is an iNT output terminal of an interval timer control circuit 43 to be described later, 41 is an N-channel MOS transistor, which is the same as 18 shown in FIG. 3, 42 is an iNT signal output buffer, and 43 is an interval timer control built in the microcomputer. In the circuit, 50 is a camera self-timer switch, 55 is a 5ELF terminal of a camera control circuit, 56 is a self-signal input inverter, 57 is a resistor that pulls up the input of the inverter 56, and 58 is a camera body control circuit.

Next, the timing of each signal will be explained according to the timing chart in FIG. When inverter 50 is turned on, the input of inverter 56, which is normally pulled up by pull-up resistor 57, becomes L level. Here, the configuration of the camera control circuit 58 is such that the 5ELF terminal 55 is sampled at a constant period (T), and the self-timer is activated when the level is detected twice, for example. In addition, at that time, the 5ELF terminal 55
After the first sampling when detecting the L level of the main switch, a serial code containing the state signal of the main switch is sent out via the serial interface 19.

In other words, when starting the self-timer on the camera side, the self-timer switch 50 is pressed for a time longer than the sampling period T.

Next, when the interval timer starts, the interval timer 1bI is set as shown in the timing chart (a).
By turning on the IriA circuit 43 and the MOS transistor 41, the 5ELF terminal 55 becomes L, and then the camera side outputs a main switch status signal using a serial code by sampling the 5ELF terminal 55 for the first time.

The interval timer control circuit 43 receives this and at the same time sets the iNT boat to L. If this is before the next sampling of the 5ELF terminal, the self-timer of the camera body will not start. Since the interval timer control circuit 43 receives the status signal of the main switch 53 in the form of a serial code, it is possible to determine whether or not to start the interval timer by determining the code. Regarding the discrimination process, refer to 5iOiN in Box 16-12 above.
This is as explained in the section T.

Finally, when the interval timer counts up and starts the self-timer, as shown in timing chart (b), unlike the start case described above, the timer side does not set the iNT boat to H by inputting the serial code.
In this case, for a certain period of time (200 m5ec in the example) rL
By setting it to J level, the camera body becomes 5EL twice.
The self-timer is activated when the IJ level of the F terminal is detected. Here, 5ELFQf of the camera body control circuit 58
The i child sampling period FIJ(T) is this 2001SeC
Needless to say, it is much shorter.

In addition, in the above-mentioned embodiment, the main switch 5 of the camera body
3 is off, the interval timer mode is canceled, but a reset state may be entered in which the timer time is not set in the interval timer mode.

Further, the synchronization display may be performed when the main switch 53 of the camera body is turned off when the interval timer is started, or when the main switch 53 of the camera body is turned off while the timer is operating.

<Effects of the Invention> As explained above, the present invention allows the photographer to switch the second switch means (interval timer mode switch) for interval photography when the first switch means (main switch) of the camera is off. Since the timer is not decremented even when the camera is turned on, it can be immediately determined that the first switch means is in the off state, which has the effect of preventing failures due to camera operation errors.

Furthermore, if it is desired to cancel interval photography during the timer count operation during interval photography, this can be easily done by turning off the first switch means of the camera.

[Brief explanation of drawings]

FIG. 1 is a rear view of an embodiment of the camera according to the present invention, FIG. 2 is a sectional view of a main part of the date mechanism on the rear side, and FIG. 3 is a block diagram of an electronic circuit for controlling the operation of the camera. Fig. 4 is a layout diagram of the monitor LCD segment, Figs. 5 to 14 are explanatory diagrams of its display state, Fig. 15 is a schematic diagram of a flowchart for executing operation control, and Figs. 16-1 to 16-18. 17 is an electric circuit diagram of the interval timer and the connection section of the camera body, and FIG. 18 is a timing chart for the operation of the timer. 10...CD for motor 111...LCD for data imprinting, 20...data imprinting mode changeover switch, 21, 22.23... imprinting data and interval timer time correction switch, 24... Elapsed time imprint mode selection switch, 25...Interval timer mode switch (second switch means), 36...
- Shooting status display switch on the camera body, 37...imprint confirmation mark, 38...imprint data confirmation display section, 53...main switch on the camera body (first switch means) Fig. 1 et al. 3 53: Main switch Fig. 2 Calyx 4 Fig. 18 Fig. 10 Fig. 12 Fig. 13 Fig. 'r, Fig. 14 Fig. 15 Fig. 16-1 Fig. 16-8 Fig. #250 Fig. 16-9 ALT Fig. 16- Figure 10 RLTiMER ET Government 16-Old Figure RET RET Figure 16-14 ET Figure 16-15 REV Figure 17 Figure 16-17 RT iNT ALT Figure 16-18 iNr ACT iNT STP ET Figure 18 (a) When the timer starts (b) When the timer is released (C) When the camera self-timer starts Samurai Procedures Amendment July 73, 1988

Claims (1)

[Scope of Claims] 1. A first switch means that centrally controls each function of the camera, and an interval photographing means that performs a shutter release operation based on a shutter release signal output from an interval timer circuit at predetermined intervals. and a second switch means for starting the operation of the interval photographing means,
In a camera in which the liquid crystal display shows the time from when the second switch means is activated until the shutter release operation is performed, when the first switch means is off, the second switch A camera characterized in that the interval photographing means is not operated by the means. 2. When the first switch means is turned on and the second switch means is operated to turn off the first switch means while the interval timer circuit is operating, the interval photographing operation is stopped. A camera according to claim 1, characterized in that: