JPS63266697A - Contents access memory - Google Patents

Abstract

PURPOSE:To simplify a circuit by using a non-volatile memory element made capable of being erased, as the information storage part of a memory cell to constitute a contents access memory (CAM). CONSTITUTION:The CAM is constituted of plural memory cells CEL, which have the storage part using the non-volatile memory element, and relational logical part, and are matrix-arranged. The storage part of the memory cell CEL0 is provided with the non-volatile memory element Q1, e.g., a control gate and a floating gate, and a stack gate transistor which executes a selective storing operation by that its threshold voltage is changed according to the presence of the injection of an electric charge in the floating gate, is used. Thus, the number of the elements can be comparatively reduced, and the storage capacity of key information can be made larger.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a content-recall memory (associative memory), and is applicable to an associative memory constituted by an 1-chip semi-embedded integrated circuit device, for example. It is about effective techniques.

[Conventional technology]

For example, as a literature on associative memory, Journal of the Information Society of Japan, v.
o127, N16 June 1986, pp. 553-W60
0 There is "associative memory". Content-address memory is used as associative memory.
The content access memory (hereinafter referred to simply as CAM) can perform data searches at high speed.

The major difference between the above CAM and ordinary memory is that the stored data is not accessed by addressing,
This means accessing the stored data using its contents (key).

In other words, the CAM has a function of performing comparison logic with stored data when a key is input, and setting a flag (hit flag) on stored data that meets an association condition.

In the associative memory, the hit flag automatically selects, for example, a RAM in which data corresponding to the key is stored and outputs it.

As shown in FIG. 3, the memory cells constituting such a CAM include inverter circuits N3 and N40) a latch circuit whose input and output are cross-connected to each other, and a latch circuit for writing/reading stored information in this latch circuit. transmission gate MO
SFETQ24. Q25 and M forming the comparison logic circuit
OSFETQ20゜Q21 and Q22. It consists of Q23.

[Problem that the invention seeks to solve]

In this memory cell, the inverter circuit N3.
Each of N4 is composed of 2 (tIif) MOS FETs, and a total of 10 MOSFETs are required.For this reason, when configured into a semiconductor integrated circuit device, the degree of integration becomes relatively small. Therefore, when providing a search function for large amounts of data, it is necessary to use multiple semiconductor integrated circuit devices, which inevitably increases the size and cost of the system.Furthermore, if the power is cut off, Since the data stored in the memory cells disappears, it is necessary to store the data every time the power is turned on.

An object of the present invention is to provide a content recall memory with a simplified circuit.

Another object of the present invention is to provide a content recall memory in which registered data is made non-volatile.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an erasable non-volatile memory element is used as the information storage section of the memory cell forming the CAM.

[For production]

According to the above-mentioned means, since the storage section of the memory cell is constituted by non-volatile storage elements, it is possible to reduce the number of elements and make registered data non-volatile.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of an associative memory to which the present invention is applied.

Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known MO3 integrated circuit manufacturing technique.

The input (inquiry) register R1 contains n+1 bits (
Input data XO~ containing a key (inquiry content) consisting of any number of bits among them
Xn is cent.

The output signal of the input register R1 is supplied to the complementary data line of the CAM via the mask register R2, although this is not particularly limited. The mask register R2 has a function of substantially invalidating the cross-marked bits. For example, the output signal of the bit marked with an x is made low regardless of the high level/low level of the bit in the input register R1. This ensures that the comparison logic output with the stored information of the corresponding CAM memory cell CEL always matches.

The CAM is composed of a plurality of memory cells CEL arranged in a matrix, each having a memory section using a non-volatile memory element and a comparison logic section (determination circuit) to simplify the circuit. For example, a memory cell CEL having the same number of bits (n+1 bits) as the register R1 is placed on the side,
Memory cells CEL corresponding to the maximum number of stored keys are arranged in the vertical columns.

The specific circuit configuration of the memory cell CEL is comprised of the following circuit, as shown in FIG.

The storage section of the memory cell CELO, the specific circuit of which is exemplified as a representative, includes a nonvolatile storage element Q1, for example, a control gate and a floating gate, and its state is changed depending on whether or not charge is injected into the floating gate. A stacked gate transistor is used which performs an information storage operation by changing a threshold voltage. The source of this memory element Q1 is coupled to the ground potential of the circuit, and a switch MOSFET Q2 is provided between its drain and one data line Do. Further, in order to obtain a read signal according to the on-state H/off state of the memory element Q1, a high resistance R is provided between the drain of the memory element Q1 and the power supply voltage Vcc of the circuit. This high resistance R is not particularly limited, but in order to reduce the area occupied by the memory cell, the high resistance R is
MOS F E that constitutes TQ3 and inverter circuit N1
It is constructed integrally with the polysilicon layer that constitutes the gate electrode of T. Thereby, the resistor R can be formed without substantially increasing the area occupied by the memory cell.

The control gate of the storage element Q1 has a read/write function.
Connected to write word line SW. Also, switch M
OSFETQ2 is connected to write word line WW. The word lines SW and WW are extended in the horizontal direction in the figure, and are connected to other memory cells CELn shown in the same row.
are connected to the gates of the storage element Q7, etc., and the gates of the switch MOSFET Q8, etc., respectively.

The pair of complementary data lines 00. Do extends vertically in the figure and connects other memory cells (not shown) in the same column.
Commonly connected to.

The comparison logic section (judgment circuit) includes a MOSFET Q3 that receives the drain output of the storage element Q1, and a complementary data line DO.
A series circuit of MOSFETQ4 whose gate is coupled to
MOSFETQ whose gate is supplied with the output signal of the inverter circuit N1 which receives the drain output of the storage element Q1.
5 and a MOS whose gate is coupled to the complementary data line Do.
Consists of a series circuit of FETQ6. These pair of series MOSFETQ3. Q4 and Q5. Q6 constitutes a discharge path for the output vAS1 that extends in the horizontal direction in the figure. That is, the output line S1 is precharged by the MOSFET Q13 that receives the precharge signal PC, and is precharged by the series MOSFET Q3. Q4
Or Q5. Discharge is performed by Q6 when a signal that does not match the stored information is input. The signal on this output line S1 is determined by the sense amplifier SA.

Next, a write operation to the above memory cell will be explained. The write operation to the above memory cell is basically performed using the well-known E
This is similar to the write operation of FROM. That is, one of the complementary data vADO to Dn is provided with a write high voltage supply circuit composed of, for example, a switch circuit using a depression MOSFET and a high resistance. Alternatively, instead of this, a voltage conversion circuit constituted by a 0M03 circuit is provided. For example, when the depletion type switch MOS FET is used, a control signal is supplied to the gate thereof to set it to a low level (circuit ground) potential during a write operation. As a result, if the output signal corresponding to the complementary data line Do from the register R2 is high level, the depletion MOSF
ET becomes off-state B, and the complementary data line DO is set to a high level according to the write high voltage. Further, if the output signal corresponding to the complementary data line DO from the register R2 is at a low level, the depletion MO5FET maintains an on state, and the complementary data line DO is maintained at the ground potential of the circuit. Further, in the level conversion circuit, a high level such as 5V is converted to a high write voltage such as 12V, and a low level is directly used as the ground potential of the circuit.

Therefore, when performing a write operation to the memory cell CEL 0 shown in the figure, both word lines SW and WW are set to a high voltage corresponding to the above-mentioned high voltage. As a result, if the level of the complementary data line DO is a high level corresponding to the write/write voltage, a write current flows through the nonvolatile memory element Q1, and hot carriers generated at the drain portion are injected into the floating gate. In addition, the complementary data line DO
If the level of is the ground potential of the circuit such as low level, the hot carriers will not be generated, and no charge will be injected into the floating gate.

This also applies to other memory cells CELn and the like provided in the complementary data gland Dn and the like.

Furthermore, memory cells arranged in other rows are connected to the word line sw.
, ww (wl) to the word line W2 or the like.

During a read operation, in other words, during a search operation, all of the write word lines WW are maintained at a low level. As a result, the switch MOSFETs Q2, Q8, etc. of all memory cells are turned off, and with the key information input from register R2,
The read word lsw is set to a selected state.

That is, the selection level of word Isw is lower than the threshold voltage raised by charge injection into the floating gate, and higher than the threshold voltage lowered by no charge injection into the floating gate. set to the level.

As a result, focusing on the word vASW (Wl), the memory element Q1 to which writing has been performed at the selection level as described above is turned off, and the drain voltage thereof is set to a high level by the resistor R. Therefore, M.O.S.
FETQ3 is turned on and MOSFETQ5 is turned off. In this state, the complementary data line DO is at a high level (
When complementary data line Do is supplied with an input signal (low level), MOSFET 6 is turned on and MOSFET Q4 is turned off. In this way, the nonvolatile memory element Q1
When the information written to and the information input are the same, a discharge path for the output line S1 is not formed.Contrary to the above case, a low level is applied to the complementary data line DO (complementary data line DO).

When a mismatch input (high level) is supplied to the MOSF
ETQ3 becomes OFF state B, and MOSFETQ4 becomes ON state. Therefore, the output line S1 is discharged through MOSFETs Q3 and Q4.

It is assumed that the write operation as described above is not performed on the memory element Q7 of the other exemplary memory cells CF and Ln. In such a memory cell, when the word line 5W is set to the above selection level, the storage element Q7 is turned on and its drain voltage is set to a low level.

Therefore, MO3FBTQ9 turns off the MOSFE
TQI 1 turns on. In this state, when an input signal of low level (complementary data line Dn is low level) is supplied to complementary data [Dn], MOSFETIO turns on and MO3FT'? , TQ12 is turned off. Therefore, since the information held in the nonvolatile memory element Q7 and the manually input information are the same, a discharge path for the output line S1 is not formed. Contrary to the above case, when a mismatch input of high level (low level to complementary data line Dn) is supplied to complementary data line Dn, MOSFET QI
O is turned off and MOSFET QI 2 is turned on. Therefore, the discharge operation of the output line S1 is performed through MOSFETs QI2 and Qll. In this way, the logic “0” and logic “1” of the information stored in the memory cell
Depending on the result, the extraction route depending on the mismatch result will be different.

All memory cells CEL coupled to one output line S1
If the comparison logic matches in O to CELn, the output ISI becomes a high hint level. If even one of the comparison logics does not match, the output line Sl is pulled to a low level through that memory cell. In addition, in the mask bit, the human input signals of the complementary data lines are both set to low level. That is, the mask register R2 sets both its output complementary data vADO and Do to a low level (logic "0") in accordance with the mask signal input to the bit to be masked. This allows MOSFETQ4. Since Q6 and the like are always turned off, the matching state is maintained regardless of the stored information. In other words, the comparison logic for the above bits is masked.

In FIG. 2, signals such as each output 4% 31 to 83 of the CAM consisting of the memory cell matrix having the above configuration are not particularly limited, but the static type RAM (hereinafter simply referred to as R
The signal is transmitted to the word line drive circuit WDV (referred to as AM). The word line drive circuit WDV of the RAM is activated by a predetermined timing signal. In a RAM, when a word line is placed in a selected state, a plurality of memory cells coupled to the word line are selected. In the case of a read operation, the stored information of a plurality of memory cells coupled to one word line is output in parallel to the output register R3. Note that in the case of a write operation, data consisting of a plurality of bits supplied through the input register (not shown) (or the register R3 used for both write and read operations is preferable) is written. For example, data corresponding to a key is written into one word of the RAM as described above.

Further, the word lines W1 to W3 of the CAM are selected by the decoder circuit DCR during the write operation as described above. That is, the decoder circuit DCR decodes the address assigned to the vertical column of the CAM and selects one word line. As a result, the key information in the row corresponding to that word line becomes complementary data mDo.
to Dn. Further, if necessary, by sequentially setting the write words 11w to the selected state, it is possible to read the stored data from the complementary data vADO to Dn side.

Next, an example of the operation mode of the associative memory of this embodiment will be explained.

For example, when extracting key information in the initial state,
The word line Wl (S
W and WW), W2. Select W3... to read the key information stored in each memory cell of the CAM,
When the extraction of key information from the CAM is completed, the key information is sequentially input to the CAM through the register R1, and the word line of the RAM is selected from the hit output signal to select the word line corresponding to each key information. Write the data to RAM. Thereafter, each time the key information is input to the CAM through the register R1, the corresponding data can be read from the RAM.

As a result, data conversion from dog to DOG, or vice versa, can be performed at high speed, for example, in the case of an English-Japanese dictionary.

The effects obtained from the above examples are as follows. In other words, (by using non-volatile memory elements as the memory cells constituting 11CAM, the number of elements can be relatively reduced to 8 (note that the area occupied by the resistor R is virtually negligible, so it is not included in the number). This has the effect of increasing the storage capacity of key information.

(2) Since the above-mentioned non-volatile memory element is used, once the key information (base data) is written, there is no need to set the key information immediately after the power is turned on. ) can be avoided.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a decoder circuit D that forms a selection signal to sequentially select word lines of CAM
The CR may use a shift register.

In this case, key information can be read out sequentially by sequentially shifting, for example, a logic "1" signal instructing word line selection in accordance with a clock signal, without generating an address signal.

Furthermore, the memory element used in the CAM memory cell CEL is of the MNOS type (metal nitride oxide).
The key information may be erased electrically, such as a semiconductor (semiconductor) or a FLOTOX type transistor. When changing from the depressed mode to the enhancement mode by writing to the floating gate as in the MNOS transistor described above, the gate of the switch MOSFET Q2 and the control gate of the storage element can be connected to a common word line.

That is, after writing, by setting the word line to the ground potential of the circuit, the switch MOSFETQ2 etc. are turned off, and the storage element is turned on/on according to the stored information.
It can be turned off. In this case, since it is necessary to set the word line to a high level when reading stored information, a current sense amplifier that detects the magnitude of the current flowing through the storage element may be used.

In addition, the above precharge MO5F is connected to the output &jl S.
In addition to using ET, a resistive element may be connected as a load means to perform static operation.

Note that when an associative memory is not configured, in other words, in a system that uses a hit signal from an output line as an output signal, the RAM is omitted.

This invention can be widely used as a content callable memory (CAM).

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by using non-volatile memory elements as memory cells constituting the CAM, the number of elements can be relatively reduced to 8, making it possible to increase the storage capacity of key information (base data). After writing, it is possible to eliminate the trouble of setting key information immediately after power is turned on.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of cells constituting a CAM, FIG. 2 is a block diagram showing an embodiment of an associative memory using a CAM according to the present invention, and FIG. FIG. 2 is a circuit diagram showing an example of a CAM memory cell. R1...Input register, R2...Mask register, CA
M...Content recall memory, CELO. CELn...memory cell, DCR...decoder circuit, W
DV: Word line drive circuit, RAM: Static RAM, R3: Output register Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A nonvolatile memory element coupled to one data line of complementary data lines to which complementary input signals are supplied via a switch MOSFET, and to which written information is transmitted from the data line; load means connected in series to the nonvolatile memory element; an inverter circuit that receives storage information of the nonvolatile storage element; and an inverter circuit that receives storage information of the nonvolatile storage element and an inverted signal formed by the inverter circuit, respectively. Memory cells are arranged in a matrix, each of which includes a pair of switch MOSFETs and a determination circuit that is connected in series with the pair of switch MOSFETs, receives a signal from the complementary data line, and sends out a match/mismatch output to the output line. Features content recall memory. 2. The above nonvolatile memory element has a stacked gate structure, and performs a memory operation depending on whether or not charge is injected into the floating gate, and its control gate terminal is connected to a word line for writing/reading. 2. A content-readable memory according to claim 1, wherein the switch MOSFET is coupled to a write word line. 3. The content recall memory according to claim 1 or 2, wherein the determination circuit constitutes a discharge path for a precharged output line.