JPS63264000A - Two-channel stereophonically reproduced sound field adjusting device - Google Patents

Abstract

PURPOSE:To adjust the normal position of an image in a two-channel stereophonic sound field to a natural condition by making respective group delaying signals of a left channel signal and a right channel signal and a signal level variable by means of plural total area pass digital filters. CONSTITUTION:To an input terminal 1, the prescribed quantity of a group delay is given and the two-channel stereophonic acoustic signal of the digital signal of a prescribed signal level is supplied. A digital signal is demodulated with a receiving part RD. The demodulated signal is supplied to digital signal processors DSPl and DSPPr. The processors DSPl and DSPr execute the action to function as a total area pass digital filter to execute the total area pass digital filter operation to realize a group delaying characteristic and an amplitude characteristic set at a characteristic setting input part CID to respective left and right signals in a stereo signal. Thus, the normal position feeling of an image comes to be natural.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-channel stereophonic sound field adjustment device that can adjust the localization of a sound image within a two-channel stereophonic sound field to a natural state.

(Prior art) The level difference and time difference (phase difference) between the sounds given to both ears of a listener are greatly related to the listener's sense of left and right direction and the localization of the sound image in a 3D sound field. is well known, and has traditionally been used to change the stereoscopic effect felt by listeners and the sense of localization of sound images in a three-dimensional reproduction sound field created using an electroacoustic transducer. Efforts have been made to vary the amplitude and phase.

By the way, there are two playback sound sources placed in front of the listener (
Localization of the sound image in a two-channel stereoscopic reproduction sound field formed by the speakers) is possible only within the plane surrounded by the two speakers mentioned above, and the listener is aware that the sound image is located outside the two speakers. It is not possible to make the user feel a localized sound image.

Therefore, if the distance between two speakers arranged to form a two-channel stereoscopic reproduction sound field cannot be increased for some reason, for example, the condition of the listening room or the speakers are fixed to the reproduction device. For example, the range of sound image localization in a two-channel stereo reproduction sound field formed by two speakers becomes narrow.

Therefore, various types of three-dimensional sound field expansion devices have been proposed that can expand the range of sound image localization even in the above-mentioned cases, and devices that change the distance between the listener and the sound source have been proposed. Various proposals have been made regarding devices that can make the listener feel the same aural sensation that the listener feels when
(See Publication No. 2).

(Problems to be Solved by the Invention) However, in the conventional device as described above, a phase shifter configured by a combination of circuit elements such as a resistor, a capacitor, a coil, etc. Since the phase and frequency characteristics of an audio signal in the form of an analog signal were changed using a filter constructed by a combination of circuit elements, the disadvantage was that the configuration of the device was complicated and expensive, and as mentioned above. The emergence of a device that does not cause such problems has been long awaited.

(Means for Solving the Problems) The present invention provides instructions for the signal level and group delay amount of the left channel signal and the signal level and group delay amount of the right channel signal so that a desired two-channel stereoscopic reproduction sound field can be obtained. A characteristic setting input section to be input, and a group delay amount corresponding to the group delay amount of the left and right channel signals set by the above-mentioned characteristic setting input section are given to the left and right channel signals, and the left and right channel signals set by the above-mentioned characteristic setting input section are The present invention provides a two-channel stereoscopic reproduction sound field adjustment device comprising digital filter calculation means for applying signal levels corresponding to the signal levels of channel signals to left and right channel signals.

(Example) Hereinafter, specific contents of the two-channel stereoscopic reproduction sound field adjustment device of the present invention will be explained in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of an embodiment of the 2-channel 3D reproduction sound field adjusting device of the present invention, and Fig. 2 shows the signal level and group delay amount of the left channel signal to obtain the desired 2-channel 3D reproduction sound field. and a plan view of the characteristic setting input section for inputting the signal level and group delay amount of the right channel signal;
The figure is a block diagram showing the configuration of a digital signal processor (DSP).
FIG. 5 is a block diagram showing the configuration of a filter to be obtained by the operation of the processor (DSP).
6 is a flow chart for explaining the operation of the central processing unit (CPU); FIG. 7 is a diagram for explaining the characteristics of the all-pass digital filter; FIG. 8 is a Z plane diagram for explaining the poles and zeros (mirrors) of an all-pass type digital filter, FIG. 9 is an example of a memory map in the coefficient setting section and coefficient memory, and FIG. 10 is a characteristic setting input section. FIG. 2 is a block diagram showing an example configuration of a position information generating section in FIG.

In FIG. 1 showing a block diagram of an embodiment of the two-channel stereoscopic reproduction sound field adjusting device of the present invention, 1 is an input terminal for a digital signal, and this input terminal 1 has a two-channel stereoscopic reproduction sound field adjustment device. A predetermined amount of group delay is given in the adjustment device, and a two-channel stereophonic sound signal (hereinafter simply referred to as a digital signal) is supplied which is a digital signal of a predetermined signal format and is to be made to a predetermined signal level. .

The digital signal supplied to the input terminal 1 described above is demodulated by the receiving section RD. PLL is a phase-locked loop, and this phase-locked loop PLL synchronizes the phase of the clock in the digital data obtained by demodulating in the receiver RD and the clock generated in the receiver RD. used for Note that depending on the configuration of the device,
It goes without saying that the input signal may be a serial signal or a parallel signal.

The signal demodulated by the receiving section RD, for example, an NRZ signal, is sent to a digital signal processor DSPQ, DS.
Supplied to Pr. Digital signal processor D
As SPQ and DSPr, for example, those having the configuration shown in FIG. 3 can be used. Note that the digital signal processors DSPΩ and DSPr shown in FIG. 1 and the digital signal processors DSPQ and DSP specifically shown in FIG.
r refers to the corresponding input/output terminals in both so that the correspondence between the two becomes clear.

The same symbols a,'' and h are attached.

The digital signal processor DSPQ performs all-pass digital filter operation on the left channel signal of the stereo signal to achieve the group delay characteristics and amplitude characteristics set in the characteristic setting input section CID. Furthermore, the digital signal processor DSPr realizes the group delay characteristic and amplitude characteristic set in the characteristic setting input section CHD for the right channel signal of the stereo signal. It operates to function as an all-pass digital filter by performing all-pass digital filter calculations.

The above two digital signal processors DSP
Since the Q and DSPr have the same configuration and the same operation mode, in the following explanation, the above two
one digital signal processor DSPQ, DSP
When describing matters common to r, it is simply referred to as digital signal processor D without distinguishing between the two.
The explanation is given with the subscripts Q and r omitted, as in SP.

The characteristic setting input section CID for inputting the signal level and group delay amount of the left channel signal and the signal level and group delay amount of the right channel signal so as to obtain a desired two-channel stereoscopic reproduction sound field is shown in FIG. By moving the knob 8 as shown within the range of the dotted line frame Z in the figure, the predetermined signal level and group delay amount of the left channel signal and the right It is configured to output digital data indicating the signal level and group delay amount of the channel signal.

FIG. 10 is a block diagram showing an example of the configuration of the position information generating section in the characteristic setting input section CID described above, and in this FIG. 10, 8 corresponds to the knob 8 shown in FIG. 2 described above. This knob 8 is connected to a sphere 10 by a connecting rod 9. The spherical body 10 is rotatably supported at multiple locations around the spherical body by supporting portions (not shown).

Therefore, the above-mentioned sphere 10 is rotated while being supported by the support portion as the above-mentioned knob 8 is moved in the area Z indicated by the dotted line frame 2 in FIG. 11
, 14 are rollers that are pressed against the surface of the sphere 10, the roller 11 is fixed to the rotating shaft 12 of the variable resistor 13, and the roller 14 is fixed to the rotating shaft of the variable resistor 16. It is fixed to 15.

The rotating shaft 12 and the rotating shaft 15 are arranged to be perpendicular to each other within a plane including the center of the spherical body 10. Therefore, when the sphere 10 is rotated by the aforementioned knob 8, the rollers 11 and 14, which are in pressure contact with the surface of the sphere 10, rotate in accordance with the direction and amount of rotation of the sphere 10. The resistance values of variable resistors 13 and 16 are varied.

A constant voltage is supplied to both ends of the variable resistors 13 and 16, respectively, and the variable resistors 13 and 16 are connected to the rotating shaft 1.
The voltage corresponding to the position of the slider rotated by the rotation of 2.15 is applied to the analog-to-digital converters ADCx, ADCy.
supply to. Therefore, the information on the position of the knob 8 in the X-axis direction is sent as a digital signal to the output terminal 17 from the digital-analog converter ADCx, and the digital-analog converter ADCx
From Cy, information on the position of the knob 8 in the Y-axis direction is sent to the output terminal 18 as a digital signal.

R9L, RE shown outside the dotted line frame Z in Figure 2
Displays such as AR and FRONT correspond to the right, left, rear, front, etc. in the 2-channel playback sound field, and are used as the characteristic setting input section when adjusting the sound image localization in the 2-channel stereoscopic playback sound field. The operation of knob 8 in CHD is, for example, when trying to move the reproduced sound image to the right of the 2-channel reproduction sound field, move knob 8 so that knob 8 is positioned to the right, and For example, when attempting to move the reproduced sound image to the rear left of the two-channel reproduction sound field, the knob 8 is moved so that it is located at the rear left. .

Corresponding to the position of the knob 8 operated as described above, in order to give each listener in the two-channel stereoscopic reproduction sound field a sense of localization of the desired sound image,
The group delay amount and signal level required for the left and right channel signals are determined by the characteristic setting input section CID corresponding to the X and Y coordinates of each point in the area Z in FIG.
It is set as follows.

That is, the digital-to-analog converter A D
Information on the position of the knob 8 in the X-axis direction output from Cx to the output terminal 17, and Y of the knob 8 output from the digital-to-analog converter ADC:y to the output terminal 18.
Corresponding to the position information in the axial direction, the predetermined group delay amount and signal level are determined by the digital
The characteristic setting input section CHD uses, for example, the information on each position of the knob 8 as an address, and inputs the information for each position of the knob 8 so that it is applied to the left and right channel signals by digital filter calculation in the signal processor DSP. Information specifying predetermined group delay amounts of left and right channel signals and information specifying signal levels of left and right channel signals are read from the read-only memory and can be sent out.

In FIG. 1, DPA is a display section, and this display section DP
In A, a predetermined display is performed according to a signal supplied from the central processing unit CPU. For example, a subcode of information supplied from the receiving unit RD to the central processing unit CPU is displayed on the display unit DPA. It is to make it.

The central processing unit CPU is a read-only memory R
It is equipped with an OM and a random access memory RAM, and the knob 8 set in the characteristic setting input section CID described above.
Information specifying the group delay amounts of the left and right channel signals and information specifying the signal levels of the left and right channel signals, which are predetermined for each position, are supplied to the two-channel stereoscopic reproduction sound field adjustment device. A digital filter operation is performed in the digital signal processor DSP so as to generate the group delay amount and signal level for each left and right channel signal set in the characteristic setting input section CID in the input digital signal. It controls the operation of each part of the two-channel stereoscopic reproduction sound field adjustment apparatus, such as controlling the display unit DPA to display a predetermined display, and other operations.

Further, in FIG. 1, STD is a serial code transfer section, SCG is a clock signal generation circuit, MPX is a multiplexer, TD is a transmission section, and 2 is an output terminal.

In Figure 3, which shows a specific configuration example of a digital signal processor DSP, SDI is a serial data input circuit, IB is an input buffer, NC-RAM is a coefficient RAM, TB is a transfer buffer, and PCD is a parameter In the control section, P-RAM is a program RAM, SDO is a serial data output circuit, SCI is a serial code interface, and D-RAM is a data RAM.

Furthermore, FN-ROM is a constant memory ROM, MUL is a multiplier, ACC is an accumulator, REG is a register with thick, and OB is an output buffer.

Digital signal processor D shown in the third diagram above
The components of the SP, including constant memory ROM (FN-ROM), multiplier MUI, accumulator ACC, register with shifter REG, and output buffer OB, are well-known circuit configurations and are based on this book. Since it is not directly related to the description of the invention, a detailed description thereof will be omitted.

The program RAM (P-RAM) described above stores in advance a program to be executed by the digital signal processor DSP, and functions as a coefficient memory by storing data such as multiplication coefficients alo to bn2. NC-RAM), these data are supplied to the multiplier MUL.

The serial code interface SCI is equipped with a serial code input terminal C and a serial code output terminal d, and receives clock signals and synchronization signals (LRCK, LRC) supplied from the serial code timing input terminal e.
Data (SD, SD') is input from the serial code input terminal C and data (SD, SD') is output from the serial code output terminal d by means of the serial code input terminal C (K bar).

The parameter control unit PCD described above has a serial code.
Program RA with data from interface SCI
6g is a trigger input terminal of the parameter control unit PCD, which outputs control signals Ts and Tw specifying the transfer timing and the number of transfers from the transfer buffer TB while identifying and sending them to the M (P-RAM) and the transfer buffer TB. .

When a trigger (synchronization signal) input is supplied from the outside to the trigger input terminal g, the parameter control unit PCD can generate a control signal Ts whose transfer timing is determined by the trigger input. However, the parameter control unit PCD has a function that allows it to be triggered by data (SD, SD') even if no external trigger input is supplied to the terminal g. There is.

The two digital signal processors DSPQ and DSPr used in the two-channel stereoscopic reproduction sound field adjustment device shown in FIG. Since it is activated by being triggered, the above-mentioned terminal g
is not used.

The serial data input circuit SDI serially-parallel converts the audio input data from the serial data input terminal a, and sends it to the data RAM (D-RAM) via the input buffer IB.
). f in the figure is the input of the data clock signal BCLK and channel identification signal LRCK that are supplied to the serial data input circuit SDI and the serial data output circuit SDO in order to determine the timing of serial data input and serial data output. It is a terminal.

FIG. 4 shows a digital filter that can obtain the desired filter characteristics through the arithmetic operation of the digital signal processor DSP in the two-channel stereoscopic sound field adjustment device of the present invention shown in FIG. This fourth figure is a diagram expressed in the form of a specific circuit configuration.
In the figure, 3 is an input terminal, 4 is a unit delay operator, 5 is a multiplication circuit, 6 is an addition circuit, and 7 is an output terminal.The filter shown in FIG. The filter has an all-pass filter configuration in which n stages of sections FLTI to FLTn are connected in cascade.

As is well known, the transfer function HA (Z) of the all-pass digital filter as shown in FIG. 4 is expressed by the following equation.

In the case of an all-pass type digital filter, the coefficient ai2 of the coefficients of the digital filter can be set to 1, and in the all-pass type digital filter,
As shown in FIG. 8, PI, P on two plan views
2. P:1=Pn-1, each pole of Pn overlaps with the zero (mirror), and the phase characteristic θ(ω) changes to the frequency (standard) as shown in Figure 7(b). It is known that each pi-quad filter section (unit filter) monotonically decreases with respect to the frequency ω).

Furthermore, the group delay characteristic τg(ω) described above is τg(ω)=-
Since it is defined as dθ(ω)/dω, (
In a), group delay characteristics represented by Gdl and Gd2-Gdn are obtained for each of the piquad filter sections FLTI to FLTn. That is, the piquad filter section F
The angular frequency θP1 of the pole P1 of LTI is expressed as (
It can be made to correspond to the center frequency f1 of the first band frequency of the group delay characteristic shown in a), and similarly the angular frequency of each pole P2 to Pn of each piquad filter section FLT2 to FLTn. f? p2 to θpn can be made to correspond to center frequencies f2 to fn of the second to nth band frequencies.

Now, the central angular frequency θP1+ in multiple frequency bands
θp2...θpn are selected so that the difference between adjacent angular frequencies is equal, that is, the following formula 0 is satisfied, and each pole P
1. P2... Distance rl connecting Pn and the center
, r2...rn are all made equal as shown in the following formula % formula %, and each pole P1゜P2・
・・・・・・Plural all-pass digital filters are arranged so that the group delays of the plural all-pass digital filters are all the same while Pn are arranged on concentric circles.
When the digital filter coefficients in the filter are set, the group delay amount τg becomes constant as shown by τgt in Figure 7, and the overall group delay characteristic of the N all-pass digital filters is approximately This results in a flat state and a group delay characteristic with no irregularities in the entire frequency band.

Regarding the all-pass digital filter configured as shown in Fig. 4, the filters of each piquad filter section FLTI to FLTn are capable of obtaining a group delay characteristic with no irregularities in the entire frequency band as described above. An example of the coefficients when n=10 is as follows.

FLT filter coefficient 1, a 10 =0.2279777008a
11=-0,9435036489a 12=1.
0000000000b 11 = 0.943503
6489b 12=-0,22797770082,
a20=0.2279540615a21=-0
,8539270229a 22=1.0000000
000 b 21=0.8539270229 b 22=-0,22795406153, a 30=
0.2286841630a31=-0,685520
7745 a 32=1.0OOOOOOOOOO b31=0.6855207745 b32=-0,2286841630 4, a40=0.2309500374a41=-0
,4528444485 a42=1.0000000000 b41=0.4528444485 b 42= -0,23095003745, a 50
=0.2332873199a 51= -0,172
3049176a 52=1.0000000000 b 51=0.1723049176 b52=-0,2332873199 6, a 60 = 0.2355608216a 61
= 0.1265036337a 62 = 1,
ooooooooooo.

b 61 = -0,1265036337b 62=
-0,23556082167, a 70=0.239
9302297a 71 = 0.418044534
6a 72 = 1.0000000000b 71
= −0,4180445346b 72= −0,2
39930229710, a 10,0 =0.256
6032823a 10,1=0.999134274
0a 10,2=1.0000000000b 10,
1=-0,9991342740b 10,2=-
0,2566032823 Note that the desired signal level can be obtained by finding the amplification factor and attenuation factor of the signal level from the characteristic setting input section CID and multiplying it by the filter coefficients a10,0 and alO,1 described above.

Next, switching of group delay characteristics and changing of signal level will be explained with reference to FIG. Switching the group delay characteristics and changing the signal level means switching the program of the filter that essentially constitutes the digital signal processor DSP, or changing the program of the filter that essentially constitutes the digital signal processor DSP.
Coefficient alO~bn of the filter that substantially constitutes SP
This can be done by switching the coefficient data corresponding to 2, and the control of the switching operation of the group delay characteristic is performed by the central processing unit CPU.

In the following description, switching the group delay characteristic and changing the signal level are the coefficients al of the filter that substantially constitutes the digital signal processor DSP.

The explanation is given by taking as an example the case where the switching is performed by switching the coefficient data corresponding to bn2.

Now, the central processing unit CPU mentioned above has a read-only memory ROM and a random access memory R.
It is configured to operate according to the flowchart shown in FIG. 6 based on the control signal from AM.

In the flowchart of Figure 6, when starting,
The axis settings are read (step 100), and then the Y-axis settings are read (step 101). Next, it is determined whether or not a change has been made (step 102), and if YES, the characteristic coefficient is selected (step 103), written in the coefficient setting section (step 104), and a switching pulse is generated (
After step 105), return to step 100 and NO
If so, the process returns to step 100 after waiting (step 106).

In this way, the coefficients of the digital filter are rewritten for each unit filter provided for each frequency band. By increasing the number n of unit filters by setting the characteristics in the characteristic setting input section (ID), the group delay amount can be increased. The amount of group delay can be reduced by decreasing the number n of unit filters.Also, in order to decrease the number n of unit filters using the same program, the unit filter FLTi with more than n stages must be It is sufficient to make the group delay amounts at the input and output equal, and the digital filter coefficients of the unit filter F LT i are as follows: aio=1.ail=o, aj2=o, bil=0゜b
When i2=o, the unit filter has filter characteristics such that the group delay amount at the input and output is equal.

The central processing unit CPU mentioned above is, for example, R8232C.
The serial format of the digital signal processor DSP is transmitted via the serial transfer unit STD shown in
When digital filter coefficient data is sent from the serial code input terminal C of the
CI) and the parameter control unit PCD to the transfer buffer TB.

FIG. 9(a) shows an example of a map of the transfer buffer TB, and in FIG. 9(a), addresses O to 3
The digital filter coefficient data alO is stored in the memory part of , and the digital filter coefficient data a11 is stored in the memory part of addresses 4 to 7, and so on. Digital·
The coefficient data of the filter is stored sequentially and is stored at address (4
The storage area specified by
2 is stored.

FIG. 9(b) is an example of a map of the coefficient RAM (NC-RAM). ] 0 is stored, and the digital filter coefficient data all is stored in the memory portions of addresses 2 and 3, and so on, the digital filter coefficient data is sequentially stored in the memory portions specified by the sequential addresses. It is stored at address (2X(5'n -1)) ~ (2X(5n
-1) + An example is shown in which coefficient data bn2 of a digital filter is stored in the storage portion designated by 11.

The map of the transfer buffer TB illustrated in FIG. 9(a) and the coefficient RAM (NC
-RAM) map, the address of the storage part where the coefficient data of the same digital filter should be stored is different when the coefficient data of each digital filter is 32 bits (8 bits x 4). In addition, the transfer buffer TB has 8 bits per address and a coefficient RAM (NC-R
This is because AM) is illustrated based on an example in which a storage capacity of 16 bits per address is used.

The address described above is specified in the third serial data of the 4-byte instruction set as shown in (i) of FIG. 5, and the coefficient data of the digital filter described above is specified as (i) of FIG. It is specified by the fourth serial data of the 4-byte instruction set as shown in .

If the word length of the coefficient data of the digital filter is 32 bits as in the example described above, the coefficient data of the digital filter is sent in four parts of 8 bits each. Note that the first code 1 and the second code 2 of the serial data of the 4-byte instruction set shown in (i) of FIG. 5 are for chip enable, which It is used to distinguish whether to select a digital signal processor DSP, etc.

The CRS bar in (h) of FIG. 5 is a start signal that informs the start of serial code transfer, and the start signal CRS bar for starting the serial code transfer is sent from the serial code transfer section STD to the input terminal of the serial code interface SCI. is applied to the

Two digital signal processors DSP shown in the two-channel stereoscopic reproduction sound field adjustment device shown in the first diagram.
That is, all-pass type digital filter calculation is performed to give the group delay amount and signal level set in the characteristic setting input section CID to the left channel signal of the stereo signal, thereby functioning as an all-pass type digital filter. A digital signal processor DSPQ operates to perform the following operations, and an all-pass digital filter operation that applies the group delay amount and signal level set to the characteristic setting input section CID to the right channel signal of the stereo signal. The digital signal processor DSPr, which performs an operation to function as an all-pass digital filter, operates in the manner described above.

A digital signal processor D S is connected to the serial code interface output terminal d of the digital signal processor DSPQ shown in the two-channel stereoscopic reproduction sound field adjustment device shown in the first figure.
Serial code interface SC in P r
Since the input terminal C of I is connected, the coefficient data of the digital filter sent to each transfer buffer TB in the digital signal processors DSPΩ and DSPr is the same as that of the digital filter that has already been sent. Together with the coefficient data, 5 words for each unit filter are sent to the coefficient RAM (NG-RAM) triggered by external synchronization signal 7.

n- Note that the digital signal processor DSP described above
The clock signal that determines the program command cycle of Q, DSPr is a clock signal fg with a frequency 128 times the frequency of the sampling pulse generated in the receiving section RD.
((g) in FIG. 5) is used, and its clock signal fg
is supplied to the clock input terminal f.

SCG in FIG. 1 is a clock signal generation circuit that generates a clock signal with a frequency corresponding to the transfer rate of the serial transfer unit STD, and the clock signal generation circuit SCG shown in FIG.
The clock signal generated by CG is a digital signal.
It is supplied to the serial code timing signal input terminal e of the serial code interface SC of the processor DSP.

Now, the two-channel stereoscopic reproduction sound field adjustment device shown in Figure 1 (
In FIG. 5, which shows the timing chart of the system), the digital signal processor DSPQ operates at time t1.
At the same time as importing the coefficient data of the digital filter,
The calculation result of the coefficient data of the previous digital filter is output, and the multiplexer MPX in Figure 1 outputs the time-division signal of the two left and right channels (indicated by (,) in Figure 5) together with the output from the digital signal processor DSPr. format)
After that, the signal is converted into a digital audio interface format in the transmitting section TD, which has an audio data modulation function and a transmitting function, and then sent to the output terminal 2.

Note that the digital data transmitted from input terminal 1 in the digital audio interface format is demodulated into NRZ at the receiving section RD and becomes serial digital audio data ((a) in Figure 5). and two digital signal processors DSPfi
, DSPr, and the channel identification signal LRCK is applied to each input terminal a of the DSPr.
, word identification signal WCK, etc., and transmits them to two digital signal processors DS.
PΩ is supplied to the DSPr and the transmitter TD so that each of the above-mentioned components can operate in synchronization with each other.

The multiplexer MPX described above is equipped with a changeover switch for the left channel signal and a changeover switch for the right channel signal, and these two changeover switches are sequentially and alternately turned on and off in response to the channel identification signal LRCK, thereby switching the left channel signal to the left channel signal. The signal and the right channel signal are sequentially and alternately supplied to the transmitter TD on the time axis.

In the description of the embodiments so far, it has been explained that a structure in which n piquad filter sections having the same structure are connected in cascade as shown in FIG. 4 is used as an all-pass type digital filter. In implementing the above, an all-pass type digital filter may be used that has a configuration in which n pi-quad filter sections with the same configuration are connected in parallel, and as described above, n pi-quad filter sections with the same configuration When using a configuration in which filter sections are connected in parallel,
An all-pass type digital filter can be realized by scaling the digital filter coefficient data while being careful about overflow.

In addition, in the description of the embodiments so far, an all-pass type digital filter configured with a second-order IIR as a unit filter has been described as an example, but the explanation is not limited to this. Alternatively, the configuration of the all-pass digital filter may be changed depending on the bandwidth and frequency, such as a mixed configuration in which a first-order IIR and a second-order IIR are used as a unit filter. Needless to say, it can be modified and used.

Furthermore, in the description of the embodiments so far, it has been assumed that a digital filter is used that gives a constant amount of group delay to the signal over the entire frequency band to be reproduced. The present invention may be implemented using a digital filter in which the amount of group delay within the targeted frequency band is not constant;
As a digital filter, some or all of it
If a device that has frequency characteristics in terms of both phase and amplitude is used, more favorable results may be obtained due to the localization and stereoscopic effect of the stereoscopic reproduction sound field.

It should be noted that the digital signal processor DSP to be used is not limited to the configuration described above, and in short, the digital signal processor DSP is an embodiment of programmable digital signal calculation means. It's not too much. Further, in the embodiments so far, a digital signal input and digital signal output system has been described, but the implementation of the present invention is not limited to such a system type. For example, an AD converter, an AD converter, Of course, the present invention can also be applied to a system that uses a DA converter on the output side to provide analog signal input and analog signal output.

(Effects of the Invention) As is clear from the above detailed explanation, the two-channel stereoscopic reproduction sound field adjustment device of the present invention adjusts the signal level of the left channel signal such that a desired two-channel stereoscopic reproduction sound field can be obtained. A characteristic setting input section for inputting the group delay amount and the signal level and group delay amount of the right channel signal; A two-channel stereoscopic reproduction comprising digital filter calculation means for applying to the left and right channel signals a signal level corresponding to the signal level of the left and right channel signals set by the above-mentioned characteristic setting input section. In the 2-channel 3D reproduction sound field adjustment device of the present invention, the 2-channel 3D reproduction sound field is set in the characteristic setting input section so as to provide a 2-channel 3D reproduction sound field in which a desired sound image localization can be obtained. The group delay amount and signal level of the left channel signal in the stereophonic sound signal and the group delay amount and signal level of the right channel signal are in a state where the overall group delay characteristic of the plurality of all-pass digital filters is approximately flat. The digital filter coefficients are set such that the same group delay characteristics are obtained for all frequency bands.The digital filter coefficients are made variable by a plurality of all-pass digital filters, so that the The sense of direction of the sound field in the channel reproduction sound field, especially the movement of the sound image in the depth direction, can be reproduced satisfactorily, and therefore the localization of the sound image becomes natural. According to this, all of the conventional problems mentioned above can be satisfactorily solved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the two-channel stereoscopic reproduction sound field adjustment device of the present invention, Fig. 2 is a front view of the characteristic setting input section, and Fig. 3 is a block diagram showing an example configuration of the digital signal processor. 4 is a block diagram showing the configuration of a filter to be obtained by the operation of the digital signal processor, FIG. 5 is a timing chart for explaining the operation of the two-channel stereoscopic reproduction sound field adjustment device of the present invention, and FIG. The figure is a flowchart to explain the operation of the central processing unit (CPU), Figure 7 is a diagram to explain the characteristics of the all-pass type digital filter, and Figure 8 is the pole and zero (mirror) of the all-pass type digital filter. FIG. 9 is a diagram showing an example of a memory map in a coefficient setting section and a coefficient memory, and FIG. 10 is a block diagram showing an example configuration of a position information generating section in a characteristic setting input section. 1... Digital signal input terminal, 2, 7... Output terminal, 3... Input terminal, 4... Unit delay operator, 5...
...Multiplication circuit, 6...Addition circuit, 8...Knob, 9.
... Connecting rod, 10... Sphere, 11, 14... Roller, 12, 15... Rotating shaft, 13.16-... Variable resistor, ADCx, ADCy... Analog-to-digital converter, RD...Reception section, PLL...Phase locked loop, DSPQ, DSPr...Digital signal processor, CHD...Characteristics setting input section, D
PA...Display unit, CPU...Central processing unit, R
OM...Read-only memory, RAM...Random access memory, STD...Serial code transfer section, SCG...Clock signal generation circuit, M
PX...multiplexer, TD...transmitter, SDI
... Serial data input circuit, IB... Input buffer, NC-RAM... Coefficient RAM, TB... Transfer buffer, PCD... Par 3 roller meter control unit, P-RAM... program RAM,
SDO... Serial data output circuit, SCI...
Serial code interface, D-RAM...
Data RAM, FN-ROM... RO for constant memory
M, MUL... Multiplier, ACC... Accumulator, REG... Register with shifter, OB... Output buffer, BCLK... Data clock signal, LRCK...
・Channel identification signal, FLTI~FLTn・
... n piquad filter sections with the same configuration, Procedural Amendment (Part 1, September 22, 1986, Commissioner of the Patent Office, Kuro 1) Akio Tono 2, Name of the invention 2-channel stereoscopic reproduction sound field adjustment device 3, Relationship with the case of the person making the amendment Patent Applicant Address 3-12 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name (432) Victor Company of Japan Co., Ltd. 4, Agent

Claims (1)

[Claims] a characteristic setting input section for inputting instructions for the signal level and group delay amount of the left channel signal and the signal level and group delay amount of the right channel signal so as to obtain a desired two-channel stereoscopic reproduction sound field; and the characteristic setting input section described above. At the same time, the group delay amount corresponding to the group delay amount of the left and right channel signals set by the above-mentioned characteristic setting input section is given to the left and right channel signals. A two-channel stereoscopic reproduction sound field adjustment device comprising a digital filter calculating means for applying to a signal.