JPS63263919A - Pll circuit - Google Patents

Abstract

PURPOSE:To detect locking/unlocking with high accuracy independently of the high or low reference frequency by detecting the lock/unlock of a PLL with a phase allowance varied inversely proportional to the set reference fre quency. CONSTITUTION:An oscillated signal from a voltage controlled oscillator VCO is frequency-divided to 1/MN by program counters PC2, PC1 via an input buffer IB and fed to one input terminal of a phase comparator PFC. A signal (fr) being the frequency-division of a system clock signal SCK by a reference fre quency generating circuit RFG is fed to other input terminal of the circuit PFC. The circuit RFG generates a pulse signal (fw) discriminating lock/unlock of the PLL whose permissible phase difference is varied in response to the signal (fr) so as to inversely proportional to the high or low reference frequency signal to be set and gives it to a lock detection LKD.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a PLL (phase e-locked loop) circuit, and for example, a PLL circuit that constitutes a digital tuning system for a radio receiver using a microcomputer. It relates to techniques that are effective for use in circuits.

[Conventional technology]

As an example of a digital tuning system for radio receivers, there is a product catalog [μPD1708J] published by 1 Nippon Electric Products on May 31, 1983. In the above-mentioned digital tuning system "μPD1708J, since the frequency space between broadcasting stations is different in each image format, the reference frequency signal supplied to the phase comparison circuit of the PLL circuit is IKHz, 5KHz,
6.25KHz, 9KHz.

It is possible to select any one frequency from 10 KHz and 12.5 KHz. For example, when the space between broadcasting stations is narrow, a low reference frequency signal such as the above-mentioned IKHz is used to reduce the tuning step for the unit of digit/l/tuning information.

[Problem that the invention seeks to solve]

In the above digital tuning system,
Even though the reference frequency signal is made changeable as described above, the phase difference for detecting lock/unlock of the PLL, i.e., the reference frequency signal supplied to the phase comparison circuit and the program counter circuit, is The allowable phase difference with the oscillation frequency of the voltage controlled oscillation circuit supplied by the oscillator is fixed.

In the above configuration, the PLL lock/unlock is accurate (cannot be detected) through research by the inventor of the present invention. In other words, when the reference frequency is lowered, Since the number of phase comparisons in the phase comparator circuit decreases, the frequency control sensitivity in the PLL circuit deteriorates.On the other hand, when the reference frequency is increased, the number of phase comparisons per unit time in the phase comparator circuit increases. , frequency control sensitivity in the PLL circuit increases.

Therefore, if the allowable phase difference that should be considered as a locked state is fixed regardless of the height of the reference frequency, the following major problem will occur. In other words, in the above-mentioned digital tuning system, the allowable phase difference is set so that PLL lock detection is possible even at the lowest reference frequency, so when the reference frequency is raised, Even if the phase difference should be considered as an unlocked state, it will be incorrectly determined as a locked state.

An object of the present invention is to provide a PLL circuit in which the allowable phase difference that defines the range of the locked state can be changed.

Another object of the present invention is to provide a PLL circuit having a frequency switching function of a reference frequency signal and a highly accurate PLL lock/unlock detection function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when changing the reference frequency signal supplied to the phase comparator circuit, pulses are formed to have positive and negative phase differences that are changed inversely to the reference frequency accordingly, and the PLL Detects lock/unlock.

[Effect]

According to the above-mentioned means, since the allowable phase difference that should be considered as a locked state can be set to an optimal value according to the reference frequency, locking/unlocking of the PLL can be detected with high accuracy.

Further, by making it possible to change the allowable phase difference while the reference frequency is constant, it becomes possible to freely set the accuracy at the time of locking under the constant reference frequency. That is, the narrower the allowable phase difference, the closer the frequency at locking becomes to the reference frequency. Conversely, the wider the allowable phase difference, the further the locking frequency will be from the reference frequency, and the accuracy will decrease.
This can speed up the time it takes to lock.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a semiconductor integrated circuit device constituting a digital tuning system including a PLL circuit to which the present invention is applied. In the figure, the semiconductor integrated circuit device LSI indicated by the dashed line
is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In the figure, a loop filter, a voltage-controlled oscillation circuit, and a chaining circuit using the oscillation frequency of the voltage-controlled oscillation circuit, which constitute the PLL circuit, are omitted in the figure, and are external to the semiconductor integrated circuit device LSI. Constructed as a circuit.

The oscillation signal of the voltage controlled oscillation circuit (not shown) is connected to terminal ■C.
0 to the input terminal of the input buffer IB.

The output signal of the input buffer IB is not particularly limited, but
The signal is supplied to a second program counter (branch circuit) PO2 that constitutes a prescaler. The oscillation frequency of the voltage controlled oscillation circuit is determined by the second program counter circuit P.
The frequency is divided into 17M by C2. The output signal of the program counter circuit PC2 is supplied to a first program counter (branch circuit) PCI. The program counter circuit PCI further divides the frequency of the 1/M branched output into 1/N. In this way, the signal fo to be frequency-controlled divided into 1/NXM by the program counter circuits PC2 and PCI is transmitted to the phase comparator circuit PF.
is supplied to one input terminal of C.

A reference frequency signal fr, which will be described next, is supplied to the other input terminal of the phase comparator circuit PFC.

In this embodiment, the reference frequency signal fr is
In order to make it possible to set the frequency of the reference frequency generating circuit RFG, the reference frequency generating circuit RFG is provided with a variable frequency division function that receives the system clock signal SCK of the microcomputer as described later, although this is not particularly limited. Further, the reference frequency generation circuit RFC generates a pulse signal for identifying lock/unlock of the PLL whose allowable phase difference is made variable according to the set reference frequency signal or under a constant reference frequency signal. It has the function of forming fw. The reference frequency fr and the pulse signal fw are set by storage information set in the control register PCR2 or PCR3.

The phase comparison output of the phase comparison circuit PFC is connected to the external terminal L.
The signal is supplied to a loop filter (not shown) via a PF.

The loop filter forms a control voltage according to the output signal of the phase comparison circuit PFC to control the oscillation frequency of the voltage controlled oscillation circuit.

The first and second program counter circuits PC1 and PO2 have their respective frequency division ratios of 1/N and 1/M set according to digital signals set in the program data (channel selection) registers PDRI to PDR4, respectively. be done. Although not particularly limited, each signal of each of the registers PDRI to PDR4 is transmitted to each of the program counter circuits PCI and PO2 via gate circuits G1 to G5.
is supplied as an initial value (count value). These gate circuits G1 to G5 have their control terminals supplied with a preset signal supplied via an OR gate circuit GO.The input of the OR gate circuit GO is supplied with a start signal sent from a control register PCRI. The signal S or the overflow (count end) signal supplied from the output of the program counter circuit PCI is supplied.Therefore,
When the start signal S is formed and the PLL
When the circuit is in operation, the program counter circuit PC
Each time an overflow signal of I is generated, each of the gate circuits G1 to G5 opens its gate and the initial value is set. As a result, the program counter circuit PC
I and PO2 are each of the above registers PDRI to PDR.
Channel division ratio (i/MxN) according to channel selection information set to 4
be made to have. Therefore, when the PLL is in a locked state, the oscillation frequency of the voltage-controlled oscillation circuit is set to the frequency signal f o (=f r ) x N x M described above.

The registers PDRI to PDR4 and the control registers PCRI, PCR2, and PCR3 receive digital signals for channel selection and digital signals corresponding to the state of the received image from the microcomputer MCU via the data bus BUS. Supplied. The microcomputer MCU forms control signals for various channel selection operations such as memory channel selection and manual channel selection through simple operations, according to the program.

The lock detection circuit LKD is the reference frequency generation circuit RF.
In response to the pulse signal fw formed by G and the frequency signal fo to be controlled from the one-phase comparator circuit PFC, which is not particularly limited, a PLL lock/unlock detection signal is formed and is sent to the control register PCRI. supply The microcomputer MCU controls the control register PCR
Read the lock/unlock information conveyed to I,
The automatic channel selection operation and display signal are formed.

The reference frequency generation circuit RFG is connected to the control register PCR.
The frequency division ratio is set according to the information set by 2.

For example, a digital signal no to D consisting of 3 bits
If 2 is 000, it is I KHz.

001 is 5KHz, 010 is 6.25Hz, 011
Then 9KHz, 100 means 10KHz, :101 means 2
Reference frequency signal fr for each frequency of 7 types in total of 5KHz
form. As a result, in countries where frequency intervals between broadcasting stations are narrow, such as the United States, the standard frequency is set to a low frequency such as IKHz, so that it is possible to receive each broadcasting station that exists in the narrow interval. A signal fr is formed.

As a result, the program counter circuits PCI and P
The minimum unit reception frequency step by O2 is the above IKH
It can be set at narrow intervals like z. Furthermore, in countries such as Japan where the frequency range between broadcasting stations is wide, a high frequency such as 25 KHz is set. As a result, the minimum unit reception frequency step by the program counter circuits PCI and PO2 can be set at wide intervals such as the 25 KHz. In this embodiment, the combination in which the 3-bit digital signals no to D2 are 111 is not used.

FIG. 2 shows a waveform diagram for explaining an example of the operation of the reference frequency generating circuit RFG.

For example, the reference frequency generation circuit RFG has a control register P
According to the information in CR2, the system clock signal SCK set to a high frequency is divided to form a reference frequency signal frl set to a predetermined frequency. In this way, when the frequency of the reference frequency signal fr1 is made relatively high, the PLL
Pulse signal fw to detect lock/unlock of
l is a pulse signal that falls from a high level to a low level one cycle before the system clock signal SCK, for example, and rises from a low level to a high level one cycle later, centered on the rising edge of the reference frequency signal frl. That is, in this case, the allowable phase difference +△ and -△
is made relatively narrow by a total of two cycles of the system clock signal SCK. The lock detection circuit LKD is constituted by a flip-flop circuit that takes in the pulse signal fwl at the rising edge of the frequency signal fo to be controlled, although it is not particularly limited thereto.

For example, if the signal taken into the flip-flop circuit is low level, in other words, if the rising edge of the frequency signal fO is within the allowable phase range △,
Forms a lock detection signal.

On the other hand, if the signal taken into the flip-flop circuit is at a high level, in other words, the frequency signal f
If the rising edge of o is outside the allowable phase range Δ, an unlock detection signal is generated.

In addition, the reference frequency generation circuit RFG is connected to the control register PCR.
In order to detect lock/unlock of the PLL when the system clock signal SCK is divided according to the information of 2 and the frequency is made relatively lower than the reference frequency signal frl, such as the reference frequency signal fr2. The pulse signal fwl is centered around the rising edge of the reference frequency signal fr2, for example, the system clock No. 28 SC.
It is a pulse signal that falls from a high level to a low level two periods before K, and rises from a low level to a high level two periods later. In other words, the allowable phase difference in this case +
△ and 1△ are the total of 4 of the above system clock signals SCK.
It is made relatively wide by the period. The lock detection circuit LKD is
If the signal taken into the flip-flop circuit is at a low level, in other words, if the rising edge of the frequency signal fo is within the allowable phase range Δ, a lock detection signal is generated. On the other hand, if the signal taken into the flip-flop circuit is high level, in other words,
If the rising edge of the frequency signal fO is outside the allowable phase range Δ, an unlock detection signal is generated.

In this way, the pulse signals fwl and fw2 are set so that the pulse width, in other words, the phase tolerance value Δ, is variable in accordance with the frequencies of the reference frequencies frl and fr2 set above.

Pulse signal fw whose phase tolerance value △ is made variable in this way
can be easily formed by differentiating the combinations of the branch outputs of each stage of the system clock signal SCK. For example, the pulse width of the pulse signal fw can be changed to fwl or fw2 by counting the system clock signal SCK and changing the count values before and after the counted output of the system clock signal at the rising edge of the reference frequency signal fr. can be easily changed to

As an example of setting the allowable phase difference △ for each of the above reference frequencies IKHz to 25KHz, for lKH2, 10μ
s, at 5KHz5. czs, 1.6 when 6.25KHz. us, 1.1 ps at 9KHz, 10K
When Hz 1. us, 0.8μs at 12.5KHz
etc. is set. Another example is 10 at IKHz.
When ps is 5KHz to 12.5KHz, it is all set to 2 μs.

As described above, in this embodiment, the allowable phase difference Δ is variably set in inverse proportion to the frequency at which the reference frequency fr is set.

When the frequency of the reference frequency fr is as low as I KHz, the phase comparator circuit PFC has the following values per unit time:
1000 phase comparison operations are performed.

On the other hand, when the reference frequency is increased to 10 times higher than 10 KHz, the phase comparison circuit PFC performs 10,000 comparison operations per unit time.

Because of this difference in phase comparison operation, the inherent frequency control sensitivity in the PLL circuit becomes thicker, and when the frequency of the reference frequency signal is low, the frequency fluctuation width of the frequency signal fO to be controlled is relatively wide. In this embodiment, when the frequency of such a reference frequency is low, the phase tolerance range Δ is widened to detect lock/unlock. When the frequency is high, the frequency fluctuation range of the controlled frequency signal fo is relatively narrow. Correspondingly, when the frequency of the reference frequency is high, the phase tolerance range △ is narrowed and its lock/unlock is detected. It is something to do.

This allows lock/unlock detection to be performed with high accuracy.

FIG. 3 shows an embodiment of the reference frequency generation circuit RFG and lock detection circuit LKD shown in FIG. 1.

Frequency dividing circuits DIVI, DIV2, ""DIVn divide the system clock signal SCK into clock signals CLKSI, CLKS2..., CLK, respectively.
Forms Sn. These clock signals are used to define the allowable phase range as shown in Figure 4 below. That is, for example, one cycle of the clock signal CLKSI defines the phase tolerance value Δ1, and one cycle of the clock signal CLKS2 defines the phase tolerance value Δ2. Clock signal CLK
S1. CLKS2°...CLKSn is selected by the multiplexer MPXI, and the selected clock signal CLKS is sent to the delay type flip-flop FFI.

These signals are respectively supplied to the clock input terminals of FF2.

Note that the above selection is performed based on the value in the data register PCR3.

Frequency dividing circuit DI V 1', DIV2', --DIVn
' C The above clock signal CLKSn is divided into clock signals fr1', fr2', . . . fr
form n.

An example of a waveform diagram of the clock signals fr1' and fr2' is shown in FIG. The frequency of the reference frequency signal fr is determined by selecting one of these clock signals by the multiplexer MPX2.

That is, the clock signal fr-1 selected by the multiplexer MPX2 is input to the input terminal of the flip-flop FFI, and is converted into a signal fr delayed by the period of - of the clock signal CLKS supplied to the clock terminal CLK and output. Output from the terminal. This output signal fr
is taken as the reference frequency signal.

The output signal fr is further input to the input terminal of the second flip-flop FF2, and is a signal fr delayed by one cycle of the clock signal CLKS supplied to the clock terminal CLK.
It is converted to -1 and output from the output terminal.

FIG. 4B shows a waveform diagram when the clock signal CLKSI is selected by the multiplexer MPXI and the clock signal f r 1' is selected by the multiplexer MPX2. The phase of the reference frequency signal fr is △
An inverter 3 and a NOR circuit NRI are provided to form a lock/unlock identification signal fw from the signal fr-1 advanced by 1 and the signal fr+x delayed by Δ1.

FIG. 4C shows a waveform diagram when the clock signal CLKS2 is selected by the multiplexer MPXI and the clock signal f r 2' is selected by the multiplexer MPX2. The phase is △ from the reference frequency signal fr
The lock/unlock identification signal fw is formed from the signal fr-1 advanced by 2 and the signal fr+1 delayed by Δ2.

In this way, when the frequency of the reference frequency signal fr is high (for example, the frequency of frl'), the high level period of the lock/unlock identification signal fw is narrowed △lX2), and when the frequency of the reference frequency signal fr is low (For example, the frequency of fry'), the high level period of the lock/unlock identification signal fw can be widened (Δ2×2). Therefore, it is possible to set an appropriate allowable phase difference in accordance with the switching of the frequency of the reference frequency signal fr.

Furthermore, in this embodiment, when the frequency of the reference frequency signal fr is constant, the lock/unlock identification signal f
The high level period of w can be changed. this is,
This is possible by selecting a different clock signal using the multiplexer MPX1 while a constant clock signal is selected using the multiplexer MPX2. The fourth diagram shows the selection by the multiplexer MPX1 from clock signals CLKS2 to C in the state shown in FIG. 4C.
A waveform diagram is shown when changing to LKSI. In this way, since the allowable phase difference (△X2) can be changed while the frequency of the reference frequency signal fr is constant, it is possible to freely set the accuracy when locking under a constant reference frequency. . That is, as the allowable phase difference is narrowed, the controlled frequency at the time of a-task becomes closer to the reference frequency, and the accuracy improves.

On the other hand, as the allowable phase difference is widened, the controlled frequency at the time of locking deviates from the reference frequency, and the accuracy decreases, but the effect is that the time until locking can be shortened.

The lock/unlock detection signal fw is supplied to the lock detection circuit LKD together with the signal fo to be frequency controlled. If the rising timing of the controlled signal fo is within the high level period of the lock/unlock detection signal fw, the four-way detection circuit LKD recognizes that it is in a locked state and sets the output signal S4 to a low level as described later. Stand down.

An operational waveform diagram of the lock detection circuit LKD is shown in FIG. CASEI is a case where the rising timing of the controlled signal fO is in the low level period of the detection signal fw, and the falling timing is in the high level period. C.A.S.
E2 is a case where both the rising and falling timings of the controlled signal fo are in the high level period of the detection signal fw. Case 3 is a case where the rising timing of the controlled signal fo is in the high level period of the detection signal fw, and the falling timing is in the low level period.

Therefore, the output signal S4 of the lock detection circuit LKD changes to the low level only in the cases 2 and 3.

NAND circuit N person 1 has a controlled signal f at one input terminal.
A signal S1 is generated by receiving a lock/unlock detection signal fw inverted by an inverter IIK at the other input terminal. Signal S1 and controlled signal f
o is a NAND circuit NA2 that constitutes a flip-flop.
and one input terminal of NA3, respectively. The output signal of the flip-flop circuit is inverted by the inverter I2 to form the input signal S2 of the NAND circuit NA4. The NAND circuit NA4 sets the output signal S3 to a low level during a period when the lock/unlock detection signal fw and the controlled signal fO are both at a high level and the signal S2 is at a high level. Therefore, like CASEI, the lock/unlock detection signal fw and the controlled signal f
Even if there is a period in which both o are at high level, signal S3 will not be brought to low level by the action of signal S2 unless the rising timing of controlled signal fo is within a predetermined range. The signal S3 is used as an input signal to the NAND circuit NA5 forming a flip-flop in the NAND circuit N-6. A high-level reset signal RD is normally applied to the input terminal of the NAND circuit N-6. When the signal S3 is set to low level, the output signal S4 is changed from high level to low level, whereby a locked state is detected. Since the output signal S4 maintains the low level until the reset signal RD is thereafter set to the low level, the locked state can be reliably recognized based on the output signal S4.

The effects obtained from the above examples are as follows.

(1) Since the phase tolerance range Δ, which is a reference for detecting the lock/unlock state, can be changed, the lock/unlock detection accuracy can be freely set.

(21) When changing the reference frequency signal supplied to the phase comparator circuit, lock/unlock detection of the PLL is performed with a phase tolerance that is changed inversely to the reference frequency, resulting in highly accurate This provides the advantage of being able to detect lock/unlock of the PLL.

(3) When changing the reference frequency signal supplied to the phase comparison circuit, it is easy to With this configuration, it is possible to obtain a highly accurate PLL lock/unlock detection circuit.

Although the invention made by the inventor of the present application has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it goes without saying that various changes can be made without departing from the gist of the invention. Nor. For example, the microcomputer may be configured with another semiconductor integrated circuit device. Further, in addition to the microcomputer, the channel selection information may be supplied from a key switch or the like.

The specific configuration of the PLL circuit can be changed in various ways. For example, a circuit that divides the oscillation signal of a voltage-controlled oscillator circuit may be composed of a fixed frequency dividing circuit (prescaler) and a program counter circuit, and may be equipped with a direct frequency dividing input and a pulse swallow input. It may be used by switching. Further, the specific circuit configuration of the detection circuit that detects lock/unlock of the PLL by varying the phase tolerance as described above can take various embodiments.

The present invention can be widely used not only in digital tuning systems for radio receivers but also in PLL circuits in which the frequency of a reference frequency signal can be switched.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in a PLL circuit that has a function of changing the reference frequency signal supplied to the phase comparator circuit, locking/unlocking of the PLL is performed with a phase tolerance that changes in inverse proportion to the set reference frequency. By performing the detection, locking/unlocking of the PLL can be detected with high accuracy.

[Brief explanation of drawings]

FIG. 1 shows a digital tuning system according to the present invention.
FIG. 2 is a block diagram showing an example of the semiconductor integrated circuit device that constitutes the system; FIG. 2 is a timing diagram showing an example of the operation of the fundamental frequency generation circuit RFC shown in FIG. 1; FIG. Reference frequency generation circuit RFG and lock detection circuit LKD shown in FIG.
FIG. 2 is a block diagram showing a specific example of the operation waveform diagram of the operation waveform diagram of FIG. LSI...Semiconductor integrated circuit device, Pct, PO2...
・Program counter circuit, PDRI to PDR4...
Data register, IB...input buffer, RFG...
・Reference frequency generation circuit, PFC...phase comparison circuit, L
KD...Lock detection circuit% PCRI, PCl3・
...Control register, MCU...Microcomputer, GO~G5...Gate circuit, MPXI, M
PX2...Microprocessor, FF1. FF2...
·flip flop. to

Claims (1)

[Claims] 1. Detection means for forming a detection signal when the phase difference between the controlled signal and the reference signal is within a predetermined range; and allowable phase difference changing means for changing the predetermined range. A PLL circuit characterized by having: 2. The PLL circuit according to claim 1, wherein the detection means forms the detection signal based on a detection pulse having a predetermined pulse width centered on an edge of the waveform of the reference signal. . 3. Claim 2, further comprising a reference frequency changing means for changing the frequency of the reference signal.
PLL circuit described in section. 4. The PLL circuit according to claim 3, further comprising means for setting the pulse width of the detection pulse according to the magnitude of the frequency of the reference signal. 5. The PLL circuit according to claim 4, wherein the pulse width is set inversely proportional to the frequency of the reference signal. 6, comprising a detection means for forming a detection signal when the phase difference between the controlled signal and the reference signal is within a predetermined range, and an allowable phase difference changing means for changing the predetermined range; A PLL characterized in that the detection means and the allowable phase difference changing means are controlled by a microcomputer.
circuit. 7. The PLL circuit according to claim 6, wherein the microcomputer is formed on the same semiconductor substrate as the PLL circuit.