JPS63263912A - Reference value generating device - Google Patents

Abstract

PURPOSE:To obtain a high reliable reference value suitable for an actual signal by generating the reference value at a serial signal period depending on the upper limit and the lower limit of the serial signal period detected from a parallel signal supplied externally. CONSTITUTION:The upper limit and the lower limit of the serial signal period of a parallel signal 1 are detected respectively by an upper limit deciding circuit 2 and a lower limit deciding circuit 3 and a reference value generating circuit 6 generates a reference value 7 based on the upper limit value 4 and the lower limit value 5. Then a comparison circuit 8 compares the parallel signal 1 at the serial signal period with the reference value 7 signal, and when the signal is larger than the reference value 7, an H level is outputted as a serial signal 9 and when the signal is smaller than the reference value 7, an L level is outputted as the signal 9.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention creates a serial signal as an "H (high)" level value and an "L (low)" level value depending on the magnitude of the parallel signal value. Among the serial signal detection circuits,
The present invention relates to a device for creating a reference value for determining whether a parallel signal value is an "H" level or an "L" level.

[Conventional technology]

FIG. 2 shows a conventional reference value creation device, and FIG. 3 shows a format diagram of the parallel signal 1 input to this reference value creation device.

This input parallel signal 1 mainly has no meaning as a signal, and always has a reference value averaging section 12 of one constant level, and the "H" level and "L" level depending on the magnitude of the parallel signal value than the parallel signal 1. It is divided into a serial signal section 22 in which a serial signal of 1 is output.

This reference value creation device uses the parallel signal 1 to create a reference value for the serial signal section 22 whose “H” level or L level is determined by the magnitude of the parallel signal value.
The values in the reference value averaging section 12 are averaged by an averaging circuit 10, and a value corresponding to +α is added to this value by a reference value creating circuit 11 to create a reference value 7.

Next, reference value 7 and serial signal section 22 of parallel signal 1
When the value of serial signal 1 is greater than reference value 7, serial signal 9 is output as "H" level, and the value of serial signal 1 is smaller than reference value 7. In this case, the serial signal 9 is output as "L" level.

FIG. 4 shows the configuration and signal waveforms of the averaging circuit 10 of FIG. 2. According to this averaging circuit, first, when the parallel signal l is before the reference value averaging section 12, the control circuit 18 outputs the average value initial setting signal 16 and clears the value of the averaging flip-flop 14. . When the parallel signal 1 inputs the reference value averaging section I2, the average value input signal 15 is output from the control circuit I8, and the value of the previous averaging flip-flop 14 and the value of the parallel signal ■ are averaged. The addition circuit 13 performs addition. When the parallel signal 1 completes the reference value averaging section 12, the control circuit 18 outputs the average value holding signal 17, and the average value holding flip-flop 19 causes the averaging adding circuit 13 to output the average value holding signal 17.
The output is held and output to the reference value creation circuit 11.

FIG. 5 shows the configuration and signal waveforms of the reference value creation circuit 11. According to this reference value creation circuit, first, the averaging circuit 1
A quasi-reference value 23 is created by adding +7 minutes to the average value obtained from 0 in the reference value creation adding circuit 20, and this value is passed through the limiter circuit 21.

In this limiter circuit 21, “
If the quasi-reference value 23 is in the range between the "H" level and the "L" level, the value of the quasi-reference value 23 is output as the reference value 7.

However, the value of the quasi-reference value 23 is “H” in the serial signal section 22.
If it is higher than the ``level'' or lower than the ``L'' level, if the quasi-standard value 23 is output as it is as the standard value 7,
The next comparison circuit 8 makes a correct judgment, which is a shame. Therefore, if the quasi-standard value 23 is higher than the "H" level, the reference value 7 is set to "H" level.
If it is lower than the "L" level, the reference value 7 is set to a value higher than the "L" level, and the reference value is kept within the range of the "H" level and "L" level of the serial signal section 22. .

[Problem that the invention seeks to solve]

The conventional reference value creation device averages the values of the reference value averaging section 12 of the parallel signal 1 and creates the value by adding +α as the reference value, so the value of +7 increases the reliability as the reference value. In addition, since the "H" level and "L" level values of the limiter circuit 21 are ideal values or calculated values, they do not depend on the actual signal. Therefore, the conventional reference value creation device has the drawback that it cannot be said to have high reliability.

An object of the present invention is to provide a reference value creation device that eliminates such drawbacks.

[Means for solving problems]

The reference value creation device of the present invention includes an upper limit judgment circuit and a lower limit judgment circuit that detect an upper limit value and a lower limit value of a serial signal section from a parallel signal supplied from the outside; It has a reference value creation circuit that creates a reference value, and a comparison circuit that compares the reference value and the serial signal section of the parallel signal to determine whether each bit of the serial signal is at an "H" level or an "L" level. are doing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention. This reference value creation device includes an upper limit determination circuit 2 that detects the upper II (“H” level) of the serial signal section 22 of the parallel signal 1 and outputs it as an upper limit value 4, and a lower limit ( “L” level)
a lower limit determination circuit 3 that detects and outputs the lower limit value 5; a reference value creation circuit 6 that creates a reference value 7 from the upper limit value 4 and the lower limit value 5; and a serial signal section 22 of the parallel signal 1 and the reference value 7. If the value of the serial signal section 22 is greater than the reference value 7, the serial signal 9 is set to “H”.
The comparator circuit (COMP) 8 outputs the "L" level as the serial signal 9 when the value of the serial signal section 22 is smaller than the reference value 7.

FIG. 6 shows specific circuit configurations of the upper limit determination circuit 2 and the lower limit determination circuit 3. These determination circuits include an upper limit determination flip-flop 24, a comparison circuit 25, a lower limit determination flip-flop 26, a plurality of inverters 27, a comparison circuit 28, and an upper/lower limit control circuit 29.

According to this circuit, first, the upper limit determination flip-flop 24 and the lower limit determination flip-flop 26 are initialized by the upper and lower limit initial setting signal 30 output from the upper and lower limit control circuit 29. The initial setting values at this time are the minimum value for the upper limit determination flip-flop 24 and the maximum value for the lower limit flip-flop 26. Then, parallel signal 1 is inputted to comparator circuit 2.
5, the value of the upper limit judgment flip-flop 24 is compared with the parallel signal 1, and if the value of the upper limit judgment flip-flop 24 is larger than the parallel signal 1, the upper limit rewriting signal 3 is
1 is not output, and the value of the upper limit determination flip-flop 24 does not change. If the value of the upper limit flip-flop 24 is smaller than the parallel signal 1, the upper limit rewrite signal 3
1 is output, making the value of parallel signal 1 the new upper limit flip-flop 24 value.

On the other hand, the comparison circuit 28 compares the value of the lower limit judgment flip-flop 26 with the parallel signal 1, and if the value of the lower limit flip-flop 26 is smaller than the parallel signal 1, the lower limit rewriting signal 32 is not output and the lower limit flip-flop 2
The value of 6 remains unchanged. If the value of the lower limit flip-flop 26 is larger than the parallel signal 1, a lower limit rewrite signal 32 is output, and the value of the parallel signal 1 is set as the new value of the lower limit flip-flop 26. Then, when the parallel signal 1 ends the serial signal section 22, the upper limit value 4
indicates the "H" level value of the serial signal 9, and lower limit value 5 indicates the "L" level value of the serial signal 9, respectively.

FIG. 7 shows a specific circuit configuration of the reference value generation circuit 6.

This reference value creation circuit includes a reference value creation addition circuit 35,
It is composed of a reference value creation flip-flop 36 and a reference value creation control circuit 37.

According to this circuit, the upper limit value 4 and the lower limit value 5 are first added by the reference value creation adding circuit 35, and in order to obtain a value intermediate between the upper limit value 4 and the lower limit value 5, the output of the reference value creation adding circuit 35 1
/2. When the serial signal section 22 of the parallel signal 1 ends, the reference value creation control circuit 37 outputs the reference value setting signal 38. Then, the reference value creating flip-flop 36 outputs the output of the reference value creating adding circuit 35 as the reference value 7.

FIG. 8 shows a concrete configuration of the reference value creation device of FIG. 1 using the circuits shown in FIGS. 6 and 7, in which the parallel signal 1 is 8 bits and the serial signal section 22 is 16 bits.
0 clock, and each bit of the serial signal has an 8-bit configuration with 20 clocks. Note that circuit elements that are the same as those shown in FIGS. 6 and 7 are designated by the same numbers. Control circuit 4 in Fig. 8
0 is a combination of the upper and lower limit control circuit 29 shown in FIG. 6 and the reference value creation control circuit 37 shown in FIG. 7.

Now, in the reference value creation device having the configuration shown in FIG. clock signal 4
2, upper and lower limit initial setting signal 30 and reference value setting signal 38
Create. FIG. 9 shows a time chart of input signals and output signals of the control circuit 40.

In the reference value creation flip-flop 36, the previously determined reference value 7 is set using the reference value setting signal 38. Next, the upper and lower limit initial setting signal 30 is output, and the value of the upper limit judgment flip-flop 24 is set to “00” (each bit is all 0).
), and the value of the lower limit judgment flip-flop 6 is set to "FF" (each bit is all 1).

Then, a serial signal 9 is extracted based on the signal in the serial signal section 22 and the reference value 7.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, a form suitable for the actual signal is obtained without using the ideal value or calculated value used in the conventional reference value creation device, so the reference value is reliable. This has the effect of increasing flexibility and simplifying the theory of operation.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the reference value creation device of the present invention, Fig. 2 is a block diagram of a conventional reference value creation device, Fig. 3 is a formant diagram of input parallel signals, and Fig. 4 is a conventional reference value creation device. FIG. 5 is a block diagram of the standard value creation circuit used in the conventional reference value creation device; FIG. 6 is the upper limit determination circuit and lower limit according to the present invention. FIG. 7 is a block diagram of a reference value creation circuit according to the present invention; FIG. 8 is a circuit diagram of an embodiment of the present invention; FIG. 9 is a control used in the embodiment of FIG. 8. It is a time chart of the signal. 1... Parallel signal 2... Upper limit judgment circuit 3... Lower limit judgment circuit 4... Upper limit value 5... Lower limit value 6... Standard Value creation circuit 7...Reference value 8...Comparison circuit 9...Serial signal 10...Averaging circuit 11...Reference value creation circuit 12... ... Reference value averaging section 13 ... Averaging addition circuit 14 ... Averaging flip-flop 15 ...
-Average value input signal 16...Average value initial setting signal 17...Average value holding signal 18...Control circuit 19...Average value holding flip-flop 20...
... Addition circuit for creating reference value 21 ... Limiter circuit 22 ... Serial signal section 23 ... Quasi-reference value 24 ... Upper limit judgment flip-flop 25 ...
・Comparison circuit 26... Lower limit judgment flip-flop 27...
・Inverter 28...Comparison circuit 29...Upper/lower limit control circuit 30...Upper/lower limit initial setting signal 31...Upper limit rewriting signal 32...Lower limit rewriting Signal 35... Addition circuit for creating reference value 36... Flip-flop 37 for creating reference value...
...Reference value creation control circuit 38...Reference value setting signal 40...Control circuit 41...Parallel frame signal 42...Parallel clock signal Agent Patent attorney Iwa Sa Yoshi Yukishiro H + Ichino I Hiroshi D -3 Tonto To

Claims (1)

[Claims] (1) An upper limit judgment circuit and a lower limit judgment circuit that detect an upper limit value and a lower limit value of a serial signal section from a parallel signal supplied from the outside, and a criterion for creating a reference value of a serial signal section from the upper limit value and the lower limit value. A reference value creation circuit comprising: a value creation circuit; and a comparison circuit that compares the reference value and the serial signal section of the parallel signal to determine whether each bit of the serial signal is at a "high" level or a "low" level.