JPS63262930A - System for multiplexing digital signal - Google Patents

Abstract

PURPOSE:To prevent crosstalk from being generated and to simplify a circuit, by applying bit adjustment on (m) frame signals branched from one main frame signal, and multiplexing them to high-order group signals respectively. CONSTITUTION:The bit adjustment are applied on the (m) frame signals branched from one main frame signal and they are multiplexed to the high-order group signals 7-1 and 7-2 so as not to generate the crosstalk on the high-order group signals 7-1 and 7-2 by the frame signals 9-1 and 9-2. In other words, synchronism is taken in each of the frame signals 9-1 and 9-2 basically, and based on the fact, required bit adjustment is applied. In such a way, it is possible to prevent the crosstalk that is a problem in a conventional asynchronous system from being generated, and also, it is enough to prepare only one main frame signal generator as a frame signal generator, then, the simplification of the circuit can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital multiplex conversion device, and in particular to a digital multiplex conversion device.
The present invention relates to a digital signal multiplexing method for multiplexing m low-order group signals into m high-order group signals.

〔overview〕

The present invention is a digital signal multiplexing method that multiplexes nXm (n, m are natural numbers) low-order group signals into m high-order group signals, in which m frame signals branched from one main frame signal are By adjusting the focus and multiplexing the high-order group signals, it is possible to prevent crosstalk, which would be a problem when the frame signals are asynchronous, and to simplify the circuit.

[Conventional technology]

Conventionally, an asynchronous multiplexing method has been used as a multiplexing method for this type of digital signal. That is, when asynchronously multiplexing nxm low-order group signals into m high-order group signals, m
The individual frame signals are asynchronously multiplexed into this higher-order group signal.

To explain the asynchronous multiplexing method in FIG. 3 as an example, four separated DSl signals 24-1 to
24-4 as two DSIC signals 27 which are higher-order group signals.
-1 and 27-2, two independent frame signals 29-1 and 29-2 are asynchronously multiplexed onto these DSIC signals 27-1 and 27-2.

In FIG. 3, 21a and 22b are transmitting counters that output frame signals 29-1 and 29-2, respectively, 23a and 23b are drive circuits thereof, and 25-
1 to 25-4 are read clocks, and 26-1 to 26
-4 is a stuff pulse.

[Problem that the invention seeks to solve]

The conventional asynchronous multiplexing method described above asynchronously multiplexes m independent frame signals into m higher-order group signals, which causes crosstalk to occur in these higher-order group signals. Also, when multiplexing into m higher-order group signals,
This method has the drawback that m number of transmitting side counters for frame configuration are required, which increases the circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal multiplexing system that eliminates the above-mentioned drawbacks, prevents crosstalk due to frame signals, and simplifies the circuitry.

[Means for solving problems]

The present invention provides a digital signal multiplexing system that multiplexes nXm (n, m are natural numbers) low-order group signals into m high-order group signals, in which m frame signals branched from one main frame signal are used. is characterized in that it performs necessary bit adjustment and multiplexes it into each of the above-mentioned higher-order group signals.

[Effect]

The m frame signals branched from one main frame signal are multiplexed into the respective high-order group signals by performing bit adjustment so that crosstalk does not occur in the higher-order group signals due to the frame signal. That is, in principle, each frame signal is synchronized, and then necessary bit adjustments are made.

Therefore, crosstalk, which is a problem in the conventional asynchronous system, can be prevented, and the circuit can be simplified by requiring only one main frame signal generator as a frame signal generator.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a digital multiplex converter according to a first embodiment of the present invention. This embodiment uses four DSI signals 4-1 and 4 as low-order group signals.
-4 as two higher-order group signals 03IC signal 7-1~
It includes a DSIC multiplex converter 2 that multiplexes the main frame signal 7-2, a transmitting side counter 1 that generates a main frame signal 9, its driving circuit 3, and a delay device (Di8).

Then, the frame signal 9- for the DSIC signal 7-1
1, the main frame signal 9 is input as is to the converter 2, and the frame signal 9-2 for the DSIC signal 7-2 is as follows.
Delay device 8 that can delay any number of bits from θ bit
Input via . This delay device 8 is composed of, for example, a simple shift register, and the 0SIC signals 7-1 and 7-
In order to prevent crosstalk caused by the frame signal from occurring in the frame signal 9-2, the frame signal 9-2 is
Shift from bit to multiple bits in 1-bit units.

In FIG. 1, 5-1 to 5-4 are readout clocks, and 6-1 to 6-4 are stuff pulses.

FIG. 2 is a block diagram showing a digital multiplex conversion apparatus as a second embodiment of the present invention, which is a generalization of the first embodiment shown in FIG. In this embodiment, the low-order group signal 14-
1 to 14-n into higher-order group signals 17-1 to 17-m, a transmission side counter 11 that generates the main frame signal 19, and its drive circuit 13,
It includes delay devices 19-2 to 19-m.

Then, the frame signal 19 for the higher-order group signal 17-1
-1, the main frame signal 19 is input as is, and the frame signal 19-2 for the higher-order group signal 17-2 is input to the delay unit 1.
Similarly, the frame signal 19-m for the higher-order group signal 17-m is inputted via the delay unit 18-2.
Manufactured through m.

In the operation of this embodiment, each of the frame signals 19-2 to 19-m is transmitted through a delay device 18-m so that crosstalk due to a hoom signal does not occur in each high-order group signal.
A shift of O bits or multiple bits is performed by 2 to 18-m. In addition, in FIG. 2, 15-1 to 15-
n is a read clock, and 16-1 to 16-m are stuff pulses.

Although the above embodiment shows an example of bit adjustment using a delay device, other methods such as inserting a switching circuit in place of the delay device and dropping several bits of the main frame signal during adjustment can also be used. It can be carried out.

〔Effect of the invention〕

As explained above, the present invention branches each frame signal of m high-order group signals from one main frame signal, and adjusts the mutual phases in units of 1 bit so as not to cause crosstalk in the high-order group signals. By entering
While reducing the crosstalk of m high-order group signals,
This has the effect of simplifying the circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of a digital multiplex conversion device as a first embodiment of the present invention. FIG. 2 is a block diagram showing the main parts of a digital multiplex converter according to a second embodiment of the present invention. FIG. 3 is a block diagram showing the main parts of a conventional digital multiplex conversion device. l, 11.21a, 21b... transmission side counter, 2.
22a, 22b-DSIC multiple conversion device, 3.13.
23a, 23b-drive circuit, 4-1 to 4-4.24-1
~24-4...DST signal, 5-1~5-4.15-
1 to 15-4. 25-1 to 25-4...read clock, 6-1 to 6-4. 16-1 to 16-n, 26-1 to
26-4...Stuff pulse, 7-1.7-2.27
-L27-2...DSIC signal, 8.18-2 to 1B
-m...Delay device (D), 9.19...Main frame signal, 9-1.9-2.19-1-19-m, 29
-L29-2...Frame signal, 12...Multiple conversion device, 14-1 to 14-m-...Low order group signal, 17 1
~17- m- higher order group signal.

Claims (1)

[Claims] (1) In a digital signal multiplexing method that multiplexes n×m (n and m are natural numbers) low-order group signals into m high-order group signals, m frame signals branched from one main frame signal are used. A multiplexing method for digital signals, characterized in that the signals are multiplexed into each of the above-mentioned higher-order group signals after performing necessary bit adjustment.