JPS63109621A - Multiplexer circuit - Google Patents

Abstract

PURPOSE:To allow each channel unit to cope with any data speed by providing a channel unit with equal scale incorporating a register at each channel to be multiplexed and setting its read speed. CONSTITUTION:N-Set (n=plural number) of channel units 101-10n are constituted equally, and each channel unit (101-10n) is provided with a register 12 storing tentatively an input signal and a read control circuit 13 controlling the read of the register 12. The read control circuit 13 includes the means setting its read clock corresponding to a different speed for the channel units 101-10n. Moreover, a means subject to time division multiplex is provided with a buffer circuit 14 provided to a read output channel of the register 12 at each channel unit and a coupling means coupling the output of the channel units 101-10n to one output. Thus, any channel copes with an optional data speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexer circuit for a multiplexing modem apparatus that performs time division multiplexing.

〔overview〕

The present invention provides a multiplexer circuit for a multiplexing modem device, in which each channel to be multiplexed is provided with an equal-sized channel unit containing a built-in register, and its readout speed can be set. It has also been designed to be compatible with

[Conventional technology]

FIG. 4 is a block diagram of a conventional multiplexer circuit. In FIG. 4, the multiplexer circuit decodes the coded selection signals 133 to 135 with a decoder 22, switches the selector 21 based on the decoding result, and converts the serial data 129 to 132 of each channel into parallel to serial data every baud rate clock. 23 to obtain serial multiplexed output data 128 in the next baud frame.

FIG. 5 is a time chart of each signal of a conventional multiplexer circuit. Figure 5 shows 7200bps for channel A.
data, and also shows the case where 2400bps data is allocated to channel B, where 100 is the baud rate clock,
122 is the channel data transmission timing (9600bp
s), 123 is input data of channel A, 125 is channel data transmission timing (2400 bps), 12
6 is the input data of channel B, 121 is the output data transmission timing (9600 bps), and 128 is the output data of the multiplexer circuit.

[Problem that the invention seeks to solve]

However, in such a conventional multiplexer circuit,
The channel to be used is determined by a coded selection signal. For example, if the channel names of data to be multiplexed are A, BSC, etc. in descending order of speed, channel A is always There was a drawback that multiplexing was not possible unless the highest speed data was allocated.

Therefore, if a failure occurs in one channel that is in use, and it takes time to recover, there is a drawback that it cannot be replaced with another unused channel.

The present invention solves the above-mentioned drawbacks and aims to provide a multiplexer circuit in which each channel can support any data rate.

[Means for solving problems]

The present invention provides a multiplexer circuit comprising n channel units corresponding to n input signals (n is a plurality of input signals) and means for time-division multiplexing the output signals of each channel unit. The units have the same configuration, and each channel unit includes a register that temporarily stores input signals and a read control circuit that controls reading of this register.The read control circuit corresponds to different speeds for each channel unit. the time-division multiplexing means includes a buffer circuit provided in the readout output path of the register for each channel unit, and a buffer circuit for combining the output of each channel unit into one output. and a coupling means.

The present invention can include a first-in, first-out register in which the register stores input signals sequentially, and a shift register in which the parallel outputs of the first-in, first-out register are input in parallel and output in series according to a read clock.

[For production]

By configuring n channel units equally,
Any input signal can be connected to any channel unit. The readout control circuit can be set according to the speed of its input signal. It becomes possible to immediately respond to input signals even if the channel number is changed.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a multiplexer circuit according to an embodiment of the present invention. In FIG. 1, from outside the figure, channel data transmission timing 101 and serial channel data 1 are shown.
02 are connected to the data and timing inputs of the first-in-first-out register 11, respectively. A baud rate differential pulse 103 is also connected to a baud rate differential pulse input of the first-in, first-out register 11. In the first-in, first-out register 11, channel data 102 is loaded at channel data transmission timing 101.

On the other hand, from outside the diagram are a baud rate i-minute pulse 106, an output data transmission timing 107, and selection signals 111 to 118.
are connected to the baud rate differential pulse input, timing input, and selection signal input of the parallel-to-serial converter 13, respectively. The parallel-to-serial converter 13 loads the selection signals 111 to 118, performs parallel-to-serial conversion using the output data transmission timing signal 107, and outputs the resultant signals. The output of parallel-to-serial converter 13 is connected to a timing input of shift register 12 and a control input of three-state buffer 14. A 1-minute baud rate pulse 104 is connected to the baud rate differential pulse input of the shift register 12 from outside the figure. First-in first-out register 1
1 to parallel data is connected to the data input of the shift register 12. In the shift register 12, the parallel-to-serial converter 1
The output of 3 connects this parallel data to the data input of the three-state buffer 14. Output data 119I of channel unit 10t is sent from three-state buffer 14 based on the content of the output of parallel-to-serial converter 13. Output data of each channel 1191-119R
are wire-ORed, multiplexed, and output outside the diagram.゛The operation of the multiplexer circuit having such a configuration will be explained. In FIG. 1, serial channel data 102 is loaded into first-in, first-out register 11 at channel data transmission timing 101.

On the other hand, the selection signals 111 to 118 loaded in parallel by the baud rate differential pulse 106 are subjected to parallel-to-serial conversion at the output data transmission timing 107.
The output of the parallel-to-serial converter 13 is connected to the control signal of the three-state buffer 14, which serves as the input clock of the first-in first-out register 11 and sends the parallel output of the first-in first-out register 11 to the three-state buffer 14.
Channel output data 119 is obtained by outputting or not outputting data depending on the contents of 8.

Output data 119 of each channel unit 101 to 10R obtained in this way. Multiplexing is realized by performing a wire-OR on each of the signals 1197 to 1197.

Note that FIG. 2 is a time chart of baud rate differential pulses of the multiplexer circuit of the present invention. In Figure 2,
100 indicates a baud rate clock, and 103, 104 and 106 indicate baud rate differential pulses shown in FIG.

FIG. 3 shows a time chart of each signal of the multiplexer circuit of the present invention.
, and also shows the case where 2400 bps data is allocated to channel B. Signals that are the same as those shown in FIG. Data and 127 are channel B output data.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of being able to support any data rate on any channel by using the same circuit for each channel.

Therefore, when a failure occurs in any of the channels in use that requires time to recover, by substituting an unused channel, it is possible to cope with an urgent emergency situation, which is useful for network communication.

Although the present invention has some redundancy in terms of hardware, if the number of channels increases by N times, the hardware scale also increases by N times, and the degree of increase in hardware scale with respect to the increase in the number of channels is smaller than in the past, making it easier to expand channels. There are advantages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplexer circuit according to an embodiment of the present invention. FIG. 2 is a time chart of each baud rate clock differential pulse of the multiplexer circuit of the present invention. FIG. 3 is a time chart of each signal of the multiplexer circuit of the present invention. FIG. 4 is a block diagram of a conventional multiplexer circuit. FIG. 15 is a time chart of each signal of a conventional multiplexer circuit. 10, ~107... Channel unit, 11... First-in first-out register, 12... Shift register, 13
. . . Parallel-serial converter constituting the readout control circuit, 14
...three-state buffer, 21...selector,
22... Decoder, 23... Parallel-serial converter, 10
0...Baud rate clock, 101...Channel data transmission timing, 102...Channel data, 1
03.104.106...Baud rate clock differential pulse, 107...Output data transmission timing, 111
~118... Selection signal, 119... Channel output data, 121... Output data transmission timing (96
00 bps), 122... Channel data transmission timing (7200 bps), 123... Channel A input data, 124... Channel A output data, 12
5...Channel data transmission timing (2400bp
s), 126...channel B input data, 127.
. . . Output data of channel B, 128 . . . Output data of the multiplexer circuit, 129 to 132 . Embodiment Fig. 1 Embodiment Each baud rate clock differential pulse Fig. 2 Il+ Conventional example Fig. 4 Conventional example Each signal time chart Fig. 5

Claims (2)

[Claims] (1) In a multiplexer circuit comprising n channel units corresponding to n input signals (n is a plurality of input signals) and means for time-division multiplexing the output signals of each channel unit, the n channel units have the same configuration, and each channel unit includes a register that temporarily stores input signals and a read control circuit that controls reading of this register. The time division multiplexing means includes a buffer circuit provided in the readout output path of the register for each channel unit, and a coupling unit for combining the outputs of each channel unit into one output. A multiplexer circuit comprising means. (2) The register includes a first-in, first-out register that sequentially accumulates input signals, and a shift register that receives the parallel outputs of the first-in, first-out register as parallel inputs and sends out serial output according to a read clock. multiplexer circuit.