JPS63262771A - Affine transformation processor - Google Patents

Abstract

PURPOSE:To simultaneously execute the affine transformation and the synthesis of a picture by simultaneously affine transforming picture information and a mask signal, associating and storing them. CONSTITUTION:When the mask signal M has a logic 1, the signal of a terminal A is outputted to a terminal Y in data selectors 4-11 according to the control of a data multiplexer 3. Therefore, an input signal B (base picture signal) and the mask signal M are inputted to a first FIFO (first in and first out) 19 through the selector 11 and the output of a i-th FIFO is inputted to a (i+1)th FIFO. When the mask signal M has a logic 0, the signal of the terminal B is similarly outputted to the terminal Y only in a k-th data selector. Therefore, only the k-th FIFO is rewritten by the affine transformed input signal A and the synthesized picture of the base picture and the input signal A is outputted from an FIFO 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an affine transformation processing device, and more particularly to an affine transformation processing device that can easily perform compositing processing of an affine-transformed image and a base image.

[Prior Art] In image information processing, affine transformation processing is often performed to reproduce a source image by enlarging, reducing, moving, rotating, etc. For example, it is possible to cut out a partial image from a certain image, perform affine transformation on the cut out partial image, and combine it with another image (base image). However, conventionally, a means for cutting out a partial image, a means for performing affine transformation on the cut out partial image, and a means for synthesizing the affine-transformed image with another image have been independent. For this reason, image synthesis requires images that have been affine-transformed in advance, and an intermediate memory is required to store them.

[Problems to be Solved by the Invention] The present invention eliminates the drawbacks of the prior art described above, and its purpose is to provide an affine transformation processing device that can simultaneously perform affine transformation and image synthesis. be.

[Means for Solving the Problems] In order to achieve the above object, the affine transformation processing device of the present invention has an image information input section for inputting image information to be affine transformed, and an image information input section for inputting image information to be affine transformed. A mask signal input section that inputs a mask signal that distinguishes the occupied area; and image information input by the image information input section and the input mask signal according to the contents of the mask signal input by the mask signal input section. The outline of the present invention is to include an affine transformation means for simultaneously performing affine transformation on the affine transformation means, and a storage means for storing the image information and the mask signal which have been affine transformed by the affine transformation means in association with each other.

Preferably, the storage means includes a base image information input section for inputting base image information, and the storage means stores the base image information input by the base image information input section, and performs affine transformation on the base image information. One aspect of this is to overwrite image information.

Preferably, a compositing means for composing base image information is provided, and one aspect of the compositing means is to compose the base image information outside the area occupied by the affine-transformed image information.

[Operation] In this configuration, the image information input section inputs image information to be affine-transformed, and the mask signal input section inputs a mask signal that distinguishes the area occupied by the image information to be affine-transformed. The affine transformation means simultaneously performs affine transformation on the image information inputted by the image information input unit and the input mask signal according to the contents of the mask signal inputted by the mask signal input unit. The storage means stores the image information affine-transformed by the affine transformation means and the mask signal in association with each other.

Preferably, the storage means includes a base image information input section for inputting base image information, and the storage means stores the base image information input by the base image information input section, and performs affine transformation on the base image information. Overwrite image information.

Preferably, the image forming apparatus includes a compositing means for composing base image information, and the compositing means composes the base image information outside the area occupied by the affine-transformed image information.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 3(A) to 3(C) are conceptual diagrams illustrating the general operation of the affine transformation processing of the embodiment. In FIG. 3(A), 100 is the input image memory or the original image itself, and the input address (x, y) of the input image memory 100 or the scanning address (x, y) when reading with a scanner etc.
For example, a partial image A to be subjected to affine transformation is specified in the area indicated by . In FIG. 3(B), 200 is another input image memory or the original image itself, and the base image B is stored in the area indicated by the input address (x, y) or scanning address (x, y). . Figure 3 (C)
In the affine transformation processing of the embodiment, for example, a partial image A cut out from the input memory 100 is transferred to the input memory 20.
0 coordinate system (x, y), translate in the X-axis direction by a distance ff1IH and in the Y-axis direction by a distance 1v, and further rotate partial image A counterclockwise by an angle θ around point a. A partial image A' is formed by overriding the partial image A' on the base image B, and the composite images are sequentially output to the outside.

At that time, the output buffer circuit that temporarily stores such a composite image is stored in the car from N (e.g., 8) first-in, first-out memories (FIFOs) 12 to 19 and N data selectors. The affine transformation synthesis processing of the embodiment is automatically performed while the output buffer circuit advances affine by affine from top to bottom along the Y-axis direction in the figure. In this case, the portion of the affine transformation processing related to parallel movement does not require any special coordinate transformation processing, and can therefore be performed by simple phase control by a CPU (not shown) or the like. For example, in FIG. 3C, the process of moving the distance V from the first X line to just before the XI affine passing through point a is phase-controlled by prohibiting the start of affine transformation processing, which will be described later, by the CPU or the like. In addition, on each X line after the X1 line, the process of moving the distance llH from the first affine to just before the YJ line passing through point a is controlled by phase control by delaying the start of the affine transformation process by the same CPU, etc. do.

The mask signal M is a signal that separates the boundary between the affine-transformed partial image A' and the base image B.

The mask signal M is, for example, a line X with point a as a reference.
This can be easily obtained by cumulatively adding a small increment in the X-axis direction ΔX=Δy tan θ every time I advances by ΔY (1 in the embodiment), and is generated in a DDA circuit (not shown).

In addition, in this embodiment, it is assumed that block processing of connected images after affine transformation processing, for example, block encoding processing of images, is performed, and the size of the block at that time is set to the number of columns m-4.
Assuming that the number of rows per line is n=4, affine transformation processing is performed in a manner suitable for this block encoding.

FIG. 1 is a circuit diagram showing an output buffer circuit of an affine transformation processing device according to an embodiment. In the figure, 1 is a digital differential analyzer that cumulatively adds minute incremental parameters ΔY (or ΔX) and outputs the upper 3-bit integer part.
The details will be described later based on FIG. 2. 2 is an exclusive OR circuit (EXOR), one input of which is the MSB output 12 (4'S) of the digital differential analyzer (DDA) 1.
The result is to subtract the value "4" from the integer output of DDAI. 3 is a 3-input 8-output multiplexer (DMLIX), and when the input to the gate terminal G is at the logic "0" level, the contents of the input terminals C (MSB), B, and A (LSB) are oo.

-111, the logic "0" level is output to the corresponding one of the output terminals Y0 to Y7, and when the input of the gate terminal G is the logic "1" level, the input terminal C
, B, and A, all signals at the output terminals Y0 to Y7 are at logic "1" level. 4 to 11 are 2 inputs 1
It is an output data selector, and when the input to the selection terminal S is at the logic "0" level, the signal from the input terminal A is output to the output terminal Y, and when the input to the selection terminal S is at the logic "1" level, it is output to the input terminal. Output the signal B to the output terminal Y.

The data depth of data selectors 4 to 11 depends on the larger data depth of input signal A or input signal B. For example, if the data depth of input signal A is 6 bits, a mask signal is added to this data depth. By adding 1 bit of M, the data depth of data selectors 4 to 11 is set to 7 bits. 12-19
is first-in first-out memory (FIF)
O), and constitutes an output buffer circuit in a narrow sense together with the data selectors 4 to 11. Similarly, the data depth is 7 bits, the storage capacity is 1024 words, and when data Do, DI, D2, etc. are taken in from the input terminal DI in synchronization with the clock signal CLK, 1024 words are input.
After the clock, data Do is sent to the output terminal DO in synchronization with the clock signal CLK.

DI, D2, etc. are output sequentially. 20 and 21 constitute a control section of the output buffer circuit together with the DDAI, EXOR2 and DMUX3, and 20 is a clock signal C.
A quaternary counter that counts LK, 21 is a quaternary counter 20
This is a D-type flip-flop (FF) that takes in the output signal 12 (MSB) of DDAI every time the ripple carry signal RC of Capacity 1024
It is a bit FIFO.

FIG. 2 is a circuit diagram showing details of the digital differential analyzer. In FIG. 0, 51 to 61 are data latch circuits,
The CPU calculates based on the rotation angle θ of the affine transformation, and holds the initially set increment parameter Δy (<t) in 11 bits. , 33 is a 14-bit full adder that cumulatively adds the incremental parameter ΔY during affine transformation. 3
4 to 4 are D-type flip-flops (FF) that hold the cumulative addition result of the increment parameter ΔY in 14 bits, of which the upper 3-bit integer part l0(1°5)I
II (2°s) and Iz (4's) are output to the outside.

4 is a timing chart showing the circuit operation of FIG. 1, and FIG. 5 is a diagram schematically showing details of the circuit operation of FIG. 1. For convenience of explanation, the detailed operation described below starts from the start point (point b) of the affine transformation of the X1+7 line in FIG.

<Initial state of the circuit> The CPU sets the incremental parameter ΔY based on the rotation angle θ in advance.
(for example, 0.6) and set it in the latches 31 to 32 before starting the affine transformation. Also, the CPU is X1+
At the start of the 7th line affine transformation, the quaternary counter 20.
FF21. and resets FFs 34 to 47 of DDAl. Incidentally, the FIFOs 12 to 19 and the FIFO 23 have stored the contents of the teno processing results (for example, the base image B and the logic "1" level of the mask bit attached to the iron, etc.).

Processing when mask signal M is at logic “1” level> When mask signal M is at logic “1” level, FIFO1
At the same time, the lower value image signal B and the logic "1" level of the mask bit are shifted into FIFO 9, and the entire contents of FIFOs 19 to 12 are shifted as they are. That is, when the mask signal M is at the logic "1" level, all the outputs of the DMUX 3 are at the logic "1" level, so the data selectors 4 to 11 all select the signal at the input terminal B. This allows FIF
Pixel data B of input signal B is input to input terminal DI of 019.
The logic "1" level of J, l, 7 and mask bit is added, the output data of FIFO19 is added to the input terminal DI of PIF018, and the process proceeds in the same manner.
The output data of the FIFO 13 is added to the second input terminal DI.

Further, the carry signal RC of the quaternary counter 20 is logic “0”.
” level, the output of the AND gate circuit 22 becomes the logic “0” level, and the logic “0” level is applied to the input terminal DI of the FIFO 23.

In this state, the first clock signal CLK is input (logic "0"
” level to logic “1” level), the content of the quaternary counter 20 changes from 0 to 1. In the DDAI, the increment parameter ΔY(
0,6) and the contents O of FF34 to 47 are added, and FF3
4-47 takes in the result of 0.6. However, DDAI
The upper 3 bit data output of is still O. Also, at this point, the mask signal M is at the logic "1" level, so the output buffer circuit simply performs a shift operation, and the FIFO 19 is set to XI+? The underlying pixel data Bj, 147 of the line and the logic "1" level of the mask bit are taken in, and the FIFO 23 takes in the logic "0" level.

When the second clock signal CLK is input, the content of the quaternary counter 20 changes from 1 to 2. DDAl's FF34
~47 takes in the addition result of 1.2, and its data output becomes 1. As a result, as shown in Fig. 5, the DMUX
The input number 3 increases by +1 in the opposite direction to the Y-axis direction, and the address for affine transformation increases along line a7. However, at this point, the mask signal M is at the logic "1" level, so the output buffer circuit simply performs a shift operation regardless of the address for affine transformation, and in this state, the FIFO 19 Data B
Jul, t+7 and the logic "1" level of the mask bit are captured, and the FIFO 23 captures the logic *O++ level.

When the third clock signal CLK is input, the content of the quaternary counter 20 changes from 2 to 3. DDAl's FF34
~47 takes in the addition result of 1.8, and its data output is 1. On the other hand, FIF019 is the base pixel data B
J+2. The logic "1" level of the toy and mask bits is taken in, and the FIFO 23 takes in the logic "O" level.

When the fourth clock signal CLK is input, the content of the quaternary counter 2o changes from 3 to 0, and at this time a ripple carry signal RC is output. This ripple carry signal RC is a signal obtained by detecting each m (4 in the embodiment) pixels in the X-axis direction. FF34-47 of DDAl is the addition result 2
．． 4, the data output will be 2. At this point, the most significant bit output I2 of DDAI is at the logic "0" level, so even if the ripple carry signal RC occurs, the FF
Cannot set 21. On the other hand, FIFOI9 contains base pixel data B J+3.1°7 and mask bit logic "1".
” level, and the FIFO 23 takes in the logic “0” level.

When the fifth clock signal CLK is input, the contents of the quaternary counter 20 change from 0 to 1 again.

FFs 34 to 47 of DDAI take in the addition result of 3.0, and the data output becomes 3. On the other hand, the FIF019 takes in the base pixel data BJ+4N and 7 and the logic "1" level of the mask bit, and the FIF023 takes in the logic "0 level".

Processing when the mask signal M is at the logic "0"level> When the sixth clock signal CLK is input, the mask signal M has changed to the logic "0" level. Mask signal M
When is at the logic "0" level, depending on the address of the affine transformation axis, if it is not applicable, the lower value image signal B is successively shifted into FIFO19, and according to the address of the affine transformation axis, any of PIF019 to 12 is shifted in. Select one of them, and apply affine transformation to the previously stored base image B and mask bit logic "1" level of partial image A' and mask bit logic "1".
0” level is overridden to form a composite image.

That is, when the mask signal M is at logic "0" level, DM
Since the output Yl corresponding to the address of the affine transformation axis outputted by UX3 becomes the logic °'0'' level, only the data selector corresponding to the output Yl will select the input signal A of its input terminal A. As a result, the affine-transformed partial image A' and the mask bit attached thereto are overridden at the logic "0" level in the output buffer circuit.

When the sixth clock signal CLK is input, the contents of the quaternary counter 20 change from 1 to 2 again.

FFs 34 to 47 of DDAI take in the addition result of 3.6, and their data output is 3. Also, at this point, the mask signal M is at the logic "0" level, so the DM
UX3 brings output Y to a logic "O" level. As a result, while the entire buffer circuit is being shifted, F
Regarding IFO 19, unless data selector 11 is selected by DMUX 3, Xl, 7th line base pixel data BJφS, I◆7. B”◆8.1 out of 7・°
The logic “0” level of the mask bit and the logic “0” level of the mask bit are captured, but from this point on, the input signal A
.

and overrides the logic "'0" level of the mask bit. In FIG. 5, the input signal A at this time is a pixel signal corresponding to the axis of line a7 of the affine-transformed partial image A'.

When the seventh clock signal CLK is input, the contents of the quaternary counter 20 change from 2 to 3 again.

FFs 34 to 47 of DDAI take in the addition result of 4.2, and the data output becomes 4. On the other hand, FIFO 19 continues to store the base pixel data BJ+8. l * y and mask bit logic parameter 0°° level is taken, but FIFO16
is the next input signal A J+ (and the mask bit logic “
O" level is overridden. PIF023 also takes in a logic "0" level.

When the eighth clock signal CLK is input, the content of the quaternary counter 20 changes from 3 to 0 again and outputs the ripple carry signal RC. FFs 34 to 47 of DDAI take in the addition result of 4.8, and their data output is 4 from the time of the seventh clock input. Therefore, when the 8th clock is input, the most significant bit output I2 of DDAI is logic "1".
” level, the ripple carry signal RC is FF
Set 21. This change in the FF 21 is a signal detected at each n (4 in the embodiment) lines in the Y-axis direction. As a result, the output of the AND gate 22 becomes a logic "1" level, and the input of the FIFO 23 also becomes a logic "1" level.The AND gate 22 detects that the affine transformation has advanced by four pixels in the Y-axis direction. On the other hand, DMU
Since the output of X3 has changed to Y4, FIFO 19 continues to contain the base pixel data Bj, 7, I+? FIFO 15 takes in the logic "0" level of the and mask bit, but the FIFO 15 overrides the logic "0" level of the next input signal A, and the mask bit. Further, since the input to the FIFO 023 is at the logic "1" level, the FIFO 23 takes in the logic "1" level.

In this way, affine transformation for three pixels could be performed while maintaining the shape along the axis of line a7.

Furthermore, if the clock signal CLK is sequentially applied in this state, the address of the affine transformation will advance more and more along the axis of line a.

However, since the output buffer circuit is only prepared for eight lines from PIF012 to PIF19, the affine transformation cannot be continued in this state. Therefore, the address of the affine transformation is decremented by 4 at this point by the control unit. That is, EXOR is set by FF21.
-4 at 2. In this way, the following affine transformation of a predetermined number of pixels can be performed again while maintaining the shape along the axis of line a. The logic "1" level stored in PIF023 is for notifying the subsequent processing device of this -4 change point.

When the ninth clock signal CLK is input, the contents of the quaternary counter 20 change from 0 to 1 again.

FFs 34 to 47 of DDAI take in the addition result of 5.4, but since it is -4, the input of DMUX3 becomes 1. On the other hand, the output Y0 of the FIFO 19 becomes a logic "0" level due to the input 0 of the DMUX 3 immediately before it.
This overrides the input signal AJ+3 and the logic "0" level of the mask bit. Furthermore, PIF023 takes in the logic "0" level.

It should be noted that the above operations are performed in multiples of 4 (block size m) by the quaternary counter 20. This is because, in order to perform mxn (4x4) block encoding in the subsequent stage, it is desirable that the change point of -4 be at a position divided by m. In addition, the above operation occurs in multiples of 4 using a quaternary counter, and FF21 checks the 4's bit of the addition output of DDAI to ensure that the value of the addition output does not greatly exceed 4 (block size n). Please also note that it is done as follows. By doing so, the output buffer circuit can be configured with only 2n FIFOs (eight in this embodiment) as in this embodiment.

[Other Embodiments] FIG. 6 is a circuit diagram showing an output buffer circuit of an affine transformation processing device according to another embodiment.

Comparing the embodiment shown in Fig. 6 with the embodiment shown in Fig. 1, ■DM
tJX3 is always active regardless of the mask signal M; ■ Gate circuit 25 is used instead of data selector 11;
The difference is that a gate circuit 25 is provided to control whether or not to write the input signal A to the FIFO 19, and (2) a data selector 24 circuit is added.

As a result, in this embodiment, input signal B is not written to FIFOs 19 to 12 at all, and mask signal M
Regardless of the contents of the input signal A and the mask signal M, the contents of the input signal A and the mask signal M are affine-transformed and written to the FIFOs 19 to 12. Similarly to the above, if the initial value of DDAI is O and the incremental parameter ΔY is 0.5, then the clock signal CL,
Every time K is input, the output data of DDA 1 is 0.0.
1, 1, 2, 3, 3, 4, 4.5.6, 6, 7.7, 0
．． 1,1. Although it changes as expected, D
The input of MUX3 is 0.0, 1, 1, 2, 3, 3, 4, 0, 1, 2, 2, 3
, 3, 4, 5, 1, 2, 2. The value of ... is added.

Therefore, due to the action of DMUX3, its output Y. NY,
Up to Y(1, YO, Yl, Yl, Y2.Y3.Y3.Y4.
YOl"' becomes the logic "0" level, and at each point the corresponding data selector switches from B inputs to A inputs.As a result, FIFOs 19 to 12 are filled with data as shown in FIG. Affine transformed input signal A on a white background
and the contents of the mask signal M are written. FIG. 7 also shows the contents of the FIFO 23 at the same timing, and the contents are unchanged from the previous embodiment.

On the other hand, B inputs of the data selector 24 are connected to input signal B, and A inputs of the data selector 24 are connected to the FIFO 12.
The S terminal input of the data selector 24 is connected to a specific bit (MSB mask bit in the embodiment) of the output of the FIFO 12. As a result, when the affine-transformed mask signal M is at the logic "O" level, A inputs of the data selector 24 are selected, and the affine-transformed input signal A and mask signal M are output. In addition, the affine-transformed mask signal M is logic “1”
At the level, B inputs of the data selector 24 are selected and the input signal B is output as is.

In the above embodiment, the case where the rotation angle θ of the affine transformation is smaller than π/2 has been described, but when the rotation angle θ is larger than π/2, the X glaze and the Y axis may be exchanged.

[Effects of the Invention] As described above, according to the present invention, image information and a mask signal are simultaneously subjected to affine transformation and are stored in association with each other, so that it is easy to distinguish them from other image information (background image information, etc.). This allows affine transformation and composition of images to be performed virtually simultaneously.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the output buffer circuit of the affine transformation processing device of the embodiment, Figure 2 is a circuit diagram showing details of the digital differential analyzer (DDA), and Figures 3 (A) to (C) are implementation examples. 4 is a timing chart showing the circuit operation of FIG. 1; FIG. 5 is a diagram schematically showing details of the circuit operation of FIG. 1; The figure shows another example of affine transformation! FIG. 7 is a diagram schematically showing details of the circuit operation of FIG. 6. In the figure, 1...digital differential analyzer (DDA), 2...
・Exclusive OR circuit (EXOR), 3...Data demultiplexer (DMUX), 4-11...Data selector, 12-19...First-in first-out memory (FIFO), 20...・Quadratic counter, 21...Flip-flop (FF), 22...
AND gate circuit, 23...first input
First-out memory (F r FO).

Claims (3)

[Claims] (1) An image information input section that inputs image information to be affin-converted; a mask signal input section that inputs a mask signal that distinguishes a region occupied by the image information to be affin-converted; and the mask signal input section affine conversion means for simultaneously performing affin transformation on the image information input by the image information input section and the input mask signal according to the contents of the input mask signal; An affine conversion processing device characterized by comprising a storage means for storing data in association with each other. (2) The storage means includes a base image information input section for inputting base image information, and the storage means stores the base image information inputted by the base image information input section, and also stores an image obtained by affin-converting the base image information inputted by the base image information input section. 2. The affine conversion processing device according to claim 1, wherein information is overwritten. (3) The method according to claim 1, further comprising a compositing means for composing base image information, wherein the compositing means composes the base image information outside the area occupied by the affine-transformed image information. Affin conversion processing device.