JPS63262743A - Channel control system - Google Patents

Abstract

PURPOSE:To prevent the use of a time for ending an instruction by shifting to a next processing when the instruction of a host computer cannot be executed in an input and output controller. CONSTITUTION:When there is a mistake in a command, the input and output device 9 informs that the execution of the command cannot be done. Therefore, a check condition is transmitted in a status phase. This signal is received by a channel 3, when a command complete is received, the channel 3 opens an SCSI bus and activates a timer 4. After a prescribed time elapses, the timer 14 outputs an interruption signal to the channel 3. The channel 3 obtains the SCSI bus according to this interruption signal again. Subsequently, the command is fed to the input and output controller 9 to store a sense byte in a control memory 4.

Description

[Detailed Description of the Invention] [Summary] A plurality of host computers and a plurality of input/output control devices are connected via a common bus, and a common bus is connected between one host computer and one input/output control device selected by one host computer. When transferring data by occupying the
The instruction is completed quickly so that the processing efficiency of the host computer does not decrease.

[Field of Industrial Application] The present invention relates to a small-scale information processing system in which a plurality of host computers operate by connecting a plurality of input/output control devices via a common bus. This invention relates to a channel control method that prevents a decrease in system processing efficiency when a given instruction cannot be executed.

In recent years, small-scale information processing systems have been constructed that process information by using a plurality of small computers such as office computers as host computers and connecting a plurality of small, large-capacity disk devices to the host computers. For example, S CS I (Small
Computer System Interface
) is now commonly used as a common interface with a high degree of freedom.

Therefore, a plurality of host computers and a plurality of input/output control devices, such as disk control devices, are each connected by a 5C3I interface, and one host computer and one disk control device selected by the host computer use the SC3I bus. It is exclusively used to transfer data.

By the way, the processor of the host computer sends a start I10 command to the channel, and the channel uses this command to acquire the 5C3I bus, selects the target disk control device, and selects the disk devices under this disk control device. Then, in order to transfer the target data, for example, a seek command is sent to position the head at the target position.

In this case, the seek operation takes time, so the 5C3I bus is temporarily released to allow other host computers to use the 5C3I bus, but when the disk drive nears the end of the seek operation, the disk controller is 5
After acquiring the C3I bus and recombining with the previously connected channel, data is transferred.

However, if there is an error in the instruction sent by the above-mentioned processor via the channel, such as a seek command, and the disk controller cannot execute this seek command, the termination of the star) I10 instruction sent by the processor It is necessary that the processing efficiency of the processor does not decrease due to the delay.

[Conventional technology]

FIG. 3 is a block diagram illustrating a conventional technique, and FIG. 4 is a diagram illustrating the operation of FIG. 3.

1-4. and 5 to 8 constitute a host computer, 1.5 is a processor that controls each host computer, 2.6 is a main storage device, 3.7 is a channel equipped with a 5csr interface, and 4.7 is a channel. 3 and 7 are control memories used respectively.

Reference numerals 9 to 11 are input/output control devices equipped with a 5C3I interface and connected to channels 3 and 7 of the host computer via a 5C8I bus.

12 and 13 are input/output devices connected to the input/output control device 9.

Input/output devices are also connected to the input/output control devices 10 and 11, but are not shown.

The operation shown in FIG. 3 will be explained using FIG. 4. processor 1
For example, when selecting the input/output device 12 to transfer data, it sends a start I10 command to channel 3, and if the 5C3I bus is free, channel 3 performs arbitration as shown in Figure 4. The SC3I bus is acquired through a phase called .

Subsequently, in a phase called selection, the input/output control device 9 is selected from the input/output control devices 9, 10, 11 and channel 7 connected to the 5CSI bus. Next, Message Out (
Message 0ut)
The input/output device 12 is selected from the input/output devices m12 and 13 connected to the selected input/output control device 9.

Here, channel 3 sends the first command that instructs the input/output device 12 what it wants to execute as a command (Command).
and) is sent to the 5C3I bus. The input/output control device 9 receives this command and controls the input/output device 12 to execute the instructed content, but if it detects that the command cannot be executed due to an error, it changes the status. ) in a phase called Check Condition (Check Con).
dition) on the 5C3I bus.

Channel 3 receives this check condition, and then input/output control device 9 receives the message in the message-in phase.
Command complete (Command Com) sent as a message to guarantee the contents of the status.
plete), the SC3I bus is temporarily released.

Upon receiving the check condition, channel 3 acquires the 5C3I bus again and sends a request sense command to input/output control device 9, so that processor 1 can consider whether the command cannot be executed. A sense byte (information fg indicating a state in which an instruction cannot be executed) is sent from the output control device 9, and the control memory 4
When stored in the CC-1 (some status is stored in the control memory 4, the status indicates the state of the input/output device at startup, and the start I
10 command is not executed).

When processor 1 is notified of CC-1, it issues a sense command to channel 3, transfers the sense byte stored in control memory 4 to main memory 2, analyzes this sense byte, and executes the next Decide what to do next.

The operations of the processor 5, main memory 6, channel 7, and control memory 8 are also similar to those described above, and therefore their explanations will be omitted.

[Problem that the invention seeks to solve]

As described above, in the past, when channel 3 received a check condition sent by the input/output control device 9, for example, once the SC3I bus was released, channel 3 was transferred to 5C3 again.
After acquiring the I bus, sending a request sense command to the input/output control device 9, and receiving a sense byte from the input/output control device 9 and storing it in the control memory 4, send CC=1 to the processor l. Therefore, it takes time from when the processor 1 sends the start I10 instruction until the CC-1 is returned to terminate this instruction.

In particular, once channel 3 releases the 5C3I bus, if another channel 7 or I/O controller 10 or I/O controller 11 acquires the SC3I bus, channel 3 will release the 5C3I bus until this process is completed. Since it is not possible to obtain CC-1, reporting of CC-1 will be extremely delayed.
During this time, the processor l is unable to proceed to the next process because one instruction is not completed, resulting in a problem that processing efficiency is significantly reduced.

[Means for solving problems]

The channel receives the sense byte from the input/output controller, stores it in the control memory, and then reports CG=1 to the processor because CC-1 is reported and the processor is unable to execute the command. This is in order to be able to provide a sense byte to consider whether the channel It is supposed to be processed.

Therefore, the channel cannot report to the processor that a check condition has been sent from the input/output control device by means of an interrupt, etc., and the channel status word (CSW) indicates that cc=i is not being executed. It reports and terminates one start I10 instruction.

Therefore, in the present invention, when a check condition is reported to a channel, CC=1 is immediately reported to the processor without sending a request sense command.
Terminate the start I10 instruction.

However, because of this, the timing of sending the request sense command, which is one of the processes of the start I10 instruction, is lost, so the request sense command is forced to be sent by an interrupt from a timer, for example, and the input/output control device read the sense byte of

If the next start I10 command is issued by the processor before reading of this sense byte is completed, CC-2 indicating that the channel is in use is reported.

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

In FIG. 1, a timer 14 is added to channel 3 in FIG.
It is activated when 1 is reported, and interrupts channel 3 after a predetermined time has elapsed. In response to this interrupt, the channel 3 sends a request sense command to the input/output control device 9, causes the input/output control device 9 to send out a sense byte, and stores it in the control memory 4.

[Effect]

By configuring as above, the channel can send a request sense command using a timer interrupt and store a sense byte from the input/output control device in the control memory, so it can report CG=1 to the processor. , even if the start I10 instruction is terminated, a sense byte can be sent in response to a sense command from the processor.

〔Example〕

FIG. 2 is a time chart explaining the operation of FIG. 1.

In FIG. 1, the same reference numerals as in FIG. 3 indicate the same functions. Processor 1 is connected to channel 3 as shown in Figure 2.
Start ■ Send 10 commands.

Channel 3 acquires the 5C3I bus in the arbitration phase shown in FIG. 4 in ■, selects, for example, the input/output control device 9 in the selection phase, selects the input/output device 12 in the message out phase, and enters the command phase. Send the command with .

Here, if there is a mistake in the command as described above, the input/output control device 9 sends a check condition in the status phase to notify that the command cannot be executed. When channel 3 receives a command complete in the message in phase, channel 3 releases the 5C3I bus, starts timer 14, and then reports CC=1 to processor 1 at step (3).

When a predetermined period of time has elapsed, the timer 14 sends an interrupt signal to the channel 3, as shown in (3). When channel 3 acquires the 5C3I bus again at ■ due to this interrupt signal,
A request sense command is sent to the input/output control device 9, a sense byte is sent out from the input/output control device 9, and is stored in the control memory 4.

When the storage of the sense byte is completed at ■ and a sense command is issued from the processor 1 at [phase], the channel 3 transfers the sense byte from the control memory 4 to the main memory 2 and stores it therein.

If channel 3 uses the SC3I bus to execute a request sense command, if processor 1 sends a start I10 command at the timing shown in (3), channel 3 will receive CC-- which indicates that the channel is in use. 2 to processor 1 at the @ timing. Therefore, processor 1 shifts to other processing until channel 3 becomes usable.

〔Effect of the invention〕

As explained above, in the present invention, when an instruction of a host computer equipped with a 5C3I interface cannot be executed by an input/output control device, in order to prevent it from taking time to complete the instruction, the host computer performs the next processing. This makes it possible to migrate to the system and prevent a decline in system processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, and FIG.
The figure is a block diagram explaining the conventional technique, and FIG. 4 is a diagram explaining the operation of FIG. 3. In the figure, 1.5 is a processor, 2.6 is a main memory, 3.7 is a channel, 4.8 is a control memory, 9.10.11 is an input/output control device, 12 and 13 are input/output devices, and 14 is a timer. 1. Figure 2. 2. Figure 3
figure

Claims (1)

[Claims] A plurality of host computers are connected to a plurality of input/output control devices (9) (10) via a common bus, and one input/output control device selected by one host computer and the common bus In a system that performs data transfer by occupying a common bus, an instruction sent from a processor (1) controlling the host computer to a channel (3) of the host computer controlling the common bus is transmitted to the channel (3) of the host computer controlling the common bus. a counting means (1) that is activated when information indicating that the control device cannot perform the execution is received on the channel (3) and generates an interrupt on the channel (3) when a predetermined period of time has elapsed;
4) is provided, and if the instruction sent by the processor (1) to the channel (3) cannot be executed by the input/output control device selected by the channel (3), the instruction is terminated, and
A channel control method characterized in that the counting means (14) is activated and the collection of information indicating a state in which an instruction cannot be executed is started from the input/output control device when an interrupt occurs.