JPS63260382A - Catv decoder - Google Patents

Abstract

PURPOSE:To decode a synchronizing signal correctly by using a counter reset by the timing pulse recovered from an audio signal and receiving an asynchronous clock having a sufficiently higher frequency than that of the timing pulse so as to generate a descrambling pulse. CONSTITUTION:The descramble pulse corresponding to the synchronizing signal part is generated by using a counter reset by the timing pulse demodulated and recovered from the audio signal and receiving the asynchronous clock having a sufficiently higher frequency than that of the timing pulse. Thus, the descrambling is applied by using the timing pulse nearly accurately corresponding to the position of the synchronizing signal of the carrier video signal and even if the timing pulse recovered at the reception side has a slight phase shift with respect to the synchronizing signal part of the carrier video signal, the synchronizing signal part is decoded correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a CAT''/decoder provided on the receiver side of CATv (cable television) broadcasting.

(b) Conventional technology One of the paid CATV broadcasting systems that scrambles TV (television) signals and sends them out so that only specific subscribers can receive them is Japanese Patent Laid-Open No. 58-5167.
There is a method shown in Publication No. 8 (HO4N 7/16)1, that is, in this method, each horizontal and vertical blanking period in an AM-modulated carrier video signal is compressed by a predetermined level compared to the video signal period. The carrier audio signal in the FM wave format is ASK modulated using a timing pulse indicating the synchronization signal position within the horizontal blanking period and a data pulse indicating the compression level, type of TV program, etc. The audio signal after ASK modulation and the video signal after compression are transmitted to the receiving side.

Therefore, in order to properly restore the synchronization signal portion by descramble, that is, amplitude expanding, the scrambled carrier video signal as described above on the receiving side, a descramble pulse that almost exactly corresponds to the horizontal synchronization signal is required. . For this reason, conventionally, a horizontal frequency oscillator is synchronously driven with a timing pulse demodulated and reproduced from the carrier audio signal to generate a descrambled pulse.

(c) Problems that the invention seeks to solveHowever,
Generally, the carrier audio signal is separated from the carrier video signal by a BPF (band pass filter), so the timing pulse in the pulse train signal obtained by ASK demodulating this audio signal is different from the carrier video signal due to the influence of the BPF. It does not exactly match the horizontal synchronizing signal of , and furthermore, the amount of phase shift differs from decoder to decoder depending on the characteristics of the BPF. Therefore, even if descrambling is performed using a descrambling pulse that precisely matches the timing of such a timing pulse, there is a problem in that the horizontal synchronizing signal portion cannot be correctly restored.

SUMMARY OF THE INVENTION Therefore, the present invention is to enable correct restoration of the synchronization signal part of the carrier video signal even when the timing pulse reproduced on the receiving side has a slight phase shift with respect to the synchronization signal part of the carrier video signal. With the goal.

(d) Means for solving the problem In the present invention, descrambling is performed by a counter that is reset by a timing pulse reproduced from a carrier audio signal and receives an asynchronous clock having a sufficiently higher frequency than the timing pulse. Now creates a pulse.

(e) Effect: According to the above configuration, descrambling can be performed using a timing pulse that corresponds almost exactly to the synchronization signal position of the carrier video signal, and therefore the synchronization signal portion can be correctly restored.

(f) Examples An embodiment of the present invention shown in the drawings will be described below.

FIG. 3(a) shows the baseband video signal before scrambling of the CATV broadcast received by this actual travel example,
Figure (b) shows A S Kl! with the timing pulse and data pulse mentioned above. The carrier audio signal that has been shifted by 1 m is shown in the same figure (C
) respectively represent the ASK demodulated output signal, and
FIG. 4(d) shows an enlarged view of a part of the period of the demodulated output signal.

That is, the compression of the video signal (a) is performed using the horizontal and vertical blanking periods (HB) (
The timing pulse (Pt) is performed for each horizontal synchronization pulse (VB) outside the VB period.
Ps) The pulse width is 2 μsec and corresponds to each pulse position. Further, the data pulse (Pd) is 20 μsec from the timing pulse (Pt) only at the 22nd to 38th H of each fee J read.

One pulse can be placed at a separate position, and when this pulse exists, it represents "1", and when it does not exist, it represents '0'. In other words, this data pulse (
Pd) is 17-pit data with pulses (always present) in the 22nd and 38th periods as start bits and stop bits, respectively, and the first 8 bits (23rd to 30th hours) are TV program programs. The latter 7 bits (31st to 37th H) represent the compression degree (dB) of the HB period and VB period.

Figure 2 shows the schematic configuration of the entire CATV decoder, and (1) shows the CATV decoder input via a coaxial cable.
A multiplexed signal input terminal (2) is a TV signal including a carrier video signal and a carrier audio signal from the multiplexed signal, and an FS to be described later.
A signal separation circuit that separates the K signal from the TV signal, (3) an RF amplifier that amplifies the TV signal, and (4) a PL output signal.
A first mixer receives the output of the first local oscillator (8) whose frequency is controlled by the L control circuit (11) and converts it into an IF multiplied signal, <5> is an IF amplifier, and (6> converts the output signal into an AF
A second local oscillator controlled by the T circuit (12) 9
), the second mixer converts the output signal into a 3-channel TV signal, and (7) converts the HB period and VB in the TV signal.
A gain switch circuit (10) is an output terminal for expanding the amplitude over a period, and these constitute a CATV humbverter (13).

On the other hand, (14) is an AS that performs ASK demodulation of the carrier audio signal extracted in the ink carrier format from the three channels of TV signals obtained at the output end of the gain switch circuit (7).
The KI tone circuit (15) obtains the pulse train signal reproduced thereby (FIG. 3 (C)) and subscriber data, which will be described later, from the MPU (microprocessor), which will be described later, and outputs the signal to the gain switch circuit (7). This is a descrambling control circuit that controls the gain switching timing and gain increase amount (dB).

In addition, (16) converts the 107.8 MHz FSK signal separated and derived from the signal separation circuit (2) into a local oscillator (1).
(7) is a mixer that converts the output signal into a 10.7 MHz signal, and (1g) is an FSX detection circuit that modulates the output signal to FSKff and reproduces so-called subscriber data indicating whether or not descrambling is possible for each subscriber. , (19) is an MPU to which the subscriber data and data from the descrambling control circuit (15), or a tuning signal from the keyboard (20) or the remote control signal receiving circuit (21) are input;
This MPU (19) tunes the converter (13) to each CATV channel by controlling the PLL circuit (11) in response to the channel selection signal, and also obtains both of the above data to tune the PLL circuit (11) for each program. Performs an operation to determine whether descrambling is possible.

FIG. 1 shows details of the descramble control circuit (15), and (22) shows the ASK demodulation circuit (14).
(23) is a first gate circuit for passing only the timing pulse (Pt) during the pulse train transmission; The first counter (25) is reset by the output pulse of the gate circuit, and the second counter (25) supplies/cuts off the 4 MHz clock pulse to this counter.
Gate circuit (26) is the output A of the first counter (24)
, C and a gate control circuit which receives the output pulses of the shaping circuit (22) and opens and closes the first and second gate circuits (23) and (25); (27) is the output of the first counter (24); a second counter, reset by C (occurs at count 240) and counting said clock;
) is an R3-FF (flip-flop) which is reset by the output of this second counter (occurred at count 40) and set by said output C of the first counter (24).

In addition, (29) is a detection circuit that detects the vertical blanking (VB) period depending on the presence or absence of a timing pulse from the first gate circuit (23), and (30) is opened during periods other than the VB period by the output of this detection circuit. The third gate circuit, (31), uses the output of this gate circuit as a data input,
The frequency dividing circuit (32) outputs the inverter (
33) with the inverted output as a clock.
F, (32) and (33) are second and third D-FFs that sequentially delay the output of the first D-FF.

(34) are these 1st to 3rd D・F F (31) (3
2) It is a changeover switch that selectively takes out each Q output of (33), and these constitute a descramble pulse phase changeover circuit (35).

On the other hand, (36) is the count output B (count 63) of the first counter (24) in order to extract the data pulse (Pd) in the pulse train signal from the waveform shaping circuit (22).
a fourth gate circuit opened by (occurred at ~127);
(37J is a data register circuit that partially stores the extracted data pulse, and (38) decodes the read data and matches the subscriber data from MPU (19) in FIG. 2. This is a data decoding/control circuit that performs detection, etc., and the output of this circuit (38) and the descrambling pulse from the changeover switch (34) are applied to the gain switch circuit (7) also shown in FIG. It has become.

The data decoding/control circuit (38) is shown in FIG.
Although it is configured in software as part of the unit of the P U (19), it is illustrated here as an independent circuit for ease of understanding.

Further, (39) is a circuit that obtains the output signal from the first gate circuit (23) and determines whether or not the received CATV signal is scrambled.
It is designed to be input to MPU (19) in the figure.

One embodiment of the present invention is generally configured as described above, and the details of the descramble pulse generating operation of the descramble control circuit (15) of FIG. 1, which is directly related to the gist of the present invention, will be explained below as shown in FIG. This will be explained with reference to time chart and kidney test.

First, when the power is turned on and the channel is switched, the first counter (24) is partially reset by an initial clear circuit (not shown). Therefore, in this initial state, the first counter (24) is reset by the output of the gate control circuit (26) at this time. The circuit (23) is open and the second gate circuit (25) is closed.

When the first timing pulse (Pt) in the pulse train signal (Fig. 4 (a)) (corresponding to Fig. 3 (c)) arrives at the waveform shaping circuit (22) from such a state, the pulse after the waveform shaping passes through the first gate circuit (23) to the first counter (
24). At the same time, the above corrugated board Mary>
A timing pulse (Pt) sets the gate control circuit (26), thereby opening the second gate circuit (25). Therefore, the first counter (24) counts up with the 4MHz clock, and when this counter (24) starts counting, the gate control circuit (24) responds to the count output A which becomes high immediately after that.
6) closes the first gate circuit (23), so the counter (24) is not reset again in response to the data pulse (Pd) immediately after the timing pulse (Pt).

In this way, the first counter (24) clocks 64
The count output B (Fig. 4 (b)) becomes high from the time when 127 pieces are counted until the time when 127 pieces are counted, and this output causes the fourth gate circuit (36) to
4) Open for 16-32 μSee after glue cent.

The first counter (24) continues to count up after that, and when the count output C (FIG. 4 (d)) becomes high after counting 240 clocks, that is, 60 μsec from the reset time, the gate control circuit 26> is reset, thereby opening the first gate circuit N (23> and closing the second gate circuit (25) to return to the initial state. Also, the count output C is output to the second counter (27).
) and set R3・FF<28>. Thereafter, the counter (27) generates an output (FIG. 4 (d)) after counting 40 4 MHz clocks from the reset time, that is, 10 Ilsec.
The output resets RS-FF (28). Since such an operation is repeated every time the timing pulse (Pt) in the pulse train signal (A) arrives,
From the above RS-F F (28) to 10 as shown in the same figure (E)
A pulse train with a width of μsec is obtained.

On the other hand, the third gate circuit (30) is connected to the VB period detection circuit (2
9) is open except during the VB period, so
The pulse train shown in FIG. 4 (e) is input to the descramble pulse phase switching circuit (35). The second and third D -F F (32) and (33) in this circuit have I
MHz glue 07 glue is also the 1st D -F F(3
1) are applied with their inverted clocks.

Therefore, the pulse train (g) appearing at the first contact (S) of the changeover switch (34) is 0.5μ
fiQc, I'm late. Similarly, the second and third contacts (S,
) are also delayed by 1.0 μsec and 1.5 μsec, respectively. In addition, the third
Since the output of the gate circuit (30) is always high during the VB period, the mixture of this high signal and the previous pulse train signal (to) undergoes a time delay as described above, resulting in three types of signals. One of them is selected by the changeover switch (34) and given to the gain switch circuit (7) as a descramble pulse.

On the other hand, as is clear from the above description, the fourth gate circuit (36)
Since the gate is open for 32 μs@c, each data pulse (Pd) in the column signal of FIG. 4(a) passes through this gate and is stored in the data register (37).

The data read out from the register (37) is then decoded by the data decoding/control circuit (38) to determine the amount of gain increase to be given to the gain switch circuit (7).

Here, the signal given to the gain switch circuit (7) is
7) Since the delay time of the descramble pulse (G) can be selected as 3-speed Gin as described above, the gain switch circuit (7)
) horizontal synchronization pulse (Ps) of the CATV signal input to
The switching position of the switch (34) may be selected depending on the degree of phase shift of the timing pulse (Pt) relative to the timing pulse (Pt). Note that the 4 MHz clock is completely (asynchronous) with the timing pulse (Pt), so even if the phase of the descramble pulse is corrected as described above, the descramble pulse will be completely (horizontally synchronized) due to the phase fluctuation of the clock. However, a phase shift of about 0.25 μsec at maximum occurs;
) is set at the optimum position.Also, by setting the pulse width of the descramble pulse (G) to 10 μseQ for the horizontal blanking period width of 12 μsec, slight phase fluctuations in the descramble pulse can be avoided. It is already possible to ignore it.

(g) Effects of the Invention According to the CATV decoder of the present invention, the phase of the descramble pulse can be easily switched, and there is no need for a PLL control circuit for synchronizing the clock for creating the descramble pulse. Therefore, the circuit configuration is also simplified.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the details of the time scrambling # control circuit in the CATV decoder according to the present invention, Fig. 2 is a block diagram showing the schematic configuration of the entire CATV decoder, and Fig. 3 is a block diagram showing the details of the time scrambling # control circuit in the CATV decoder according to the present invention. The signal waveform diagram in FIG. 4 is an operation time chart of the circuit in FIG. 1. (15): Descramble control circuit, (35): Descramble pulse phase switching circuit.

Claims (1)

[Claims] (1) In a CATV decoder that receives CATV broadcasting in which the synchronization signal part of the video signal is compressed by a predetermined level and the carrier audio signal is modulated with a timing pulse indicating the position of the synchronization signal and sent out, the audio It is reset by the timing pulse demodulated and regenerated from the signal,
A CATV decoder characterized in that a descramble pulse corresponding to the synchronization signal portion is created by a counter inputting an asynchronous clock having a sufficiently higher frequency than the timing pulse.