JPH0385982A - Video scramble descramble device - Google Patents

Abstract

PURPOSE:To attain descrambling with inexpensive constitution without giving adverse effect onto an audio signal and a video signal by synchronizing information for descrambling with a video signal and superimposing a sinusoidal wave with a frequency being a multiple of 1/n of a horizontal frequency onto an audio intermediate frequency signal and sending the result to the receiver side. CONSTITUTION:A video intermediate frequency signal is compressed in the timing from a synchronizing signal compression pulse generating circuit 6, a synchronizing separator circuit 5 separates a horizontal synchronizing signal and a vertical synchronizing signal from the video intermediate frequency signal and they are outputted to the synchronizing signal compression pulse generating circuit 6 and a 1/2fH oscillation section 7. Then 1/2fH sinusoidal wave of a horizontal frequency is superimposed onto an audio intermediate frequency signal synchronously with the video signal and the result is sent to the receiver side. Sinusoidal wave extraction means 29-31 at the receiver side extract a sinusoidal wave from the audio intermediate frequency signal, descramble means 33, 34, 36 detect the phase of the sinusoidal wave to obtain a compression timing of the synchronizing signal. Thus, even when scramble information is superimposed onto the audio intermediate frequency signal, the device constitution cost is reduced without giving adverse effect onto the audio signal and the video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a video scrambling/descrambling device for pay television broadcasting such as CATV.

(Prior art) In pay television broadcasting systems, in order to prevent unauthorized viewing by non-subscribers, video signals are scrambled and transmitted, and terminal receivers unscrambling to reproduce normal video signals. method is adopted.

As for this scrambling method, the level of the video intermediate frequency signal portion of the video intermediate frequency signal is compressed and transmitted on the transmission II side, and the audio intermediate frequency signal is AM-modulated to inform the receiving device of the compressed position and scrambled information is transmitted. There is something that transmits In this case, the receiving side performs AM detection on the audio intermediate frequency signal, reproduces the scramble information, determines the synchronous compression position, and obtains an expansion timing pulse to level-expand the video intermediate frequency compression position. There is.

However, according to this scrambling method, a rectangular wave-like pulse is superimposed on the audio intermediate frequency signal in order to transmit scrambled information. Therefore, there is a problem in that the trigger pulse is mixed into the audio signal itself, producing a buzzing sound.

A proposal to solve this problem has been made in Japanese Patent Application No. 62-223348.

According to this proposal, the frequencies fH (horizontal frequency) and n
Two fH sine waves (hereinafter referred to as fH and nfH sine waves) are combined to create scramble information, and this scramble information is superimposed on the audio intermediate frequency signal and transmitted. In the receiving device, the audio intermediate frequency signal is subjected to AM detection,
The fH sine wave and the nfH sine wave are separated, the content of scramble information is determined from the combination, the synchronous compression position is determined, and the expansion timing pulse is obtained based on this.

FIG. 9 is a timing chart for explaining the principle of generation of the extended timing pulse in the above system.

FIG. 9(a) shows a synchronously compressed video intermediate frequency signal, and the portion indicated by the broken line is the synchronously compressed portion. In addition, the figure (b) is an "M audio intermediate frequency signal, on which scramble information is superimposed to inform the receiving device of the synchronously compressed part. This scramble information is
It consists of a combination of a sine wave and an nfH (n-4 in FIG. 9) sine wave, which are superimposed by amplitude modulation. The same figure (C
) and (d) are the fII sine wave and nl, respectively, which are obtained by performing AM detection on the audio intermediate frequency and separating and extracting it using an imperial filter.
It is a sine wave. Figure (e) shows the extension timing pulse.

In the receiving device, the amplitude of the nfH sine wave becomes O (stops)
It has stop detection means for detecting timing and counting means for counting fH sine waves and generating extended timing pulses. As shown in FIG. 9(d), the nfH sine wave stops in the first half of the vertical synchronization period. The stop detection means detects this stop point, and the counting means starts from this stop point.
In the second cycle of the sine wave, as shown in FIG. 2(e), an extension timing pulse is generated to extend the level of the vertical synchronization period. Note that timing pulse generation in the counting means is determined by separately transmitted key data. In this example, the key data is "2". When the compression position is changed, the value of the key data is also changed.

Confidential data that informs the compression position of the horizontal synchronization signal is inserted into the portion corresponding to the latter half of the vertical synchronization period. As shown in FIG. 9(d), this secret data has an amplitude of an nfH sine wave (“1”).

The data is transmitted as nothing (“O”). On the receiving side,
This secret data is detected and decoded based on separately transmitted key data to obtain compressed position information of the horizontal synchronization signal. The expansion timing pulse of the horizontal synchronization signal is configured to be generated when a counter that is reset at, for example, the zero degree phase of the fH sine wave reaches a predetermined value, and the expansion timing pulse is generated when a counter that is reset at the zero degree phase of the fH sine wave reaches a predetermined value. This designated girl is determined based on the information.

By the way, in order to generate a high M degree fH sine wave and nfH sine wave on the transmitting side and perform highly accurate detection on the receiving side, an extremely highly accurate narrow band filter is required. Also, fH
The phase relationship between the sine wave and the nfH sine wave is important,
The slice level during detection needs to be highly accurate. For these reasons, there is a problem in that the entire system becomes extremely expensive.

(Problems to be Solved by the Invention) As described above, in the conventional video scrambling/descrambling device described above, it is necessary to generate and detect the f11 sine wave and the nfH sine wave with extremely high precision. There was a problem that the entire system became expensive.

The present invention has been made in view of such problems, and includes:
When scrambling information for unscrambling a video intermediate frequency signal is superimposed on an audio intermediate frequency signal, a superimposition method that does not adversely affect the audio and video signals is adopted, and the configuration of the device can be made inexpensive. The purpose is to provide a scramble/descramble device.

[Structure of the Invention] (Means for Solving the 12 Problems) A video scrambling/descrambling device according to the present invention includes, on a transmitting side, scrambling means for level compressing a synchronizing signal portion of a video intermediate frequency signal; sine wave superimposition means for superimposing a sine wave having a frequency 1/n times the horizontal frequency on the audio intermediate frequency signal in synchronization with the frequency signal;
a descrambling information providing means for adjusting the phase of the sine wave based on the compression timing of the synchronization signal; a sine wave extracting means for extracting the sine wave by detecting an audio intermediate frequency signal on the receiving side; and descrambling means for creating an expansion timing pulse for expanding the compressed portion of the video intermediate frequency signal from the phase of the sine wave from the sine wave extraction means.

(Function) In the present invention, on the transmitting side, the scrambling means performs scrambling by compressing the synchronization signal part of the video signal, and the information in the descramble is synchronized with the video signal and is 1/n times the horizontal frequency. By superimposing a frequency sine wave on the audio intermediate frequency signal, it is transmitted to the receiving side. On the receiving side, a sine wave extraction means extracts a sine wave from the audio intermediate frequency signal, and a descrambling means detects the phase of this sine wave, thereby obtaining the compression timing of the synchronization signal.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 and FIG. 2 show video scramble and video scramble according to the present invention.
1 is a block diagram showing an embodiment of a descrambling device, with FIG. 1 showing a transmitting device and FIG. 2 showing a receiving device. 3 is a timing chart for explaining the scrambling method of the embodiment shown in FIGS. 1 and 2, and FIG. 3(a) shows a scrambled video signal, and FIG. ) shows an audio intermediate frequency signal on which scramble information is superimposed, and FIG. 3(C) shows an expansion timing pulse for descrambling.

First, an overview of the scrambling method of this embodiment will be explained with reference to FIG.

The broken line in FIG. 3(a) shows the video signal before scrambling. In this way, in the video signal, the horizontal synchronization signal is compressed, and compression is also performed at a predetermined vertical synchronization compression position in the vertical retrace period. Furthermore, a sine wave having a frequency of (1/2) fH (hereinafter referred to as (1/2) fH sine wave) is superimposed on the audio intermediate frequency signal shown in FIG. 3(1)) by amplitude modulation. The (1/2) fit sine wave is synchronized with the video signal, and its phase is reversed at a predetermined position within the vertical retrace period. An expansion timing pulse (FIG. 3(C)) for descrambling is obtained from this audio intermediate frequency signal. The video signal is expanded and descrambled at the timing of this expansion timing pulse. (1/2>fH
After a period T1 from the point d at which the phase of the sine wave is inverted, the extension of the vertical retrace period ends and the extension of the horizontal synchronizing signal starts. Further, an extension timing pulse is generated in period T2II from the timing of the maximum amplitude of the (1/2) fH sine wave. In this embodiment, this period TI
, T2 are made variable between the transmitting device and the receiving device, thereby improving security.

Note that since one frame consists of 455 lines, the phase of the (1/2) fH sine wave is reversed every frame; You may switch. Also, when the phase of the (1/2) fH sine wave is switched once per frame, for fields where the phase is not switched, the horizontal synchronization signal from the previous field where the phase was switched is counted. This allows for easy interpolation.

Next, the transmitting device will be explained with reference to FIG.

An audio intermediate frequency signal is input to the input terminal 1, and a video intermediate frequency signal is input to the input terminal 2.

This audio intermediate frequency signal is given to the amplitude modulator 3. The amplitude modulator 3 amplitude-modulates the audio intermediate frequency signal based on a signal for descrambling from the (1/2) fH oscillation unit 7, which will be described later, and outputs it to the synthesis circuit 8. On the other hand, the video intermediate frequency signal is given to a gain switching circuit 4 and a synchronous separation circuit 5. The gain switching circuit 4 compresses the video intermediate frequency signal and outputs it to the synthesis circuit 8 at the timing of a compression pulse from a synchronization signal compression pulse generation circuit 6, which will be described later. The synchronization separation circuit 5 separates the horizontal and vertical synchronization signals from the video intermediate frequency signal and converts them into synchronization signal compression pulse generation circuits 6 and (1/2).
It is output to the fH oscillation section 7. The synchronization signal compression pulse generation circuit 6 outputs compression pulses synchronized with the horizontal and vertical synchronization signals of the video intermediate frequency signal.

In this way, the video intermediate frequency signal is scrambled by compressing the horizontal synchronizing signal by the gain switching circuit 4 and compressing it during a predetermined period of the vertical blanking period. This scrambled video intermediate frequency signal is applied to a synthesis circuit 8. The synthesis circuit 8 synthesizes the audio intermediate frequency signal superimposed with the descrambling information from the amplitude modulator 3 and the scrambled video intermediate frequency signal fj from the gain switching circuit 4, and converts the signal into a TV signal up-converter 9.
Output to. The TV signal up converter 9 converts the input signal to the frequency of a predetermined channel and converts the input signal to a synthesis circuit 1.
Output to 0.

(1/2) fH that outputs a signal for descrambling
The oscillator 7 receives the Domei signal and the 11-period value generator 11 and T2.
tilJ II by the data from the two-period value generator 12
I and outputs a (1/2) fH sine wave synchronized with the video signal. 11 period value generator 11 outputs data indicating period T1 shown in FIG. 3(C). Further, the T211j value generator 12 generates (1/2) fH
Data indicating the distance from the 90 degree phase of the sine wave or the position E' ((H period) of 2701i is outputted, and the generation timing of the horizontal extension timing pulse is determined by this data T2.

In this embodiment, as described above, this data TI
, T2 are variable, and the receiving side is also notified to ensure security. 11 period value generator 11 and data from T2JlJ value generator 12 Tl, T2
is given to the formatter 13.

The formatter 13 formats the data according to a predetermined communication procedure and outputs it to the FSK modulator 14. The FSK modulator 14 performs FSK modulation on this signal and outputs it to the combining circuit 10. A combining circuit 10 combines the signal from the FSK modulator 14 and the TV
The signal from the signal up converter 9 is combined and output to the output terminal 15.

FIG. 4 is a block diagram showing a specific configuration of the (1/2) fH oscillation section 7. As shown in FIG.

The horizontal synchronization signal from the synchronization separation circuit 5 is input to a rising edge detector 16. The rising edge detector 16 extracts the phase component of the horizontal synchronizing signal and outputs it to one input terminal of the OR circuit 17 and the clock terminal CK of the fH counter 18 . The output of the OR circuit 17 is given to the clear end CL of the counter 19, and the signal from the output end QO of the counter 19 is given to the OR circuit 17.
is applied to the other input terminal of .

Counter 19 counts a clock of 3.579545 MHz. Therefore, in 2 horizontal periods of the video signal, 4
There will be 55 counts. Since the signal from the output terminal QO is given to the OR circuit 17, the output pulse from the rising edge detection circuit 16 is given to the counter 19 once every two times, and the counter 19 is cleared by counting two lines of the video signal. be done. In this way, the counter 19 is designed to output a 214-hour, 0-count output in synchronization with the video signal.

The latch 20 receives data T1 from the T11 period value generator 11.
Based on this, the complement data TI' of T1 for the count value 455 is stored. The fH counter 18 receives a horizontal period signal from the rising edge detection circuit 16 at the clock terminal CK, is cleared by the vertical synchronization signal, and outputs information indicating the number of lines of the video signal to the XOR circuit 21. XO
The data TI' from the latch 20 is also input to the R circuit 21, and the XOR circuit 2142 performs the exclusive OR of the output of the latch 20 and the fH counter 18.
Coincidence with the output of is detected, and the inverted signal is sent to counter 1.
Output to preset input IPH of 9. The counter 19 receives the data end data (2) by this preset input.
27). As a result, the count value of the counter 19 is forcibly set to 227, and the phase inversion shown in FIG. 3(b) is performed.

The count output of the counter 19 is input to the ROM 22 . The ROM 22 stores values corresponding to the amplitude of the sine wave, and the ROM 22 sequentially outputs amplitude data to the D/A converter 23 based on the count output. The D/A converter 23 converts the output of the ROM 22 into an analog signal and outputs a sine wave signal. In this way, the D/A converter 23 outputs a (1/2)01 sine wave signal synchronized with the video signal.

Here, data T2 from the T2WJ value generator 12 is also given to the ROM 22. This data T2 changes the phase of the output of the ROM 22. In other words, (1/2)f from the D/A converter 33 is determined by the data T2.
The phase of the H sine wave! It has been IIWJ.

Note that the sum of T2 and the count value of the counter 19 is stored in the ROM.
22 also changes the phase of the sine wave to ti11
can be controlled. Further, as described above, the count value of the counter 19 is forcibly set to 227 by giving a preset input to the counter 19 based on the data T1. This means that D/
This corresponds to the phase of the sine wave from the A converter 23 leading by 180 degrees (the phase is reversed). In this way, the data TI
, T2 to improve security by adjusting the compression timing.

Next, the operation of the transmitting device configured as described above will be explained.

The video intermediate frequency signal from the input terminal 2 is input to the synchronization separation circuit 5 and the gain switching circuit 4. The synchronization separation circuit 5 separates the horizontal synchronization signal and vertical synchronization signal of the video signal and outputs them to the synchronization signal compression pulse generation circuit 6 and the (1/2) fH oscillation section 7. The opening signal compressed pulse generation circuit 6 generates a compressed pulse at the timing indicated by the broken line in FIG. 3(a) based on the horizontal and vertical synchronizing signals, and outputs it to the gain switching circuit 4. In this way, the gain switching circuit 4 compresses the video intermediate frequency signal at a predetermined vertical compression position between the horizontal synchronizing signal and the vertical g-line, and outputs the compressed signal to the combining circuit 8.

On the other hand, as described above, from the (1/2) fH oscillation unit 7, the signal is synchronized with the video signal and is transmitted during the period TI.

A (1/2) fH sine wave signal whose phase is switched based on T2 is output to the amplitude converter W4 3 as descrambling information, and this sine wave signal changes the amplitude of the audio intermediate frequency signal from the input terminal 1. The signal is modulated and applied to the synthesis circuit 8. In the synthesis circuit 8, the audio intermediate frequency signal superimposed with descramble information and the scrambled video signal are synthesized, and this synthesized signal is converted to a predetermined channel frequency in the TV signal up-converter 9 and given to the synthesis circuit 10. .

On the other hand, the 1-1 period value generator 11 and the 12-period value generator 12
The data TI, T2 from
The signal is modulated and applied to the synthesis circuit 10.

In this way, in the synthesis circuit 10, the scrambled video signal, the audio intermediate frequency signal including the descrambling information, and the FSK modulated period TI are generated.

The data of T2 is combined and output from the output terminal 15.

Next, the receiving device will be explained with reference to FIG.

In FIG. 2, an RF signal from the output terminal 15 in FIG. 1 is inputted to the input terminal 25 via a transmission path (not shown). This RF double signal tuner 26 and FSK detector 21
given to. The tuner 26 selects a predetermined channel, converts it into, for example, two television channels, and outputs it to the gain switching circuit 28 and the audio signal extraction circuit 29. F.S.
The K detector 27 detects the RF multiplied signal FSK and supplies it to the waveform shaping circuit 35.

The audio signal extraction circuit 29 extracts an audio signal from the video signal from the tuner 26 and supplies it to the AM detector 30. A.M.
The detector 30 detects the sine wave superimposed on the audio intermediate frequency signal in the transmitting device and outputs the detected sine wave to the waveform shaping circuit 32 via the bandpass filter 31 .

1? The range filter 31 is a filter for removing noise components, and the waveform shaping circuit 32 converts a sine wave into a pulse and outputs it to a phase detection circuit 33 and a descrambling position creation circuit 34. On the other hand, the waveform shaping circuit 35 shapes the waveform of the signal from the FSK detector 27, outputs data for period T1 to the phase detection circuit 33, and outputs data for period T2 to the descramble position creation circuit 34.

The phase detection circuit 33 obtains an end pulse indicating the end timing of a predetermined vertical synchronization compression position during the vertical retrace period from the pulse from the waveform shaping circuit 32 and the data of period T1, and outputs it to the descramble timing pulse generator 36. do. Further, the descrambling position creation circuit 34 is the waveform shaping circuit 3
2 and data indicating the period T2, the descrambling timing pulse generator 36 outputs a signal indicating a descrambling scale for waveform expansion to the descrambling timing pulse generator 36. The descramble timing pulse generator 36 includes a phase detection circuit 33 and a descramble position generation circuit 34.
An expansion timing pulse is generated at a timing based on the signal from the gain switching circuit 28 and outputted to the gain switching circuit 28. The gain switching circuit 28 expands the video signal from the tuner 26 based on this expansion timing pulse, expands the compressed synchronization signal, and outputs a normal video signal to a television receiver (not shown). There is.

FIG. 5 is a block diagram showing a specific configuration of the phase detection circuit 33, and FIG. 6 is a timing chart for explaining its operation. FIG. 6(a) shows the waveform shaping circuit 32.
FIG. 6(b) shows a pulse with a waveform-shaped frequency of (1/2)fH (hereinafter referred to as (1/2)fH pulse), and FIG. 6(b) shows a rising edge detection pulse from the NAND43. (C) shows the output of the counter 48, and FIG.
d) shows the output of the OR circuit 46, and FIG. 6(e) shows the NA
The output of the ND circuit 41 is shown.

The rising edge detector 40 is composed of latches 41, 42 and a NAND circuit 43, and the data end of the latch 41 receives (1/2) f I+ from the waveform shaping circuit 32 in FIG.
A pulse is input. The output IQ of latch 41 is NAND
It is connected to one input terminal of the circuit 43 and the data terminal of the latch 42, and the inverted output terminal Q of the latch 42 is connected to the NAND circuit 43.
is connected to the other input terminal of the The latches 41 and 42 are operated by a clock having a frequency of 4fH. A rising detection pulse is output from the NAND circuit 43, and this rising detection pulse is applied to one input terminal of the OR circuit 46, and is also applied to the NAND circuit 45.
It is applied to one input terminal of 47.

On the other hand, the counter 48 operates with a clock of 4f]1 and 0
Count ~7. Note that when a preset input occurs at the preset end PR of the counter 48, the count value becomes 6.
is preset to . Count output Q3 of counter 48
is applied to the other input terminals of the NAND circuit 45 and the OR circuit 46. The output of the NAND circuit 45 is applied to the clear end CL of the counter 49, and the output of the OR circuit 46 is applied to the clock end C of the counter 49. Counter 49 is N
It is cleared by the output of the AND circuit 45, and the output of the OR circuit 46 is counted. The output of the counter 49 is the XOR circuit 5
given to 0.

On the other hand, the latch 51 is given data for the period T1 from the waveform shaping circuit 35, and latches this data while also giving it to the XOR circuit 50. The output of the XOR circuit 50 is given to the other input terminal of the NΔAND circuit 47, and the end pulse from the NAND circuit 47 is applied to the descramble timing pulse generation VS36 and the preset terminal PR of the counter 48.
is output to.

In the phase detection circuit 33 configured in this manner, a pulse shown in FIG. 6(a) is applied to the latch 41. The rising edge detection circuit 40 composed of the latches 41 and 42 and the NAND circuit 43 outputs a rising edge detection pulse having a clock width of (1/2) at the input timing of the first clock after the rising edge of the H pulse. Figure 6(b)
). On the other hand, the counter 48 operates with a 4fH clock,
Count from 0 to 7. The count output from the output terminal Q3 of the counter 48 (FIG. 6(C)) is given to the OR circuit 46, and the clock terminal CK of the counter 49 is supplied to the clock terminal CK of the counter 49 as shown in FIG.
The pulse shown in is input. The output of the OR circuit 46 is (
1/2) indicates the number of pulses after phase inversion of the fH pulse.

A count output from the output terminal Q of the counter 49 is given to an XOR circuit 50. The XOR circuit 50 takes the exclusive OR of this count output and the data T1 from the latch circuit 51, that is, performs coincidence detection and outputs the NAND circuit 4.
Output to 7. The XOR circuit 50 outputs a signal indicating that a period T1 has elapsed since the phase of the (1/2)fH pulse was inverted.

An inverted signal of the rising detection pulse is also input to the NAND circuit 47, and the NAND circuit 4γ outputs an end pulse indicating the end of extension at the timing of the rising detection pulse. In this way, the end timing of the predetermined vertical synchronization compression position of the vertical retrace period is obtained.

Note that the counter 48 functions as a phase comparator synchronized with the (1/2) fH pulse, and the counter 49 functions as a counter that counts the number of phase shifts.

FIG. 7 is a block diagram showing a specific configuration of the descramble position generating circuit 34 in FIG. 2, and FIG. 8 is a timing chart for explaining its operation. FIG. 8(a) shows the output of the AM detector 30, FIG. 8(b) shows the (1/2) fH pulse from the waveform shaping circuit 32,
FIG. 8(C) shows the output of the counter 57, and FIG.
) indicates the extension timing pulse.

In FIG. 7, (1/2)f from the waveform shaping circuit 32
The H pulse is applied to a rising/falling detector 55. The rising/falling detector 55 detects the pulses indicating the rising and falling of the (1/2) full pulse by using the counter 5.
Clear end CL of 6 and preset end PR of counter 57
Output to. Counter 56 is 3.579545M HZ
1/2 of the count output is applied to the data end of the counter 57. Counter 57 is also 3.5
It operates with a clock of 79,545 MHz, and is preset to data at the data end by a preset input.

Descramble position creation circuit 34 configured in this way
corrects the rise and fall timing of the pulse from the waveform shaping circuit 32. As shown in FIGS. 8(a) and (b), the sine wave from the ΔM detector 30 is
When waveform shaping is performed at the slice level shown in a), section A,
B will not have the same length.

Therefore, if an extended timing pulse is created based on the phase of the (1/2) fH pulse from the waveform shaping circuit 32 shown in FIG. 8(b), the phase will shift. For this reason, a pulse unrelated to the slice level is first created, and the expansion timing pulse is obtained based on this pulse.

(1/2) fH pulse is detected by rising/falling detector 55
The pulses are applied to the clear end CL of the counter 56 and the preset end PR of the counter 57 at the rising and falling positions. The counter 56 is cleared at the rising and falling edges of the (1/2) fH pulse, and is 3.57
By counting the 9545 MHz clock, the occurrences of sections A and B are counted. This section A,
A half value of the count value corresponding to B is given to the data end of the counter 57. Counter 57 is 3.57954
A 5 MHz clock is counted, and the data edge value is preset at the rising and falling edges of the (1/2) fH pulse.

The interval length from the maximum amplitude position to the minimum amplitude position of the (1/2) fH sine wave shown in FIG. 8(a) is determined by setting the count value of the counter 57 to a count value corresponding to 8/2 at the rising timing of S. By setting the count value of the counter 57 to a count value corresponding to A/2 at the falling timing, a pulse that rises at the timing of the maximum amplitude position and the minimum amplitude position of the (1/2) fH sine wave (Fig. C)) can be output from a predetermined bit of the counter 57. Note that since the preset input is always given to the counter 57, it is possible to cope with a change in the phase of the (1/2) fH sine wave.

This pulse is used by the descramble timing pulse generator 3.
6 and based on the data of period T2, FIG.
The extension timing pulse shown in d) is generated. In this way, we deal with variations in the slice level.

Next, the operation of the receiving device configured as described above will be explained.

The R input signal from the input terminal 25 is converted into two television channels by the tuner 26, and the F
FSK detection is performed by the SK detector 27. By performing FSK detection, data of TI and T2 combined on the transmitting side is obtained from the waveform shaping circuit 35.

On the other hand, the two audio signal extraction circuits extract audio signals from the output of the tuner 26. This audio signal is transmitted to the AM detector 30
AM detection is performed at , and a sine wave for descrambling is detected. Furthermore, noise is removed from this sine wave by a bandpass filter 31, and the waveform shaping circuit 32 removes noise (
1/2) fH pulse and is applied to the phase detection circuit 33 and the descramble position creation circuit 34.

As mentioned above, the phase detection circuit 33 is connected to the waveform shaping circuit 35.
A termination pulse is generated based on the data T1 from , and the descrambling position generating circuit 34 outputs the pulse shown in FIG. 8(C) based on the data T2. These pulses are generated by a descramble timing pulse generator 36.
and the descramble timing pulse generator 3
6 outputs the expansion timing pulse to the gain switching circuit 28. The gain switching circuit 28 expands and descrambles the video signal from the tuner 26 at the timing of this expansion timing pulse, and outputs a normal video signal to the television receiver.

In this way, in this embodiment, the (1/2) fH sine wave synchronized with the video signal is superimposed on the audio intermediate frequency signal as information for descrambling. This (1/2)
The fH sine wave can be generated with a simple circuit, and
The video signal is not adversely affected by this sine wave. Furthermore, the phase of this sine wave is made variable by data TI and T2 to improve security.

Note that the present invention is not limited to the above embodiments,
For example, the frequency of the sine wave may be (1/n) f 11. Furthermore, although compression is performed horizontally and vertically in this embodiment, either one may be used.

[Effects of the Invention] As explained above, according to the present invention, the information for descrambling is synchronized with the video signal and
n) A sine wave with twice the frequency is superimposed on the audio intermediate frequency signal and transmitted to the receiving side, and the audio and video signals are not adversely affected by this sine wave, and
This sine wave can be generated, detected, and descrambled using an extremely inexpensive configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmitting device of a video scrambling/descrambling device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a receiving device of a video scrambling/descrambling device according to the present invention. Figure 3 is the first
FIG. 4 is a timing chart for explaining the outline of the scrambling method of the embodiment shown in FIG.
1/2) Block diagram showing the specific configuration of the fH oscillation section,
Figure 5 is a block diagram showing the specific configuration of the phase detection circuit in Figure 2, Figure 6 is a timing chart for explaining the operation of the phase detection circuit, and Figure 7 is a block diagram in Figure 2. FIG. 8 is a block diagram showing the specific configuration of the descrambling position generating circuit, FIG. 8 is a timing chart for explaining the operation of the descrambling position generating circuit, and FIG. 9 is a block diagram showing the operation of the conventional video scrambling/descrambling device. It is a timing chart for explanation. 1.2...Input terminal, 3...Amplitude modulator, 4...
Gain switching circuit, 5... Synchronization separation circuit, 6 Synchronization signal compression pulse, 7... (1/2) fH oscillator, 8.10... Synthesis circuit, 11... T1 period value generator, 12... T2 period value generator, 13... Formatter, 14... FSK modulator, 15... Output terminal.

Claims (1)

[Scope of Claims] On the transmitting side, a scrambling means for level compressing the synchronization signal portion of the video intermediate frequency signal, and a sine wave having a frequency 1/n times the horizontal frequency in synchronization with the video intermediate frequency signal as an audio intermediate frequency signal. a sine wave superimposition means for superimposing the frequency signal on the frequency signal; a descrambling information adding means for adjusting the phase of the sine wave based on the compression timing of the synchronization signal; A sine wave extraction means for extracting a sine wave having a frequency 1/n times the frequency, and an expansion timing pulse for expanding the compressed part of the video intermediate frequency signal from the phase of the sine wave from the sine wave extraction means. A video scrambling device characterized in that it is equipped with a descrambling means for
Descrambling device.