JPS63260220A - Rush current preventing circuit - Google Patents
Rush current preventing circuitInfo
- Publication number
- JPS63260220A JPS63260220A JP9357687A JP9357687A JPS63260220A JP S63260220 A JPS63260220 A JP S63260220A JP 9357687 A JP9357687 A JP 9357687A JP 9357687 A JP9357687 A JP 9357687A JP S63260220 A JPS63260220 A JP S63260220A
- Authority
- JP
- Japan
- Prior art keywords
- current
- source
- power
- circuit
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 12
- 238000009499 grossing Methods 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は１通信機器や電子機器の電源投入時における突
入電流を防止する回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that prevents inrush current when a communication device or an electronic device is powered on.
本発明は、突入電流が発生する経路にパワーＭＯＳ・Ｆ
ＥＴを直列に接続し、パワーＭＯ８，ＦＦ１Ｔのゲート
・ソース間電圧変化に対するドレイン・ソース間オン抵
抗変化を利用することにより、突入電流を防止するよう
にしたものである。The present invention provides power MOS/F in the path where rush current occurs.
Inrush current is prevented by connecting ETs in series and utilizing the change in on-resistance between the drain and source in response to the change in voltage between the gate and source of the power MO8 and FF1T.
従来、上記の突入電流の対策として、電流経路に突入電
流制限用の抵抗と一定時限後にオン動作するリレー接点
又はサイリスタとを並列に接続し【、突入電流を制限す
る方法が取られていた。第５図にかような従来回路の一
例を示し、第６図にその電流特性を示す。第５図におい
【、（１）は直流電源、（２）は電源スィッチ、（３）
は抵抗、（４）は時限回路、（５）は時限回路（４）に
よって駆動されるリレーコイル、（６）はリレー接点、
（７）は平滑用コンデンサ、（８）はＤ／Ｄコンバータ
等の負荷回路を示す。同図において、電源スィッチ（２
）を閉じると、直流電源（１）からの電流ｉＵ低抵抗３
）を経て平滑コンデンサ（７）と負荷回路（８）に流れ
る。この場合、平滑コンデンサ（７）への充電電流は突
入電流として第６図■に示すように流れる。時限回路（
４）によって一定時間後にリレーコイル（５）か駆動さ
れ、ＩＪ ７−接点（６）が閉じる。すると、抵抗（３
）により減衰していた突入電流は、リレー接点（６）を
介して第６図■に示すように再び増大し、やがて減衰し
て定常電流に落着く。Conventionally, as a countermeasure against the above-mentioned inrush current, a method has been taken in which a resistor for inrush current limitation is connected in parallel with a relay contact or a thyristor that turns on after a certain period of time in the current path to limit the inrush current. FIG. 5 shows an example of such a conventional circuit, and FIG. 6 shows its current characteristics. In Figure 5, (1) is the DC power supply, (2) is the power switch, (3)
is a resistor, (4) is a timed circuit, (5) is a relay coil driven by the timed circuit (4), (6) is a relay contact,
(7) shows a smoothing capacitor, and (8) shows a load circuit such as a D/D converter. In the figure, the power switch (2
) when closed, the current iU from the DC power supply (1) low resistance 3
) to the smoothing capacitor (7) and the load circuit (8). In this case, the charging current to the smoothing capacitor (7) flows as an inrush current as shown in FIG. Timed circuit (
4) drives the relay coil (5) after a certain period of time, and the IJ 7-contact (6) closes. Then, the resistance (3
), the inrush current increases again via the relay contact (6) as shown in FIG.
第６図■は、上述のような突入電流制限回路かない場合
の突入電流を示す。同図の■と■を比べると、突入電流
の大きさか若干抑えられていることが認められる。FIG. 6 (■) shows the inrush current when there is no inrush current limiting circuit as described above. Comparing ■ and ■ in the same figure, it can be seen that the magnitude of the inrush current has been slightly suppressed.
しかし、従来の突入電流制限回路では、依然として■の
ように成る程度の突入電流が流れるばかりでなく、抵抗
を介して限流させるため、電源スイツチ投入後機器か正
常に動作するまでに時間を要するなどの欠点がある。However, with conventional inrush current limiting circuits, not only does the inrush current still flow as shown in ■, but the current is limited through a resistor, so it takes time for the device to operate normally after the power switch is turned on. There are drawbacks such as.
本発明は、突入電流制限回路にパワーＭＯ８，ＦＥＴを
直列に接続し、パワーＭＯ８，ＦＥＴのゲート・ソース
間電圧変化に対するドレイン・ソース間オン抵抗変化を
利用するようにした。In the present invention, the power MO8 and the FET are connected in series to the inrush current limiting circuit, and the change in on-resistance between the drain and source of the power MO8 and the FET with respect to the change in the voltage between the gate and source of the power MO8 and the FET is utilized.
パフ −ＭＯＳ 、 ＦＥＴは、第３図に示すようなＶ
ＧＳ （ゲート・ソース間［圧）対Ｉｎｓ （ドレイン
・ソース間電流）特性を有するので、電源投入後パワー
ＭＯ８，ＦＥＴのゲート・ソース間に徐々に上昇する電
圧を印加することにより、突入電流を防止することがで
きる。Puff-MOS, FET has V
Since it has a GS (gate-source voltage) vs. Ins (drain-source current) characteristic, inrush current can be reduced by applying a voltage that gradually increases between the gate and source of the power MO8 and FET after power is turned on. It can be prevented.
第１図は本発明の第１の実施例を示す回路図、第２図は
その゛電流特性例を示す図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing an example of its current characteristics.
第１図において、従来例と対応する部分には同一の符号
を付した。（９）は抵抗、ｆｉＧはコンデンサ、ｕＤハ
パワー ＭＯＳ −ＦＥＴ ヲ示す。なお、（２−１）
は電源スイツチ補助ブレーク接点である。同図において
、電源スィッチ（２）を閉じると、直流電源！１１から
の電圧は、抵抗（９）、平滑コンデンサ（７）及び負荷
回路（８）の一端に印加される。この時点では、平滑コ
ンデンサ（７）及び負荷回路（８）の他端に接続されて
いるパワーＭＯ８、ＦＥＴ （ｆｉｌがオフ状態にある
ため、電流ｉは流れない。In FIG. 1, parts corresponding to those of the conventional example are given the same reference numerals. (9) is a resistor, fiG is a capacitor, and uD is a power MOS-FET. Furthermore, (2-1)
is the power switch auxiliary break contact. In the figure, when the power switch (2) is closed, DC power is turned on! The voltage from 11 is applied to one end of a resistor (9), a smoothing capacitor (7) and a load circuit (8). At this point, the power MO8 and FET (fil) connected to the other ends of the smoothing capacitor (7) and the load circuit (8) are in the off state, so no current i flows.
一方、十分に大きい抵抗値をもつ抵抗（９）を介してコ
ンデンサαＣに充電が行われ、コンデンサα０両端の電
圧が上昇し、これがパワーＭＯＳ・ＦＥＴＱυのゲ−）
（Ｇ）とソース（Ｓ）間に印加される。ここで、パワ
ーＭＯＳ・ＰＥＴは第３図に示すような特性を有する。On the other hand, the capacitor αC is charged via the resistor (9) with a sufficiently large resistance value, and the voltage across the capacitor α0 rises, which is the voltage of the power MOS/FET Qυ.
(G) and the source (S). Here, the power MOS/PET has characteristics as shown in FIG.
同図中、横軸はＧＳ間電圧ＶＧＳ、縦軸はドレイン（Ｄ
）とソース（Ｓ）間を流れる電流ＩＤＳを示す。したが
って、パワーＭＯＳ・ＦＥＴ（ｌυのドレイン・ソース
間のオン抵抗は、電源投入後徐々に下がり始め、電流ｉ
は緩やかに流れ始め次第に定常電流に達する。その状態
を示すものが第２図である。同図において、■は第６図
の■と同様に突入電流防止回路が全くない場合の電流特
性、■は第１図実施例の電流特性を示す。In the figure, the horizontal axis is the GS voltage VGS, and the vertical axis is the drain (D
) and the source (S). Therefore, the on-resistance between the drain and source of the power MOS/FET (lυ) begins to gradually decrease after the power is turned on, and the current i
begins to flow slowly and gradually reaches a steady current. FIG. 2 shows this state. In the figure, ``■'' shows the current characteristics in the case where there is no inrush current prevention circuit, similar to ``■'' in FIG. 6, and ``■'' shows the current characteristics of the embodiment in FIG. 1.
第４図は、本発明の第２の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
第１図はＮ型パワーＭＯ８，ＦＥＴを使用した実施例で
あるが、第４図に示すようにＰ型パワーＭＯ８，ＦＥＴ
を使用することもできる。本実施例の構成、作用及び効
果は第１図のものと変わらないので、重複説明を省略す
る。Figure 1 shows an example using an N-type power MO8, FET, but as shown in Figure 4, a P-type power MO8, FET is used.
You can also use The configuration, operation, and effects of this embodiment are the same as those in FIG. 1, so redundant explanation will be omitted.
なお、上述の例では、パワーＭＯ８，ＦＥＴ（１１）の
駆動回路として時定数を適当に選んだＲＣ回路を用いた
が、パワーＭＯＳ・ＦＥＴｒｉυのＧＳ間電圧ＶＧＳを
徐々に上昇させる如き作用をするものであれば、他のも
のを用いてもよい。In the above example, an RC circuit with an appropriately selected time constant was used as the drive circuit for the power MO8 and FET (11), but the RC circuit has the effect of gradually increasing the GS voltage VGS of the power MOS/FET Triυ. Any other material may be used as long as it is suitable.
以上説明したとおり、本発明によれば、電源投入時にお
ける突入電流を全く発生せず緩やかな電流供給を行うの
で、供給電源側装置において平常時供給電力以上の電力
を消費しない。また、突入電流による雑音（サージノイ
ズ）も発生しないので、他装置への影響を防止できる。As described above, according to the present invention, no inrush current is generated when the power is turned on, and a gradual current is supplied, so that the power supply side device does not consume more power than the normally supplied power. Further, since noise (surge noise) due to rush current is not generated, it is possible to prevent influence on other devices.
更に、電源投入後正常電流に達するまでの時間を容易に
調整しうる。しかも、回路構成か簡単で、装置の小形化
か可能となる利点がある。Furthermore, it is possible to easily adjust the time it takes to reach the normal current after the power is turned on. Moreover, the circuit configuration is simple and the device can be made smaller.
第１図は本発明の第１の実施例を示す回路図、第２図は
その電流特性例を示す図、第３図はパワー ＭＯＳ 、
ＦＥＴのｖｃｓ−ＩＤＳ％性曲線図、第４図ハ本発明
の第２の実施例を示す回路図、第５図は従来例を示す略
式回路図、第６図は従来例の電流特性を示す図である。
（２）・・・・・・電源スィッチ、Ｕυ・・・・・・パ
ワーＭＯ８，ＦＥＴ。
（９，１０）・・・・・・パワーＭＯＳ・ＦＥＴの０８
間に電源投入後徐々に上昇する電圧を印加する手段、■
、■、■・・・・・・従来例の電流特性、■・・・・・
・本発明による電流特性。FIG. 1 is a circuit diagram showing the first embodiment of the present invention, FIG. 2 is a diagram showing an example of its current characteristics, and FIG. 3 is a power MOS,
vcs-IDS% characteristic curve diagram of FET, Figure 4 is a circuit diagram showing the second embodiment of the present invention, Figure 5 is a schematic circuit diagram showing a conventional example, and Figure 6 shows current characteristics of the conventional example. It is a diagram. (2)...Power switch, Uυ...Power MO8, FET. (9,10)...08 of power MOS/FET
A means of applying a voltage that gradually increases after the power is turned on between ■
, ■, ■... Current characteristics of conventional example, ■...
- Current characteristics according to the present invention.
Claims (1)
発生する経路に直列に接続されたパワーＭＯＳ・ＦＥＴ
と、 電源投入と共に徐々に上昇する電圧を上記パワーＭＯＳ
・ＦＥＴのゲート・ソース間に印加する手段とを具え、 電源投入後定常電流に移行するまでの間に上記経路に流
れる電流を緩やかに変化させるようにした突入電流防止
回路。[Claims] A power MOS/FET connected in series to a path where an inrush current occurs until the current changes to a steady state when the power is turned on.
Then, the voltage that gradually increases as the power is turned on is applied to the power MOS described above.
- An inrush current prevention circuit that includes means for applying voltage between the gate and source of the FET, and that gradually changes the current flowing through the above path after power is turned on until the current changes to a steady state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9357687A JPS63260220A (en) | 1987-04-16 | 1987-04-16 | Rush current preventing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9357687A JPS63260220A (en) | 1987-04-16 | 1987-04-16 | Rush current preventing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63260220A true JPS63260220A (en) | 1988-10-27 |
Family
ID=14086091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9357687A Pending JPS63260220A (en) | 1987-04-16 | 1987-04-16 | Rush current preventing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63260220A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555883B1 (en) * | 2001-10-29 | 2003-04-29 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
| JP2007035027A (en) * | 2005-07-22 | 2007-02-08 | Taida Electronic Ind Co Ltd | Power supply monitoring apparatus for fan |
| JP2007215300A (en) * | 2006-02-08 | 2007-08-23 | Toshiba Tec Corp | Power supply |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148321A (en) * | 1979-05-01 | 1980-11-18 | Ch Polt I | Dc circuit switching device |
| JPS57159126A (en) * | 1981-03-05 | 1982-10-01 | Siemens Ag | Drive circuit for power field effect switching transistor |
-
1987
- 1987-04-16 JP JP9357687A patent/JPS63260220A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148321A (en) * | 1979-05-01 | 1980-11-18 | Ch Polt I | Dc circuit switching device |
| JPS57159126A (en) * | 1981-03-05 | 1982-10-01 | Siemens Ag | Drive circuit for power field effect switching transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555883B1 (en) * | 2001-10-29 | 2003-04-29 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
| JP2007035027A (en) * | 2005-07-22 | 2007-02-08 | Taida Electronic Ind Co Ltd | Power supply monitoring apparatus for fan |
| JP4532444B2 (en) * | 2005-07-22 | 2010-08-25 | 台達電子工業股▲ふん▼有限公司 | Fan power monitoring device |
| JP2007215300A (en) * | 2006-02-08 | 2007-08-23 | Toshiba Tec Corp | Power supply |
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