JPS63260038A - Flattening of layer insulation film - Google Patents

Abstract

PURPOSE:To lessen damage to a leveled film and obtain a favorable step coverage of an upper layer interconnection and the like by controlling a heat treatment of a rotating application glass film to a glass layer containing impurities having a prescribed impurity concentration and by performing wet etching after controlling an etching speed for both the glass layer and film. CONSTITUTION:A lower layer interconnection is formed of polysilicon on a substrate 1 and steps 3 are formed. Then, a glass layer (PSG) 4 containing impurities grows uniformly to the whole surface on the steps 3 by a CVD technique. As the effect of steps 3 is reflected, a stepped part 2 is formed due to the glass layer 4 containing the impurities. The stepped part 2 is leveled once by being coated with a spin-on-glass layer (SOG) on its part 2 and PSG and SOG layers are heat-treated at an annealing temperature and are annealed. After having a suitable etching ratio between PSG and SOG, a layer insulation film is leveled by wet etching with hydrofluoric acid.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a planarization method, and more particularly to a planarization method that performs planarization by controlling the etching rate of a step portion and a planarization film.

[Summary of the invention]

The present invention is a planarization method in which a planarizing film is formed on a step portion formed on a substrate and then etched. A spin-coated glass film is formed and flattened, and the impurity-containing glass layer having a predetermined impurity concentration is wet-etched by controlling the heat treatment temperature of the spin-coating glass film to control the etching rate of both. This method causes less damage to the film, is inexpensive, and enables good planarization of step coverage.

[Conventional technology]

In conventional planarization methods, for example, when forming an interlayer insulating film on a lower layer wiring using only a CVD (chemical vapor deposition) film in a multilayer wiring process of a semiconductor device, it is uniformly formed according to the undulations of the steps of the lower layer wiring. As the film grows, the undulations at the stepped portions are not alleviated and unevenness remains on the surface. For this reason, if you try to form a main wiring layer on top of it, the wiring arrangement (coating) becomes poor, and there is a problem that wiring breaks and short circuits are more likely to occur.Recently, interlayer insulation When forming a film that requires planarization, such as a film, use CVD or the like to apply PS on the underlying step.
After forming a G (phosphorus silicate glass) film, SOG (spin glass) is prepared by dissolving Sin, etc. in a solvent such as alcohol.
Planarize the surface using a film (on glass), and then apply RI.
A film having a desired thickness and a flattened surface is formed by uniformly etching back the entire surface using E.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional planarization method, PSG film and SO
A method of flattening the surface using a G film and then uniformly etching back the entire surface using RIE was being explored, but using RIE, which is used for etching, is costly and can damage the film itself. There is a problem in that the dielectric strength is lowered.

On the other hand, in wet etching using dilute hydrofluoric acid, etc., PSG generally has a higher etching rate, so SO
There is a problem in that it is not easy to control the etching rate with G.

SUMMARY OF THE INVENTION An object of the present invention is to provide a planarization method that can solve the above problems.

[Means for solving problems]

In order to solve the above problems, the present invention provides a planarization method in which a flattening film is formed on a step formed on a substrate and then etched. and a step of forming and flattening a spin-coated glass film on the stepped portion, the heat treatment temperature of the spin-coating glass film being controlled for the impurity-containing glass layer having a predetermined impurity concentration. A method is used in which the etching speed of both is controlled and flattening is performed by wet etching.

The planarization method of the present invention will be explained below with reference to FIG.
81(b)(C)(d).

The planarization method of the present invention is a planarization method in which a planarization film is formed on the step portion 2 formed on the substrate 1 and etched, as illustrated in the first answer diagram. Step 3 (FIG. 1(b)) of forming a stepped portion 2 on which a glass layer 4 containing impurities is formed (FIG. 1(a)), and forming a spin-coated glass film 5 on the stepped portion 2. The step of forming and flattening the impurity-containing glass layer 4 having a predetermined impurity concentration is controlled by controlling the heat treatment temperature of the spin-coated glass film 5. The etching rate is appropriately controlled and wet etching is performed to flatten the surface (FIG. 1(d)).

The step portion 2 refers to a step formed by forming the glass layer 4 containing impurities on the step 3 of the substrate 1.

The above impurity-containing glass layer 4 is a glass layer containing appropriate impurities and their concentration, such as PSG (phosphorus silicate glass) or BSG depending on the type of impurity.
(boron/silicate glass), ASSG (arsenic/silicate glass), etc. can be preferably used. Taking the case of PSG as an example, the higher the phosphorus concentration, the higher the etching rate for wet etching.

The spin-coated glass film 5 is a glass film formed by spin-coating, and is called -11R 5OG (spin-on glass), and is coated with 5I in a solvent such as alcohol.
A solution of n1 etc. is used. Since the SOG is applied by spin, the SOG can enter into the recesses on the surface and flatten the surface. According to the findings of the present inventors, it has been found that the etching rate of this SOG with respect to wet etching increases as the temperature of the annealing treatment performed after application of the SOG is lower.

In this way, the present invention provides a glass layer 4 containing impurities (
For example, planarization is achieved by controlling the etching rates for wet etching of PSG) and spin coating glass film 5 (SOG), but such a method has not been used in the past.

The wet etching for planarization can be performed using, for example, a solution prepared by diluting hydrofluoric acid with water in an appropriate proportion.

[Effect]

As described above, the present invention controls the heat treatment temperature of the spin-coated glass film 5 formed on the stepped portion 2 to increase the etching rate of the glass layer 4 containing impurities having a predetermined impurity concentration. Since the planarization is performed by wet etching in this manner, it is possible to avoid damage when using RIE, etc., and to obtain a planarization film of stable quality at a low cost. Therefore, a good step cover arrangement can be obtained.

〔Example〕

Hereinafter, one embodiment of the planarization method of the present invention will be described in detail with reference to FIG. It should be noted that, as a matter of course, the following example shows an example of the present invention, and the present invention is not limited only to this example.

FIGS. 1(a) to (d) are cross-sectional views showing the planarization process of this example, and FIG. 2 is a PS in wet etching.
FIG. 3 is a diagram showing the correlation between G and SOG etching rates.

In this example, the planarization method of the present invention is applied to the formation of a planarized interlayer insulating film in a multilayer wiring process of MOS LSI.

In this embodiment, as shown in FIG. 1 (al), a lower layer wiring is formed of polysilicon on a substrate 1. This forms a step 3.

Next, as shown in FIG.
(using SG) 4 is grown uniformly over the entire surface by CVD. In this way, a step portion 2 is formed by the glass layer 4 containing impurities, reflecting the step 3.

Next, as shown in FIG. 1 (C1), a spin coated glass film (SOG) 5 is coated on the stepped portion 2 and once flattened, the PSG and SOG are heat treated at an annealing temperature of about 850° C. and baked to harden. The etching rates of PSG and SOG in this state are as shown in the following table (pure 5i02 is also shown for comparison).

In the table above, the etching solution used in this example was diluted with water at a ratio of 5 parts to 100 parts of a commercially available hydronic acid solution, and SOG was OCD manufactured by Tokyo Ohka;
5t-40310 was used, and the annealing time was 30 minutes.

In this example, the annealing temperature was 850°C, and as shown in the table above, the etching rate was 1400 etching/win for the PSG film with a phosphorus concentration of 5.2% and 1100 etching for the SOG film.
Human/win and almost 1: Slightly PS based on process level
The etching rate of the G film is increased. This is to correct and flatten the raised shape of the stepped portion 2 of the PSG film as seen in FIG. 1(C).

Figure 2 shows the PSG of the table above, ! = This is a graph of the SOG relationship, but only the phosphorus concentration of PSG is 5.2%
As can be understood from the dashed line showing the state of moving back and forth from
In this example, the etching rate ratio between the two was approximately 1:process, but it is possible to select an appropriate etching rate ratio by changing the annealing temperature and the phosphorus concentration of PSG depending on the desired etching shape. be. In the present invention, "flattening" broadly means obtaining a desired shape by changing the etching rate ratio, and is not limited to strict flattening.

As described above, the interlayer insulating film could be planarized by wet etching with hydrofluoric acid at an appropriate etching rate ratio of 4 between PSG and SOG. Unlike the planarization method using RIE, this method does not damage the glabellar insulating film and can be realized at low cost. The planarized interlayer insulating film thus obtained has good step coverage and is therefore suitable for forming upper layer wiring. Furthermore, if an aluminum wiring or the like is formed on an uneven interlayer insulating film, etc., the patterned shape of the resist will be distorted. According to the flattening method, it is not necessary to use these.

Although this embodiment has described a planarization method in a multilayer wiring process for MOS LSI, it goes without saying that it can also be used in manufacturing processes for bipolar LSI and other semiconductor devices.

〔Effect of the invention〕

As described above, the planarization method of the present invention causes less damage to the planarization film, and can perform planarization at low cost and with high reliability. I was able to make it good.

[Brief explanation of the drawing]

Figures 1 (al to d) are cross-sectional views showing the planarization process of this example, and Figure 2 is a PS in wet etching.
FIG. 3 is a diagram showing the correlation between G and SOG etching rates. 1...Substrate, 2...Step portion, 3...Step (lower layer wiring), 4...Glass layer containing impurities, 5...Rotation Coated glass membrane.

Claims (1)

[Claims] A planarization method in which a planarization film is formed on a step formed on a substrate and etched, comprising: forming a step in which a glass layer containing an impurity is formed on the step; forming and flattening a spin-coated glass film on the stepped portion; and controlling the heat treatment temperature of the spin-coating glass film on the impurity-containing glass layer having a predetermined impurity concentration to increase the etching rate of both. A planarization method characterized by controlling wet etching and planarization.