JPS63257841A - Logic simulator - Google Patents

Abstract

PURPOSE:To attain high speed simulation with less hardware by using each information in a memory so as to calculate the output state of a basic function element, comparing the result with a preceding value so as to detect an event and applying the similar processing as to the succeeding element. CONSTITUTION:An input value of elements 2-1-2-3, an effective bit and its attribute are red respectively from an effective bit and attribute memory 100 and an input signal storage memory 210 and the result is calculated in an logic arithmetic circuit 300. The result is fetched in a register 400 and compared with a preceding value in an output status memory 500. Since the both preceding values was, X, the output change after simulation takes place and an event detection circuit 500 detects an event. The elements connected to the elements 2-1-2-3 are found out from a connection memory 700 and the element 3-1, 3-2 are used as the object of simulation of the next level. When the processing of level 2 is finished, the element of level 3 is simulated and when the element of simulation is finished for the final level, the simulation of one test data is completed. The next pattern is conducted similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic simulator, and more particularly to a high-speed logic simulator using hardware.

Prior Art Conventionally, this type of logic simulator was usually created using software (for example, T, 5asaki e
tal, ``Old xS; to Mixed Level
Simulator for large Digit
al System Logic Veriri
ca mouth”.

Proc, of 17th Design Auto
mat, Conf,, PP, 626-633, J
une 1980. ) With such conventional software-based logic simulators, when there is a large amount of test data for simulation (when the number of simulation clocks is large), the simulation execution time increases, which poses a major problem in terms of ensuring design quality. ing.

Therefore, the present invention was made to solve the drawbacks of the conventional methods, and its purpose is to perform logic simulations at high speed even when there is a large amount of test data for simulation. The object of the present invention is to provide a logic simulator with a hardware configuration that allows for

Composition of the Invention The logic simulator according to the present invention is a logic simulator that performs logic simulation of a logic circuit consisting of a plurality of basic functional elements, and includes mutual connection state information of the basic functional elements and input signals of each of the basic functional elements. A memory means that stores in advance element attribute information indicating logical values and types of functions, and input signal logic corresponding to these basic functional elements from the memory means for a predetermined number of basic functional elements among the basic functional elements. logical operation means for deriving values and element attribute information respectively and performing simulation processing in parallel;
An output state memory means for storing the previous processing result by the logic operation means compares the previous processing result of the output state memory means with the latest processing result of the logic operation means, and detects that there is a change. searching means for searching other basic functional elements connected to each basic functional element currently being simulated using the connection state information when the basic functional element is currently being simulated; It is characterized in that the following simulation processing is performed on the element.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
A) is a diagram showing a simulated logic circuit to be subjected to logic simulation by the logic simulator shown in the blocks of FIG. FIG. 2 (B) is a logic circuit diagram obtained by converting all the logic circuits shown in FIG. In the logic simulator shown in FIG. 1, the logic circuit constituted by the four human-powered basic functional elements shown in FIG. 2(B) is treated as a logic circuit to be simulated.

In Fig. 1, as shown in Fig. 2 (B), the effective bits (4
Bits indicating whether or not the human input signal line is actually used) and the type of function of each basic functional element (element attributes indicating functions such as AND gate, OR gate, etc.) are stored in memory 100 in advance for each basic functional element. is stored within.

The signal logic values of the respective input signal lines of each basic functional element are stored in temporary memories 210 and 220, and the selector 20
1, the data stored in both memories 210 and 220 is alternatively derived and input to the logic operation circuit 300, and in this logic operation circuit 300, the valid bit of each basic functional element stored in the previous memory 100 is determined. Logic simulation is performed using the element attribute data and the input signal logic value selected by the selector 201.

The results of the logic simulation performed in this logic operation circuit 300 are temporarily stored in the register 400. This stored logical operation result is combined with the contents of the output state memory 500 storing the previous logical operation result and the event detection circuit 6.
00 is compared. As a result of this comparison, if it is determined that there has been a change, it means that an event has occurred, so
Based on the logic circuit connection data stored in the connection state memory 700 in advance, other basic functional elements connected to the output of the basic functional element currently being simulated are searched. Input signal values and events for each basic functional element are stored in memory 800 in advance, and input state values corresponding to the searched basic functional element are read from memory 800 and temporarily stored in memories 210 and 220. It has become.

Next, the present invention will be explained in detail. First, before the simulation starts, the valid bits of the input signal lines of each basic functional element and the attributes of the basic functional element are stored in advance in the memory 100 corresponding to these basic functional elements, and the basic function is shown in FIG. The storage state of these data corresponding to the elements 2-1 to 2-5, respectively, is shown.

For example, in 2-1, the upper four bits indicate valid bits, and the lower three bits indicate attributes. Of the top 4 bits, “
1pa indicates that the input signal is supplied from the previous stage,
II OII indicates that there is no connection from the previous stage and a fixed value (clamp value) is entered. The upper 2 bits of the lower 3 bits indicate the function of the element (in this example, "o o" is an AND gate, and 01 is an OR gate. 11 i Q 1
1 indicates EXOR gate), and the remaining 1 bit distinguishes between positive and negative [“O” is positive.

“1 pa is no (reversed)” is shown.

The output state memory 500 stores the initial states (
For example, II X I + undetermined) is included. Further, the connection state memory 700 stores the connection relationships of all basic functional elements. The memory 800 contains event information for performing simulations and input states of basic functional elements. Before the simulation behavior is driven,
The basic functional element connected to the primary input becomes an event. As shown in FIG. 2(B), levels are assigned to the circuit to be simulated from the primary input to the output, and the simulation is performed for each level. In this example, it is assumed that the logical operation circuit 300 can execute simulations for three basic functional elements in parallel.

The simulation is performed as follows. Assuming level 2 is the simulation target, memory 8
00, the input values of the basic functional elements 2-1 to 2-3 belonging to level 2 are stored in the memory 210, and the input values of the basic functional elements 2-1 to 2-3 belonging to level 2 are stored in the memory 220.
Input values of -4 and 2-5 are sent, respectively. At this time, the clamp value is input to the clamp signal line.

The simulation is performed using the element 2-1゜2- from the memory 210.
The input values of elements 2 and 2-3 are transferred from the memory 100 to element 2-
The valid bits 1.2-2 and 2-3 and their attributes are respectively read out and calculated by the logic operation circuit 300.

In this example, the result is (0, 1, 0), which is loaded into the register 400. The value in register 400 is compared to the previous value in memory 500. In this example, since the previous elements 2-1, 2-2 and 2-3 were both 'X'', an output change occurred after the simulation, and an event occurred in the event detection circuit 600. be done. At this time, the elements connected to each element 2-1, 2-2, and 2-3 are searched from the connection state memory 700, and the element 3
-1.3-2 is the next level simulation target element.

On the other hand, the selector 201 switches its input after a certain period of time, reads out data from the memory 220, and reads the data from the memory 100.
The elements 2-4 and 2-5 are read out from the logic operation circuit 3.
00 and continue the same process.

When level 2 processing is completed, the elements belonging to level 3 are simulated, and when the final level is completed, the simulation for one test data is completed. The next pattern is also executed using the same procedure.

Effects of the Invention As described above, according to the present invention, a memory is provided in which connection state information, input state value information, element attribute information, etc. of basic functional elements constituting a logic circuit to be simulated are stored in advance. Calculate the output state of the basic functional element using each information,
By comparing this calculation result with the previous output state value, an event is detected and the same process is performed for the next basic functional element, making it possible to perform logic simulations at high speed with less hardware. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a simulated logic circuit to be subjected to logic simulation, and FIG. 3 is an example of memory contents at an operation stage in the block of FIG. 1. FIG. Explanation of symbols of main parts 100... Valid bit and attribute storage memory 210, 220... Input signal value storage memory 3
00...Logic operation circuit 400...Register

Claims (1)

[Claims] A logic simulator that performs logic simulation of a logic circuit consisting of a plurality of basic functional elements, the element attribute indicating mutual connection state information of the basic functional elements, input signal logic value of each of the basic functional elements, and type of function. Deriving input signal logic values and element attribute information corresponding to these basic functional elements from the memory means for a predetermined number of basic functional elements among the basic functional elements and a memory means in which information is stored in advance, respectively. A logic operation means for performing simulation processing in parallel, an output state memory means for storing the previous processing result of the logic operation means, and a previous processing result of the output state memory means and the latest processing result of the logic operation means. searching means for searching for other basic functional elements connected to each basic functional element currently being simulated using the connection state information when a change is detected; 1. A logic simulator characterized in that the following simulation processing is performed on the basic functional element searched by the search means.