JPS63253992A - Driving circuit for liquid crystal optical shutter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a recording device using a liquid crystal optical shutter, and more particularly to a driving circuit for driving the liquid crystal optical shutter.

[Prior art and its problems]

The liquid crystal optical shutter is composed of a large number of microshutters arranged in the main scanning direction of the photoreceptor, and by selectively opening and closing the microshutters, an electrostatic latent image in the form of dots is formed on the photoreceptor. The number of micro-shutters is determined by the printing density; for example, in the case of 10 dots/11 and printing on A3 size paper, 3000 micro-shutters are required in the main scanning direction. If such a large-capacity microshutter is statically driven, the number of driving elements, the number of wiring lines, the mounting area, etc. will increase, and the device will not only become expensive. It is also difficult to implement.

Therefore, liquid crystal optical shutters are generally driven by a time-division driving method.

The drive circuit that drives this liquid crystal optical shutter in a time-division manner is the LS
A control signal for selectively opening and closing each micro-shutter of the liquid crystal optical shutter is output from the drive circuit L$I output bin to each micro-shutter ρ signal electrode.

Therefore, by increasing the number of pins in the drive circuit LSI and increasing the number of output pins for signals that drive signal electrodes, the drive circuit LS used can be
The number of Is can be reduced, and costs can be reduced. Furthermore, when mounting the drive circuit LSI chip, if it can be mounted thinly, it becomes possible to make the print head of a recording device comprising a liquid crystal optical shutter and a drive circuit LSI smaller and thinner.

For this reason, recently, drive circuit LSIs are suitable for multi-bin design, and TAB (Tape Auto-mate
It is mounted on a film tape using the d Bonding method. Mounting using the TAB method has the advantage that it is easy to automate the mounting, that it can be thoroughly tested before mounting, and if the chip is defective, it can be replaced (correctable).

However, when increasing the number of pins, the distance between the bonding baths of the driving LSI chip becomes narrower, so the outer lead distance also becomes very narrow (for example, 0.15n+).
When checking chip operation using an IC tester,
It is not possible to test by bringing the probe needle into contact with all the outer leads at once, and therefore the test must be carried out several times, resulting in poor operational efficiency.

Conversely, in order to improve the work efficiency of operation checks,
If terminal connections are made using the TAB method with outer lead spacing within the range that can be tested at one time with an IC tester, the problem arises that the number of drive LSI chips used increases because the number of output pins inevitably decreases. Ta.

[Purpose of the invention]

In view of the above-mentioned conventional drawbacks, the present invention provides a driving circuit for a liquid crystal optical shutter consisting of an LSI chip terminal-connected by the TAB method, which allows easy operation checking even if the outer lead spacing is very narrow, and allows for a large number of pins. The purpose is to

[Key points of the invention]

In order to achieve the above object, the present invention seals a liquid crystal substance between two glass substrates, provides a plurality of scanning electrodes on one glass substrate, provides a plurality of signal electrodes on the other glass substrate, and provides a liquid crystal substance between two glass substrates. In a drive circuit for a liquid crystal light shutter that drives a plurality of shutters formed at intersections of the shutters, the drive circuit includes a shift register that serially inputs opening/closing data for opening and closing the shutters and outputs it in parallel; An LSI chip is connected to an external lead terminal on the film, and has a delay means for delaying some output data, a storage means for storing the output of the delay means, and a buffer for inputting the output of the storage means. The output of the buffer is taken out of the chip by the external lead terminal, and the number of external lead terminals is small (all of them are connected to one test terminal).

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, a liquid crystal printer according to the present invention will be explained.

FIG. 15 shows a schematic configuration diagram of the liquid crystal printer.

In FIG. 15, 1 is a drum-shaped photoreceptor, which rotates at a constant speed in the direction shown. The surface of the photoreceptor 1 is charged in advance by a charger 2, and then optical writing is performed by a print head 3 using a liquid crystal optical shutter. The print head 3 is driven by a recording control section 4 having a drive circuit, which will be described later, and selectively opens and closes individual microshutters constituting the liquid crystal light shutter according to a video signal (recorded data), thereby creating a dot structure on the photoreceptor 1. Forms an electrostatic latent image.

This latent image is visualized using toner by a developing device 5,
A toner image is formed on the photoreceptor 1. Further, the transfer paper 6 is fed by a paper feed roll 7, synchronized by a standby roll 8 so that the leading edge of the transfer paper 6 and the leading edge of the above-mentioned toner image coincide with each other, and then transferred by a transfer device 9. The toner image is transferred onto the paper 6.

In the transfer unit 6, a toner image is transferred at a separation unit 10.

The transfer paper 6 is separated from the photoreceptor 1 in a separating section 10, thermally fixed in a fixing device 1 whose temperature is controlled to a constant temperature by a thermistor lla and a fixing heater llb, and carried out of the machine by a paper discharge roll 12. . On the other hand, since the toner that was not completely transferred by the transfer device 9 remains on the surface of the photoreceptor 1, after the residual toner is removed by the static eliminator 13, the cleaning unit 1
After the surface of the photoreceptor 1 is cleaned by the photoreceptor 4 and the surface of the photoreceptor 1 is neutralized by the eraser 15, a uniform charge is again applied to the surface of the photoreceptor 1 by the charger 2 in preparation for the next exposure.

As shown in FIG. 16, the printing gutter 3 includes a light source 16, a light source heater 17, a liquid crystal light shank 18, and a liquid crystal heater 1.
9. It mainly consists of control boards 21a and 21b on which an imaging lens 20 and an LSI described later are mounted. A fluorescent lamp is used as the light source 16, and a thermistor 22 for detecting the temperature of the light source heater 17 is attached to one end of the light source heater 17.

The liquid crystal light shank 18 is controlled by two-time division driving as shown in FIG. 17, and is of a guest-host type. A liquid crystal mixture is sealed between two glass substrates 23 and 24, and The substrate 23 is provided with signal electrodes 25 alternately, and the glass substrate 24 is provided with a common electrode 26. The micro-shutter 27 is formed of a transparent electrode made of indium (InzOi), tin oxide (SnO□), etc., with a necessary size and a necessary shape at the intersection of the signal electrode 25 and the common electrode 26. At least one polarizing plate and a liquid crystal heater 19 are provided on the liquid crystal panel configured as described above.
The liquid crystal optical shutter 18 is configured by arranging the liquid crystal light shutter 18. In addition, the liquid crystal light shank 18 also has a liquid crystal light shutter 18.
A thermistor (not shown) is attached to detect the temperature of.

Optical writing on the photoreceptor 1 is performed using a signal electrode 25 and a common electrode 26.
By applying a drive signal from the control boards 21a and 21b to each micro shutter 27 of the liquid crystal optical shutter 18
This is performed by controlling the opening and closing of the micro-shutter 27 and irradiating the surface of the photoreceptor 1 with light from the light source 16 that has passed through the micro-shutter 27 in the open state.

FIG. 1 shows a drive circuit for a liquid crystal light shutter according to the present invention, and shows a duty A two-frequency drive liquid crystal light shutter drive circuit. Note that the circuit shown in Figure 1 is C
It is a block diagram of an LSI circuit configured by an MO3 circuit, and the circuit shown as 30 in the figure is the entire circuit of one LSI.

This LSI can be connected in cascade in the same way as in the past, so by using a plurality of these LSIs, all the micro shutters can be driven.

Furthermore, if the circuit shown as 40 in the figure is one channel, one LSI has N channel circuits.

The 1 channel circuit 40 is a video signal (recorded data)
Shift register section 41-1.41-2 for taking in
, a delay section 42-1 and 42-2 that delay data from the shift register section 41-2, a data launch section 43-1 and a delay section 42 that latch the video signal output from the shift register section 41-1. -2 has a data latch section 43-2 that latches the video signal output from the LCD light shutter 18;
It also has a level shifter 45 and a high pressure resistant cover sofa 46.

The circuit configuration of the shift register section 41-1.4 knee 2 is shown in FIG. figure(
b), the circuit configuration of the data selector modulation section 44 is shown in Figure 2 (
The circuit configuration of the level shifter 45 is shown in FIG. 2(d).

The level shifter 45 has VSS/
Convert the VDD logic level to the V, /VIllD logic level. Hereinafter, the V3S/VDDO logic level will be referred to as "θ"/"1", and the v■/VDIll logic level will be referred to as "L"/"H".

The data selector modulation section 44 also includes an inverter 81 .
The drive signal PTI is sent to the inverters 83 and 84 through 82.
A drive signal PT2 is input from the outside via the inverter 85, a select signal DSEL is input via the inverter 85, and a select signal DSEL is input via the inverters 85 and 86.

As is known from the circuit configuration shown in FIG. 2 (tc), the data selector modulator 44 selects the A input when the select signal DSEL is "0", and when the A input is "1", the drive signal P
If the A input is "0", the inverted signal PTI of TI is outputted from the terminal W to the level shifter 45 as an inverted signal T2 of the drive signal PT2.

Also, when the select signal DSEL is "1", the B input is selected, and if the B input is "1", the inverted signal PTI of the drive signal PT1 is sent, and if the B input is "10", the inverted signal PT2 of the drive signal PT2 is selected. is output from terminal W to level shifter 45.

The latch pulse generator 50 also generates three-phase latch pulses CK21, CK22, and CK23, and sends the latch pulse CK21 to the data latch unit 43-2.
This is a circuit that outputs K22 and CK23 to the delay control section 60 (described later), and is a circuit that outputs the select signal D input from the outside.
SEL is inputted to the input terminal (2) of the flip-flop 51-1 via inverters 85 and 86, and a launch pulse CK2 is also inputted to the inverter 53 from the outside.

Furthermore, to explain the internal configuration in detail, the output of the inverter 53 (launch pulse CK2) is transferred to the inverter 54,
It is input to the terminal φ of the NAND gate 52-1.5.2-2.52-3 and the flip-flop 51-1.51-2.51-3, and the flip-flop 51-1.51-2.
52-3 are connected in cascade. In addition, the outputs from the terminals X of the flip-flops 51-1, 51-2.51-3 are respectively
It is input in 2-3. Nantes Gate 52-1.52-
2.52-3, the output (CK2) of the in-hark 53 is "1", and the flip-flop 51-1.51-2.
When the output from terminal X of 51-3 is 1'', launch pulses CK21, CK22, and CK23 are output, respectively.

Furthermore, the latch pulse CK21 output from the Nant gate 52-1 is input to the terminal φ of the data latch unit 43-1, 43-2 via the inverter 89, 90.

Next, the delay control section 60 controls the launch pulse generation section 50
The latch pulses CK22, CK23 from the Nant gate 52-2, 52-3, and the test control unit 70 (described later)
Test signals T1, T2 from outside, test control signal T from outside
A control unit which inputs H, generates clock signals φ2 and φ3, and supplies the clock signals φ2 and φ3 to the delay parts 42-1 and 42-2 in the circuit 40 via inverters 87 and 88, respectively, By controlling the clock signals φ2 and φ3, the delay time interval until the video signal output from the shift register section 41-2 is input to the data launch section 43-2 is controlled. To explain the configuration of the delay control section 60, the output of an inverter 61 to which a test control signal TH is input from the outside is input to Nant gates 63 and 64 via an inverter 62. Nantes Gate 63.
Further, the test signals T2 and T1 output from the test control section 70 are input to 64, respectively. Furthermore, the pulse signal CK22 output from the latch pulse generator 50 and the output of the Nant gate 63 are input to the Nant gate 65, and the clock signal φ2 is output from the Nant gate 65 to the inverter 87. In addition, the pulse signal CK23 output from the latch pulse generator 50 to the Nant gate 66
The output of the Nandts gate 64 is input thereto, and the clock signal φ3 is outputted from the Nandts gate 66 to the inverter 88.

Next, the test control unit 70 controls the high pressure output cover, the 7th floor 46
Gate signals G, , G, , Gz, Ga that control the output of
It is a control unit that generates the gate signals G+, G based on test control signals TG, Tl, and T2 input from the outside.
z, G3, and G4 are generated. Test control section 70
To explain the configuration, a test control signal TG inputted from the outside is passed through inverters 71, 72 to
-1.74-2.74-3.74-4 is input,
By setting the test control signal TG to "l" from the outside, the Nantes gate 73-1.73-2.73-3.73-
4 output is Nantes Gate 74-1.74-2.74-3
．． 74-4 and level shifter 75-1.7 respectively.
Enter 5-2.75-3.75-4. The circuit configuration of the level shifter 75-1.75-2.75-3.75-4 is similar to that of the level shifter 45, as shown in FIG. 2 1d). Then, the logic level of Vss/vI, I is converted to the logic level of VEE/V on. Further, a test control signal T1 is input from an external terminal to an inverter 76, and an output of the inverter 76 is input to an inverter 77 and a Nant gate 73-1.73-3. The output of the inverter 77 is the Nant gate 7
3-2.73-4 and the delay control section 60 is input to the Nant gate 64. Furthermore, a test control signal T2 is input to the inverter 78 from an external terminal, the output of the inverter 78 is input to the Nant gates 73-1 and 73-2 and the inverter 79, and the output of the inverter 79 is input to the Nant gate 73-1, 73-2 and the inverter 79. 3.73-4 and delay control section 6
It is input to the Nantes gate 63 of 0. Further, a video signal is inputted from the external terminal D1 to the input terminal I of the shift register 41-2 via inverters 91.92, and a clock pulse CKI inputted from the outside is inputted to the inverter 93.92.
94 to the terminal φ of the shift register 41-1, 41-2.

Next, the operation of the drive circuit 30 configured as described above will be explained as follows.
This will be explained with reference to the timing chart shown in FIG.

The video signal is as shown in FIG. 3(f) and as shown in FIG. 3(e).
The clock pulse CK is serially input to the terminal D1 in synchronization with the rising edge of the clock pulse CKI shown in
In synchronization with the falling edge of I, the video signal shown in gl in the same figure is taken into the shift register 41-2 of the first stage circuit 40. In synchronization with the write synchronization signal shown in the figure, the transfer permission signal shown in FIG.
A latch pulse CK2 shown in FIG. 3(1)) is input. A plurality of latch pulses CK2 are input during time T,
The latch pulse generator 50 generates three launch pulses CK21 in response to the data select signal DSEL shown in FIG. 3(d).
, CK22, and CK23.

That is, when the latch pulse CK2 shown in FIG. 4 (C1) is input, the data select signal DSEL shown in FIG.
-1.51-2.51-3, the pulse signals a, b, c whose phases are sequentially shifted as shown in (d) to (fl) in the same figure.
is output. These pulse signals a and bSc are applied to each Nant gate 52-1.52-2.5 of the latch pulse generation section 50.
2-3, the timing is further shifted, and the time T, after one line of video signal is captured.
Afterwards, the first latch pulse CK21 is output. Therefore, as shown in FIGS. 4(g) to (1), each Nant gate 52-1.52-2.52 of the launch pulse generating section
-Latch pulses CK21SCK22, CK2 sequentially from -3
3 is output.

Here, a configuration example of the liquid crystal optical shutter 18 using two-time division driving is shown in FIGS. 5(al, (b), (C), <di).

In the same figure, the signal electrode 10 is similar to FIG. 17 described above.
A micro shutter 103 is formed at the intersection of the common electrodes 102-1 and 102-2. Furthermore, the two common electrodes 102-1 and 102-2 are electrically insulated by the insulating section 104. In the configuration of one liquid crystal light shutter 18, the interval between horizontally adjacent microshutters 103, that is, 1
Between the dot interval DOP and the arrangement interval LP of the micro-shutter 103 in the by-product scanning direction, LP=(m+1/2)xDOP-・-(1-1)(m
=0.1.2.3, ...) must be satisfied.

FIGS. 5A, BL, and C1 are diagrams showing the arrangement of the micro shutter 103 in the liquid crystal optical shutter 18 when m=2.1.0 in equation (1-1), respectively. As is clear from FIG. 5, the maximum aperture width WA in the sub-scanning direction is WA and LP+DOP''=(m+1/2)XDOP+DOP-, (m+1.
5) It can be expressed as X Do P ------(1-2).

In forming the liquid crystal light shutter 18, the larger the value of m shown in equation (1-1), the more the signal electrode 101 and the common electrode 102.
-1.102-2 patterning becomes easier, but when the value of m is increased, the maximum aperture width WA increases as can be seen from equation (1-2), and the optical System (lens) (imaging lens 20 shown in FIG.
etc.), a wide-angle lens is required.

There are two methods of drawing out the signal electrode 101 in the liquid crystal optical shank 18: drawing out on one side and drawing out on both sides. This is an example in which the signal electrode 101 is formed by a drawing method.

When the signal electrode is formed by drawing out one side, the difference between the signal electrode drawing interval sp and the 1-dot interval DOP is 5P=2XDOP.
・-(1-3) On the other hand, when the signal electrode is formed by drawing out both sides, 5P=4XDOP −・・−−−1−・・・・・・・−・
There is a relationship (1-4).

When controlling the opening and closing of each micro-shutter 103 of the liquid crystal optical shutter 18 by two-time division driving, even-numbered bits of the video signal are delayed depending on the size of the arrangement interval LP of the micro-shutters 103 in the sub-scanning direction. It is necessary to control time.

The method of controlling the delay time according to this embodiment will be explained below.

When driving the liquid crystal optical shutter 18 shown in FIG. 5 (al) in which the micro shutters 103 are arranged at the arrangement interval LP where m=2 in equation (1-1), the output from the shift register section 41-2 is The even-numbered bits of the video signal output from the shift register section 41-1 are shifted to the odd-numbered bits of the video signal outputted from the shift register section 41-1 through the delay sections 42-1 and 42-2.
The data is delayed by bits and output to the data latch section 43-2, and the opening/closing control of the micro shutter 103 is performed.

In this embodiment, a liquid crystal display device in which microshanks 103 are arranged at an arrangement interval LP of m=2.1 and O in formula (1-1), respectively, as shown in FIGS. 5(a), (b), and (C) Both optical shutters 18 are driven by an external control signal T.
This is possible by controlling 1, T2, and TH. Hereinafter, a method of driving the liquid crystal optical shutter of this embodiment according to the arrangement interval LP of the micro shutter 103 will be explained.

(When driving a liquid crystal optical shutter in which micro shutters 103 are arranged at an interval LP of m=2 as shown in FIG. 5(a)) At this time, TH is set to "0". Then, Nantes Gate 6
3.64 output is always 1", latch pulse CK2
2, CK23 passes through the Nantes gate 65 and 66 and enters the terminal stone and stone of Dere part 42-2 and 42-1, respectively. Therefore, the even bits of the video signal output from the shift register section 41-2 are
Two lines of odd bits of the video signal outputted from 1-1 are sent and input to the data launch section 43-2.

In the two-time division drive, optical writing of odd numbered bits is performed in the first half of the period T shown in FIG. 3, and optical writing of even numbered bits is performed in the second half of the period T. Optical writing of bits is 2.5 for odd bits.
This is done with a delay of one line. During this delay time of 2.5 lines, the photoreceptor 1 moves in the sub-scanning direction by a distance equal to the micro-shutter arrangement interval LP, and correct optical writing corresponding to the video signal is performed.

(Liquid crystal optical shutter 1 in which micro-shutters 103 are arranged at an arrangement interval LP of m=1 shown in FIG. 5 (bl, (dl)
In this case, TH is set to "1" and one of T1 and T2 is set to "1". If only TI is set to "1", the output of the Nant gate 64 will always be 10, and the clock pulse GK23 will not be able to pass through the Nant gate 66. Therefore, the terminal stone of the delay part 42-1 will always have an "O" output. '' is input, and the even-numbered bit data of the video signal input to the terminal I of the delay section 42-1 is outputted as it is from the terminal X to the terminal I of the delay section 42-2 without delay.

Similarly, TH is set to 1", and only T2 in T1.TzO is set to "
1'', the delay of the delay part 42-2 is eliminated.

In this way, by setting TH to "1" and setting only one of T1 and T2 to "1", the even numbered bits of the video signal are delayed by one line with respect to the odd numbered bits of the video signal. The data can be input to the data latch section 43-2. Then, during the delay time of 1.5 lines, the photoreceptor 1 moves in the sub-scanning direction by a distance of the micro-shutter arrangement interval LP shown in FIG. 5 (bl, (dl).

(When driving the liquid crystal optical shutter 18 in which the micro shutter 103 is arranged at the arrangement interval LP of m=Q shown in FIG. 5(C)) In this case, all of TH, TI and T2 are set to "1". do. As mentioned above, TH=T I =T2'=“1”
In this case, the delay caused by the delay part 42-1 and the delay part 42-2 is eliminated, so the even-numbered bits of the video signal are
The data is optically written on the photoreceptor 1 with a delay of 0.5 line with respect to odd bits.

During this 0.5 line delay time, the photoreceptor 1 moves by a distance LP shown in FIG. 5(C) in the sub-scanning direction, so that correct optical writing is performed.

The control signals P1, T2 corresponding to the arrangement interval LP of the micro shutter 103 of the liquid crystal optical shutter 18, explained above,
The method of delay control using TH is summarized in Table 1 below.

Table 1 (-2 indeterminate) As described above, according to this example, in formula (1-1),
It is possible to drive three types of liquid crystal optical shutters 1 and 8 having different arrangement intervals LP of micro shutters 103 where m=o and 1.2.

Incidentally, the number of signal electrodes per print head of a liquid crystal printer, that is, the total number of output channels of the drive circuit LSI of the liquid crystal optical shutter, is determined by the recording width and recording density to be printed. For example, using a liquid crystal optical shutter with duty A and two-division drive as shown in FIG. 5, recording width A4 (or 8 inches) and recording density 240D P
per inch), the number of output channels of the driving LSI for the liquid crystal optical shutter is 210+ in recording width.
+e or 2161, so approximately 1000 pieces are required. In addition, the recording density is 3000 PI on A3 size paper.
When printing, approximately 1700 output channels are required.

Here, the recording widths A4, B4, and A3 are each 240 DPI.
Table 2 below shows the number of drive LSIs (not shown) with conventional IQO pins and 80 channels required when printing at a recording density of 300DPI.

(Margin below) Table 2 As shown in Table 2, recording width B4, recording density 240 DP
When printing with I, 16 driving LSIs are required.
When printing with recording width A3 and recording density 300DPI, 2
Two driving LSIs are required.

In this way, a large number of driving LSIs are connected to each other in FIGS.
Since it is difficult to connect to the signal electrode 101 drawn out on one side as shown in el, the signal electrode 101 was drawn out on both sides and connected to the driving LSI as shown in FIG. 5 (dl). The number of driving LSIs shown in parentheses in Table 2 is required.

In addition, as a method of reducing the number of signal electrodes 101, if the duty ratio is increased and m time division driving is performed, the signal electrodes 101
The number of common electrodes 1 is reduced to 18, but the number of common electrodes 1 is reduced to 18.
02-1.102-2 also increases, and as a result, the number of insulating parts 104 also increases. For this reason, the amount of light leaking from the insulating section 104 increases, causing the light to turn on! /The S/N ratio of the off-light amount decreases, and furthermore, in dynamic drive, the micro shutter 1
The amount of exposure light received by the photoreceptor 1 when the opening of 03 is reduced to 18, resulting in deterioration of print quality.

Therefore, in the present invention, the duty ratio is set to A, the number of channels N shown in FIG.
Connect the external lead terminals using TAB (Tape Auto).
bonding) method. The number of channels N is determined by the recording width and recording density of printing. The optimal number of channels N can be set based on the total number of dots per line, but N = 256.16
Drive LS at each recording width and each recording density when set to 0
The number of I used is shown in Table 3 below.

(Margin below) As shown in Table 3, recording width B4, recording density 240DPI
In the case of printing, the number of 256-channel drive LSIs used is five, which is a reduction of 11 compared to the case of using the conventional 80-channel drive LSI shown in Table 2.

Next, as shown in FIG. 6(a), (bl, and (C), one side of the LSI chip 122 of the drive circuit 30 whose input/output electrodes are connected to external lead terminals by the TAB method is The signal electrode 1- of the liquid crystal light shutter 18 drawn out to
FIG. 3 is a schematic diagram showing the state of connection with Of, and (in the figure) is a sectional view thereof.

First, referring to FIG. 2B, the driving LSI chip 122 is connected to the outer leads 121 formed on the base film 118 by bumps 123, and the outer leads 121 are connected to the signals arranged on the signal board 116. The electrode 112 and the base film 118 are connected at the window 119.

Next, the configuration of the liquid crystal optical shank 18 will be briefly explained.
Common substrate 1 with gap maintained by spacer 117
A liquid crystal mixture 124 is sealed between the signal electrode 14 and the signal substrate 116, and the signal electrode 112 is placed on the common substrate 114 as shown in the figure (
It is formed as shown in a), and common electrodes 111-1 and 111-2 are formed on the common substrate 114. In addition, polarizing plates 113 and 115 are provided on the common substrate 114, respectively.
, are provided on the signal board 116. As shown in FIG. 6 (al), a micro-shutter 110 is formed at the intersection of the signal electrode 112 and the common electrode 111-1, 111-2.

A method of connecting the outer lead 121 formed on the base film 118 by the TAB method to the signal electrode 112 of the liquid crystal optical shutter 18 with the driving LSI chip connected to the outer lead 121 by the bump 123 will be described below. Here, the distance between adjacent signal electrodes 112 is sp, the bonding distance between outer leads 121 (hereinafter referred to as OLB distance) is FP, and the distance between adjacent signal electrodes 121 is FP.
The distance between the outer leads 121 bonded to the terminals at both ends (hereinafter referred to as OLB full width) is FL, and the distance between the outer leads 121 bonded to the terminals at both ends of
The entire length of the base film 118 on which the chip 122 is mounted will be described as FW, the distance between adjacent base films 118 as FTP, and the distance between the outer leads 121 closest to each other between adjacent base films 118 as FTP.

Now, the number of output channels of the driving LSI chip 122 is N.
In this case, FL= (N-1)XFP, and FP=
If it is SP, then FL=(N-1)XSP.

Therefore, if the recording density is 300DPI, N=256 channels, and S P =0.169211, FL is 4.
It becomes 311. Also, the recording density is 240DPI, N=2
If it is 56 channels, FL=54 mm.

In this way, when FL becomes large, FW becomes even larger than FL and FTP cannot be obtained, so it is necessary to mount the drive LSI chip 122 using the TAB method using a general 35 mm base film as described above. becomes impossible.

Therefore, in order to implement the base film of -i 35 dragons by the method, as FP<SP, F
It is necessary to make L as small as possible.

The recording density is set to 2 so that the 256 channel drive LSI chip 122 is connected to the signal electrode 112 of the liquid crystal optical shutter 18.
Parameters FL and F for implementation with the TAB method used for print heads that record at 40DP■ and 300DPI
The values of W and FTP are shown in Table 4 below.

Table 4 N -256, F P = 0.15m■ (Unit: l) As shown in Table 4, by setting the OLB spacing FP to Q, 15m1, the FW becomes approximately 40.25n+, and the effective width is 25m. It became possible to mount the drive LSI: J-tube 122 on the base film 11B with a width of 3511 mm.

In FIG. 7, the input/output terminals of the drive LSI chip 122 are connected to the outer leads 1 on the base film 118 using the TAB method.
21 is shown. In the figure, terminal 14
External input signals TG, Tl, T2, PTI, DS shown at the right end of FIG.
EL, CK2, TH, sD I, CK 1 and power supply VI
ID% vss and VEE are input to the driving LSI chip 122, and again. outputs.

In addition, the drive LSI chip 122 is connected to the collective connection terminal 140.
Channel outputs Y1 to YN are outputted through the outer leads 121 to Yi and Yi. 1.Y. 2.Y. , are input as - pairs.

As shown in the figure, the width WA from the outer lead 121a to the outer lead 121b can be narrowed, and the drive L is mounted on the base film 118 with an effective width of 25 mm using the TAB method.
It became possible to mount the SI chip 122.

When recording at a high recording density such as 480DPI or 600DP1, a method is adopted in which the signal electrodes are drawn out to both sides as shown in FIG. 5(d), and a TAB as shown in FIG. A plurality of drive LSI chips 122 whose outer leads are connected according to this method are arranged, and their outer leads 121 are connected to the signal electrodes 112.

In this way, it is possible to drive liquid crystal optical shutters of various recording densities using the driving LSI chip 122 bonded to the outer lead 121 on the base film 118 with F P =0.150 using the TAB method.

However, the channel output YN of a 256-channel or 160-channel drive LSI implemented using the TAB method is determined by the OLB interval F P =0.1 for each channel.
It is very difficult to accurately check with a jig or tool through the 5 mm outer lead 121.

Hereinafter, a method of checking each channel output YN of the driving LSI chip 122 of the present invention will be explained. Figure 8 (al is
High voltage output buffer 46 and gate signal G1 shown in FIG.
, G2, G3, and G4 in more detail. The high voltage output buffer 46 of each channel includes 46-1.46-2.46-3 in order from the right side to the left side of the drawing.
, . . . are written with consecutive numbers of 46-N. High voltage output buffer 46-1.46~2.46-3.46-4.4
6-5,...46-N have gate signals G1, G2, G3, G4, G1,...G as shown in the same figure (al).
4 enters. Further, the detailed circuit configuration of the high voltage output buffer 46-x is shown in FIG. .2.3.4) is "H", it enters a high impedance (hereinafter referred to as Z) state. Also, G
When y is "L", the yX input becomes the channel output YX and is output from the high voltage output buffer 46-x. In the present invention, the driving LS is
After bonding the input/output terminals of the I chip 122 and the outer leads 121 on the base film 118, (channel output Y2, Y3, Y4), (channel output Y
6, Y6, Yl, ya), (channel output Y,, Y
i (l I,Y,.2,Yi.3),... (
Channel output YN-,, Y, l-z, YN-YN)
The outer leads 121 outputting the output signals are short-circuited as a set of four channel outputs in parentheses, and connected to the collective connection terminal 140 as shown in FIG. Then, the channel output Yi~Y+,z (i=1.5, 9. . .
To check the output of N-3), connect I to each batch connection terminal 140.
This is done by bringing the probe needle 141 of a C tester (not shown) into contact with it.

As a result of the check, the channel output is Y.

~Y8.3 is all normal and the drive LSI chip is found to be good, cut off all the bulk connection terminals 140 at the cutting position A-A' shown in Fig. 7, and At the window 119, the outer lead 121 is connected to a predetermined signal electrode 112 of the liquid crystal optical shutter 18 by soldering.Furthermore, on the input terminal side, the base film 118 is cut at the cutting position BB'.

In this embodiment, the gate signals G1 and G are controlled by externally controlling the test control signal TG and the control signals T1 and T2.
2. Controls the output of G3 and G4 and connects them all together '41t terminal 1
The channel output of the high voltage output cover sofa 46 input to 40 is Y8, Y,. 1, Y2, 2, Y, (i=1.5
．． 9. ..., N-3) to check the channel outputs Y8 to Y, +3.

FIG. 8 (bl shows test control signal TG, control signal T1,
High voltage output cover sofa 46-X (
The output state of X=1.2, . . . , N) is shown. The same figure (b
), channel outputs Yi, Y, by setting TO="1" and controlling TI, T2. 1.Y.

2. Even when Y1+3 is short-circuited and connected to the collective connection terminal 140, it is possible to check each channel output.

For example, by setting TG="13" and T1=72="0", only the gate signal G1 becomes "L" and the channel output Y can be checked.Similarly, T
By setting G=71="1" and T2="0", the channel output Y i + 1 can be checked as TG=
By setting T 2 = “1” and T, 1 = “0”, the channel output Y 4 * z can be checked as TG = 7.
By setting 1 = T 2 = "1", channel outputs Y, + can be checked.

In FIG. 10, channel outputs Y1, Y,. Yl, 2,
Test 1as2a how to check the output of Y, and
'h... Shown as 7a, 8a. In the same figure, “
-" indicates don't care. When the circuit configuration of the high voltage output buffer 46-1 is as shown in FIG. 2 (fl), the outputs Y, . It becomes like yi~y and 3 shown in .

As can be seen from FIG. 10, the L'' and H'' outputs of channel output Y4 are determined by tests la and 2a, and by tests 3a and 2a.
L” and H” of channel output Y 6 + 1 by 4a
You can check the output of゛Similarly, channel output Y is determined by tests 5a and 6a.
The "L" and "H" outputs of i + 2 are tested in test 7a,
Channel output Y, by 8a. 3 “L” and “・H”
You can check the output of

Next, while referring to FIG. 1, FIG. 11, and FIG. 12,
Figure 2 shows the circuit configuration of the high voltage output buffer 46 in Figure 1.
A method of checking each channel output Y via the collective connection terminal 140 in the case shown in f) will be explained.

First, the control signal TH is set to "0" from the outside to enable the delay portions 42-1 and 42-2.

Next, as shown in the timing chart of FIG.
1=PT2="0" and turn on the power. and,
When TG=O and TI=72="1", the test control unit 70 outputs gate signal port=G2=G3="H", G4
= ``L'' is a high pressure resistant cover sofa 46-1.46
Add to i+1.46-1+2.46-i+3. For this reason, as shown in FIG. 8(b), the high pressure-resistant cover sofa 46
-1.46-1+1.46-i+2 output Yi, Yt+
+, Y8.2 becomes high impedance, and the output Y of the high voltage output cover sofa 46-i+3. , only are valid.

Next, from the external terminal D1, as shown in the procedure IC of FIG. If the number of channels of LSI30 is N, then N=4
is an integer that satisfies m). Data D2 is channel output Y.

In the shift register sections 4t-i and 41-2 of the circuit 40,
Data D3 and D4 are channel output Y. 1 circuit 40
The data D5 is stored in the shift register section 41-1, 41-2.
, D6 are sent to the shift register section 41-1.41-2 of the circuit 40 with channel output ¥1.2, and data D1 and DIl are sent to the shift register section 41-1.41-2 of the circuit 40 with channel output Y i + 3. Enter each.

In addition, the output of the data latch unit 43-1.43-2 of the circuit 40 for channel output Y, is 9, L2, and the data latch unit 43-1.43 of the circuit 40 for channel output Y, +1.
-2 output is L3, and the output of the data latch section 43-1, 43-2 of the circuit 40 of the new channel output Y1.2 is L3.
, L6 channel output Y, 9. The following explanation will be given assuming that the outputs of the data latch sections 43-1 and 43-2 of the circuit 40 are referred to as 1 and 43-2.

As shown in the timing chart of FIG. 4, by inputting the launch pulse CK2, the latch pulse generating section 50 first applies the launch pulse CK21 to the data latch section 43-1, 43-2, and then the delay section 42-2. 42-
1, latch pulses CK22 and CK23 are sequentially applied. As a result of this procedure 1c, the latch outputs L3, L6, and L become "O" as shown in FIG.

In the next step 2C, data D+ to D s =″01010101 as shown in FIG.
” for m blocks, and input the latch pulse CK2 as shown in the timing chart in FIG. In the next step 3C, only the latch pulse CK2 is input.At this time, the data latch section 43-2
The latch pulse CK21 applied to the data D2, D4, D6 . D8 is input from the delay section 42-2 to the data latch section 43-2. As a result, the latch outputs L1 to L all become "O" as shown in FIG.

Next, as shown in the timing chart of FIG.
When G is changed to "1", since TI=72="l", only G4 becomes "L" as shown in FIG. 8(b), and only channel output Y (+3 becomes effective). .

Next, when PT1=PT2 is set to "L", the DSEL is "O", so the launch outputs L1, L3, L5, and L7 are selected by the respective data selector modulators 44 and sent to the high voltage output cover sofa 46 via the level shifter 45. However, since only dl is the force L'', only 7 is latched output, and only 7 passes through the high voltage output cover sofa 46 and is connected to the collective connection terminal 140.
join. The output level at this time is shown in STB in Figure 12.
By inputting and checking the input from the bulk connection terminal 140 through the probe needle 141 during the first half pulse period of 7a, the output is latched and output ("0"), that is, the channel output Y8° is "L". You can check whether Note that NG in FIG. 12 indicates an incorrect output level (No Good).

Next, as shown in the timing chart of FIG.
When EL is changed from "0" to @1, only the latch output signal 8 is selected by the data selector modulator 44 and input to the batch connection terminal 140 via the level shifter 45 and the high voltage output cover sofa 46-i+3. At this time, the latch output and the output check (“0”) of 8 are as shown in Fig. 12.
This is done depending on whether the channel output Y1° is "L" during the second half pulse period of 7a of TB.

As shown in FIG. 8), by controlling T1aT2, the gate signals G3, G2, and G1 are sequentially set to L". Then, the high breakdown voltage output 46-i+2.46-i
By making the output of
This is done during the pulse periods of STB 5a, 3a, l, -a shown in Figure 2 (channel output Y, 42, Yi+1S
Check “L” of Yi).

After completing tests 1as 5as 3a and la, PT
Set ISPT2 and TG to "0". By setting TG="0", a high withstand voltage output 46-i is generated.

46-i+1.45-i+2.46-4+3 are all valid. By setting PT1=PT2="0", the high voltage output buffer 46-1.46-i+1,46
All outputs of -i+2.46-4+3 become "L", resulting in channel output Y, ,Y. I,Ye+Z
, Yi+3 are also all "L". In this way, channel outputs Y, , Y8 . After resetting all Yi+2 and Y4+3 to "L", set TG to 1", and then set TI
By setting T2 and T2 to 1", only the mouth is set to "L". Then, after validating only channel output Y and .3, PTI and PT2 are set to "1". Also, DSEL is set to "0". shall be.

Then, as shown in step 4C in FIG. 11, when "0" is input from the external terminal D1, the shift register section 41-1.4 is synchronized with the falling edge of the clock signal CKI.
The data D1 to D8 of 1-2 are shifted by 1 bit, and the data D1 to D become ="10101010". Then, the latch pulse CK2 is inputted at the timing shown in FIG. 4, and the latch pulses CK21, CK22, and CK23 are sequentially generated. Delay part 4 due to launch pulse CK21
The data D2, D4, D6, and D8 shown in step 2C of FIG. 11, which were latched in the data launch section 43-
2, all latch outputs L1 to L8 are “
1”.

Next, in the same way as when performing tests 7a, 5a, 3a, la, after setting TG-“1”, T1, T2, D S , E
L's system? 11, and the STB 8a shown in FIG.
During the pulse periods of 6a, 4a, and 2a, the output levels of the channel outputs Y1.3, Y, 2, Yl, 1, and Y (“
H'') is checked (Test 8 a'-).

5a, 4a, 2a).

As described above, all of the tests 1a to 8a have been completed, and the base film l18 on which the good drive LSI chip 122 is mounted is cut at the cutting position A-- shown by the dashed line in FIG.
Cut at A' and B-B''. Cutting position A-A'
By cutting the base film 118 at the channel output Y8, Y, + Y,. 2. The collective connection terminal 140 to which the four outer leads 121, which are the output lines of Y i 43, are connected together is disconnected, and the drive LSI chip 12
20 channel output Y is Yi*l5Yi and 2, Y
l-ya. Outer lead 1 connected to each terminal (band) of
21, channel output Y8, Y i + Y (+
z, Y,. 3 can be input individually.

Next, the outer lead 121 of this channel output Yj (j=1 to N) is connected to a predetermined signal electrode 112 of the liquid crystal optical shutter 18.

The connection between the outer lead 121 and the signal electrode 112 is made by the sixth
This is done by soldering at the position of the window 119 as shown in FIG.

Next, the high pressure-resistant cover sofa 46 shown in FIG.
13 and 13 show how to check when the outer leads 121 of the channel outputs Y, ~Y8.3 are all connected to the collective connection terminal 140 in the case of the circuit configuration shown in ), as shown in FIG. This will be explained with reference to FIG.

First, as in the case of the high voltage output buffer 46 shown in Fig. 2 ff), after setting PTl = PT2 = "0", setting TG = O, and resetting the channel outputs Y, ~Y,, 3 to "L". do. Next, as shown in step lb in FIG.
Terminal, Yorori, ~D, = ” 00000000
” for m blocks at the timing shown in Figure 3,
Latch pulse CK2 is inputted at the timing shown in FIG. 4, and latch pulses CK21, CK22, and CK23 are generated. As a result, the data D2 is stored in the delay part 42-1.
, D4, D5, and D8 are connected to the data latch section 43-1 by Dl,
D3, D3, D is input.

Therefore, the latch outputs 1 to L are the hand l of FIG.
As shown in 1ll't1b, it becomes "0XOXOXOX" (x indicates undefined). Next, in step 2b of FIG. 13, data D, to D8-"0000000,1" are input at the same timing as step 1b. As a result, data D2, D4 . Db and Da are input to the delay section 42-2.

Next, in step 3b of FIG. 13, 2-bit data "OO" is input, and the latch pulse CK2 is output at the timing shown in FIG.
Enter. As a result, the data D2, D4, D6, D8 (0, 0, 0, 0) in step 1b are input to the data launch section 43-2 at the fall of the launch pulse CK21, so the latch outputs L1 to L, i=″oooooooo
o”.

Next, TG, PTI and PT2 are changed from O'' to 1''. Then, by changing the outputs of TI and T2 as shown in FIG. 8(b), the gate signals G4, G3,
Set G2 and G1 to "L" sequentially, and test 7 shown in FIG.
a, 5a, 3ax1a are shown in the STB of FIG. 14. Pulses 7a, 5a.

Perform at timings 3a and 1a. Also, tests 7a, 5
In a, 3a, la, DSEL=“ in the first half of the test
By setting DSEL-“0” and DSEL-“1” in the second half, the latch output L1,
Channel output Y i + 3 by Ll, L8, Ll
, Y8゜2, Y, Y, "L" check in the second half of tests 7a, 5a, 3a, 1a, launch output L8,
Channel output Y8.3, Y by L8, L4, L2
1 * z, Y,. Check Y, L''.

After tests 7a, 5a, 3a, and 1a are completed as described above, channel outputs y, , y, , with PT1=PT2-"o" and TG="0".

is reset to “L”.

Next, as shown in step 4b of FIG. 13, data D,
-D a = "00010010" is input for m block 07 and latch pulse CK2 is input, data D (1'') of step 1b is input to data launch section 43-2 by latch pulse CK21, so launch output L1~L
8 becomes "00000011". Here, TG, T
,,T, are set to “1”, and PTI and PT2 are set to “1”.
1", only the gate signal G4 becomes "L" and the other G3, G2, and G1 all become "I]", so only the channel output Y i + 3 becomes valid.

This is because, as can be seen from the circuit configuration in FIG. 2(h), L, ~L6 are all "O", so the channel output Y8
,2,Y8. Input I of Yl's high pressure resistant cover sofa 46
is "L". Also, since the gate power G is also "H", the channel outputs Y1+2, Y,. This is because the output X of the high voltage output buffer 46 of Y becomes Z (high impedance). Furthermore, even if the gate power G is "H", if the input I is "H", the output In the case of using this method, the output check at the time of batch connection must be performed with the input I (latch output and the same as 1 to L8) of the high voltage output cover sofa 46 other than the channel output Y to be checked as L''. Therefore, As shown in step 4b of FIG. 13, output the lunch and set 1 to L8 to
”, only the gate signal G4 is set to “L”, and the first θ
Test 8a shown in the figure is performed. In addition, the ST shown in FIG.
By setting DSEL to "0" during the first half pulse period of 8a of B, the latch output L? However, by setting DSEL to "1" during the second half pulse period of STB 8a shown in FIG. 14, the latch output Lll is "L", but check 7 is performed depending on whether the channel output Yi+3 is "H" or not. I will After Test 1-83 is completed, PTI, PT2 and T
Channel output Yj (j-1~IN) when G is “O”
are all reset to “L”.

Next, as shown in step 5b of FIG.
Set De to "01001000", input the launch pulse CK2 at the timing shown in Fig. 4, and input the latch pulse GK.
Order 21, CK22, and CK23. Then, due to the fall of latch pulse GK21, data D in step 3b is
3 ("1") is input to the data latch sections 43-2. Therefore, the latch output, ~L, is 0000110
0'', so by setting T1=0 and T2=1 and setting only gate signal 7 to "L", test low a in FIG. 10 is performed. Channel output YJ (J=1~I
N) to "L".

Furthermore, after inputting 2-bit data "0" and "1" from the terminal D1 in step 6b of FIG.
Enter. As a result, data D4 (“1”) in step 4b is transferred to the data latch section 43 by the launch pulse CK21.
Since it is input to -2, it outputs lunch, and ~L8 is "0"
0110000”.Here, T1="1", T2
By setting ="0", only the gate signal G2 becomes "L".
'', and perform test 1-48 shown in FIG. 10 to check the "H" level of channel output Y,.1.Test 4
After completing step a, set PTI, PT2 and TG to 0'', reset channel output Y, (j-1-N) to “L”, and write 2-bit data “ as shown in step 7b of Figure 13.
Input ``O'', '0''. and (clock pulse CK
When "2" is input, data D2 ("1") in step 5b is input to the data latch section 43-2 due to the fall of the latch pulse CK21.
Since L8 is "11000000", T1 and T2
is set to "0" and only the gate signal Gl is set to "L".Then, in the first half pulse period of STB 2a shown in FIG.
Test 2a shown in Figure 0 is performed to check the output of latch L1 1'', and check the output of latch L2 during the second half pulse period of 2a of STB.
“L” output check of channel output Yi “H”
Perform the level check. As described above, even if the circuit configuration of the high voltage output buffer 46 is made as shown in FIG. 2(h), all of tests 1a to 8a shown in FIG.

The circuit configuration of the high pressure output cover sofa 46 is shown in Figure 2 (h).
In this case, there is an advantage that the number of gates can be reduced compared to the circuit configuration shown in FIG. 2(f).

The circuit configuration of the high voltage output cover sofa 46 and the level shifter 45 is as shown in FIG. 2(1) with the level shifter 46a shown in FIG. It is also possible to have a configuration.

As described above, in this embodiment, the outer lead interval FP of the driving LSI chip, which connects external lead terminals by the TAB method, is set to the arrangement interval SP of the signal electrodes of the liquid crystal optical shutter.
By setting SP>FP, it is possible to use a driving LSI whose outer leads are connected by the TAB method with the same outer lead interval FP even for liquid crystal light shutter (LC3) panels with different recording densities.

In addition, even if the FP is very narrow such as 0.1mm≦FP≦0.25m, the driving L
It is now possible to check the output of the SI chip.

Furthermore, for liquid crystal light shutter (LSI) panels with high recording density such as 480D PI and 600D PI, 240D PI can be used by extending the signal electrodes to both sides as shown in FIG. 5(d). , 30
It is possible to use a driving LSI chip whose outer leads are bonded by the TAB method with the same outer lead spacing as used in 0-DP I.

Furthermore, in this embodiment, an example of driving a liquid crystal optical shutter of 2 time division drive with 2 duty was shown, but in general, the micro shutter arrangement interval LP of a liquid crystal light shutter of n time division drive with 18 duty is LP= (m+f/n)+DOP
−−−−−−−(1,5)m=0.1,2.3 ・
... 1=1.2.3.4 ... n=time division number 1<n. Therefore, even for a liquid crystal optical shutter in which micro-shutters are arranged at intervals that satisfy equations (1, 5), the circuit configuration of a part of the delay circuit is changed to perform delay control of m lines corresponding to m above. By doing so, the liquid crystal optical shutter drive circuit of the present invention can apparently write correct dot data on one line.

〔Effect of the invention〕

As described above in detail, according to the present invention, the driving LSI chip of the liquid crystal optical shutter is outer lead bonded by the TAB method, and the outer leads from the driven SL chip are connected to predetermined test terminals for each plurality of outer leads. By connecting them all at once, the following effects can be obtained.

a. Since it is possible to externally control via the input side outer lead so that only one of the outer lead outputs connected to the above test terminals is valid, the output side outer lead spacing can be made so narrow that the test jig cannot check it. However, by making the test connection terminals sufficiently large, it is possible to easily check the operation of the driving LSI chip using a test jig. Further, as a result, it becomes possible to increase the number of bins of the driving LSI chip.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG.
l~(il is a circuit configuration diagram of the main circuit used in the above embodiment, FIGS. 3 and 4 are timing charts explaining the operation of the embodiment of FIG. 1, and FIG. 5 (al~fdl are , a configuration diagram of a two-time division drive liquid crystal optical shutter, and Figures 6(a) and lb) show the connection method between the outer leads of the drive LSI chip and the signal electrode of the liquid crystal optical shutter, in which the lead terminals are connected using the TAB method. The figure shown in Figure 7 is
Figure 8 shows how the outer leads of the drive LSI chip are connected all at once with the lead terminals connected using the TAB method (al is the high voltage output cover sofa and the gate signal G1
-G4 connection method, Figure 8 fb) is a diagram showing the control method of the high pressure output cover sofa, Figure 9 is a diagram showing how to connect the outer leads all at once, Figure 10 is the channel output Y ,~Y H+
FIG. 12 is a diagram showing the test procedure for checking the channel output of the driving LSI chip in the case of fl.
Fig. 13 is a timing chart explaining the operation of the steps IC to 4C shown in Fig. 1, and Fig. 2 f shows the circuit configuration of the high voltage output cover sofa.
Fig. 14 is a timing chart explaining the operation of steps 1b to 7b shown in Fig. 13; FIG. 16 is a sectional view of a print head; FIG. 17 is a plan view of a liquid crystal optical shutter. 41-1.41-2...Shift register section, 42-1
．． 42-2...Delay part, 43-1.43-2...
- Data latch section, 44... Data selector modulation section, 45... Level shifter, 46... High voltage output cover sofa, 50... Launch pulse generation section, 60... Delay control section, 70... Test control unit, 118... Base film, 119... Window, 121... Outer lead, 122... Drive LSI chip, 123... Bump, 140... Bulk connection terminal. Patent applicant Casio Electronics Industries Co., Ltd.
Top Casio Computer Co., Ltd. Cf) Figure 2-->-nu

Claims (1)

[Claims] A liquid crystal substance is sealed between two glass substrates, a plurality of scanning electrodes are provided on one glass substrate, a plurality of signal electrodes are provided on the other glass substrate, and the electrodes are formed at the intersection of both electrodes. In a drive circuit for a liquid crystal light shutter that drives a plurality of shutters, the drive circuit includes a shift register that serially inputs opening/closing data for opening and closing the shutters and outputs it in parallel; An LSI chip having delay means for delaying data, storage means for storing the output of the delay means, and a buffer for inputting the output of the storage means is connected to an external lead terminal on the film. A driving circuit for a liquid crystal optical shutter, characterized in that an output is taken out of the chip by the external lead terminal, and a plurality of the external lead terminals are connected to at least one test terminal.