JP2000019552A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a liquid crystal display having high quality by preventing the image flickering which occurs with mis-counting by segment drivers. SOLUTION: This liquid crystal display device has a first multilayered printed circuit board 1a which is connected to first electrode groups via TCPs 15A1 to 15AN mounted with plural segment drive circuits 16A1 to 16AN for impressing pixel drive voltages to at least the first electrode groups and a second multilayered printed circuit board which is connected to second electrode groups via the TCPs mounted with plural common driver circuits for impressing common voltages to the second electrode groups and has drive circuits, such as buffer circuits, for supplying image clock signals CL2 inputted from outside to the segment drive circuits 16A1 to 16AN. The high-speed clock signal wiring to be wired to the first multilayered printed circuit board is positioned in the layers close to the connecting surfaces of the TCPs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which a clock signal input to a segment drive circuit for supplying an image drive voltage to each pixel is prevented from being counted incorrectly and flicker is eliminated. About.

[0002]

2. Description of the Related Art A liquid crystal display device has a structure in which at least one is provided with a liquid crystal panel composed of a set of fine patterns constituting pixels on a pair of transparent substrates (liquid crystal display substrates). There are two types of liquid crystal display devices depending on the operation mode of the liquid crystal. One is a passive matrix display using a so-called STN liquid crystal material, in which pixels are formed at intersections of a pair of upper and lower striped electrodes, and the other is an active matrix display in which a switching element such as a thin film transistor is provided for each pixel.

In the passive matrix system, a first substrate having a first electrode group (hereinafter, referred to as a segment electrode group) formed in a direction bridging one parallel side of a substrate constituting a rectangular screen; A liquid crystal panel is formed in which a liquid crystal layer made of a liquid crystal composition is sandwiched between a second substrate having a second electrode group (hereinafter, a common electrode group) formed in a direction intersecting with the electrode group. The liquid crystal panel is the first
And a second multilayer printed circuit board. The first multilayer printed circuit board is connected to the segment electrode group via a plurality of segment drive circuits (or segment drivers) and applies a pixel drive voltage, and each segment drive circuit has a tape carrier pad for each of the plurality of segment electrodes. (Or TCP). The second multilayer printed circuit board is connected to a plurality of common electrode groups via a plurality of common drive circuits (or common drivers) and applies a common voltage, and each common drive circuit applies a TCP to each of the plurality of common electrodes. Will be installed.

[0004] A drive circuit is mounted on the second multilayer printed circuit board. The drive circuit supplies the segment electrodes based on a line clock signal (line pulse, generally CL1), a pixel clock signal (pixel pulse, generally CL2), and a frame clock signal (frame pulse, generally CL3) input from the host computer. Apply image data voltage.

[0005] The pixel clock signal CL2 is input from a controller on the host computer side and supplied to the clock line at a required level via a buffer circuit.
The clock line is wired to the second multilayer printed board and the first multilayer printed board. The clock line wired on the first multilayer printed circuit board is connected to a plurality of segment drivers in parallel. Each of the segment drivers counts a clock signal and applies an image data voltage to a predetermined pixel when the count reaches a predetermined count value.

FIG. 1 is a schematic diagram illustrating a conventional liquid crystal display device having a liquid crystal panel and a multilayer printed circuit board arranged on the liquid crystal panel. In this liquid crystal display device, the screen area of the liquid crystal panel 3 is vertically divided, and these are scanned in parallel. The upper screen area AR1 is a TCP 15A1 to 15AN for connecting the liquid crystal panel to the segment substrate 1a.
Plural segment drivers 16A1-16 mounted on
Driven by AN. The segment board 1a is a first multilayer printed board installed on the upper side of the panel. The lower screen area AR2 is driven by a plurality of segment drivers 16B1 to 16BN mounted on TCPs 15B1 to 15BN that connect the liquid crystal panel to the segment substrate 1b. The segment board 1b is a first multilayer printed board installed on the lower side of the panel.

[0007] A common substrate 2 as a second multilayer printed circuit board
Is mounted with a connector 11, a buffer circuit 12, and logic circuits 13a and 13b. Buffer circuit 12
Separates the pixel clock signal CL2 input to the connector 11 from the controller on the host computer side into two clock lines. As described above, the upper screen area AR1 is driven by the plurality of segment drivers 16A1 to 16AN installed on the upper side of the liquid crystal panel, and the lower screen area AR2 is driven by the plurality of segment drivers 16B1 installed on the lower side of the liquid crystal panel. Ｂ16BN. The frame clock signal CL3 is a signal (vertical synchronization signal) that defines the start timing of the screen, and the line clock signal CL1 is a signal (horizontal synchronization signal) that defines the start timing of one horizontal scan. Omitted. The signal lines of the clock signal CL1, the pixel clock signal CL2, and the frame signal clock CL3 are usually arranged on both the first multilayer printed board and the second multilayer printed board, and are connected by the joiner 14 between these printed boards. You.

FIGS. 2A and 2B are schematic views illustrating the structure of a conventional multilayer printed circuit board on the segment side. FIG. 2A is a perspective view of a main part, and FIG. 2B is a sectional view taken along line 2B-2B of FIG. .

As shown in FIG. 2A, a segment substrate 1a, which is a first multilayer printed circuit board, is disposed on the upper side of the liquid crystal panel 3 and has segment drivers 16A1 and 16A2.
Are connected to the panel via TCPs 15A1, 15A2, etc., on which are mounted. Japanese Patent Application Laid-Open No. Sho 60-70601 discloses this type of liquid crystal display device.
And JP-B-51-13666.

[0010]

This type of multilayer printed circuit board 1a has six to ten layers of laminated wiring 17, and FIG.
As shown in (b), the clock signal wiring is generally T
It is laid on the opposite side (lower layer side) of the CP. TCP
The solder connection portion 20 with the TCP 15A1 in the figure is connected to the pixel clock wiring 18 via the through hole 19. In particular, when the wiring 18 for the pixel clock signal CL2, which is a high-speed clock signal, is laid in the lower layer, a capacitance component (parasitic capacitance) occurs at the through hole 19, and reflection occurs.

FIG. 3 shows an equivalent circuit diagram of a clock wiring.
FIG. 4 shows a waveform diagram of the pixel clock signal CL2. In FIG. 3, C _TCP indicates the input capacitance of the _TCP 15A1 or the like, and C _T indicates the parasitic capacitance of the clock wiring. The clock signal CL2 from the buffer circuit 12 is supplied through the clock wiring,
It is counted by the CP segment driver 16A1 and the like. When the count reaches a predetermined value, each of the segment drivers takes in data and applies a pixel voltage to the segment wiring.

[0012] If there is a parasitic capacitance C _T of the clock wiring described above, the reflection component (-) is increased, the clock signal CL
2 has a waveform as indicated by R in FIG. If that counts such as the segment driver 16A1 at the falling edge of the waveform, the deformation of the waveform due to R in FIG occurs near the threshold V _TH of the high level H and low level L, counting miss occurs, this is such flicker on the screen There was a problem of causing display defects.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a high quality liquid crystal display device having no flickering in an image.

[0014]

In order to achieve the above object, according to the present invention, wiring of a high-speed clock signal to be supplied to a liquid crystal drive circuit on a multilayer printed circuit board is arranged in a layer close to a surface connecting a TCP. Thereby, the through hole for connecting the clock signal line to the TCP is made short enough to reduce the parasitic capacitance.

In a passive matrix type liquid crystal display device, the present invention has the following configuration.

(1) A first device having a first electrode group formed in a direction bridging one parallel side constituting a rectangular screen.
Substrate and a second electrode formed in a direction intersecting the electrode group.
Through a liquid crystal panel having a liquid crystal layer sandwiched between a second substrate having a group of electrodes and a plurality of segment drive circuits arranged to apply a pixel drive voltage to the first group of electrodes. And a pixel clock signal input from the outside through a TCP connected with a first multilayer printed circuit board and a plurality of common drive circuits arranged so as to apply a common voltage to the second electrode group. In a liquid crystal display device having a second multilayer printed circuit board on which a driving circuit such as a buffer circuit for supplying to a segment drive circuit is mounted, a high-speed clock signal wiring to be wired on the first multilayer printed circuit board is connected to a connection surface of the TCP. Position it on the layer near the side.

(2) The high-speed clock signal line in (1) is a pixel clock signal line.

According to the above configurations (1) and (2), the through hole connecting the clock signal wiring and the TCP is shortened, and the parasitic capacitance and the reflection noise are reduced. As a result, a liquid crystal display device having no flicker in the display image can be obtained.

In addition to the image clock signal line, the present invention can be similarly applied to other wirings such as a line clock signal (line pulse CL1) and a frame clock signal (frame pulse CL3).

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Overview of Passive Matrix Liquid Crystal Display First, an example of a liquid crystal display to which the present invention is applied will be described in detail. The following description is based on a passive matrix liquid crystal display device.

FIG. 5 is an explanatory diagram of an optical arrangement of a liquid crystal display device to which the present invention is applied. The liquid crystal layer is sealed between the upper substrate 30 and the lower substrate 31 at an interval of the cell gap d.
A pair of retardation films 34 and 35 and a pair of polarizing plates 32 and 33 are arranged so as to sandwich a cell constituted by 0 and the lower substrate 31.

An alignment layer of a polymer film is disposed at the interface between the upper substrate 30 and the lower substrate 31, and the rubbing alignment directions 40, 41 are defined in order to define the twist angle θ of the liquid crystal molecules constituting the liquid crystal layer. It is determined as shown.

FIG. 6 is an explanatory diagram showing the relationship between the adjacent rubbing direction and the optical axis of each component in the optical arrangement of the liquid crystal display device to which the present invention is applied.

As shown in FIG. 6, the rubbing alignment direction is formed so as to be symmetrical in the horizontal direction of the liquid crystal panel, and the twist angle θ is 230 degrees to 260 degrees. The retardation films 34 and 35 are arranged so that the directions of the optical axes 44 and 45 are at angles α and γ of 40 to 90 degrees (preferably 70 to 90 degrees) with respect to the adjacent rubbing directions 40 and 41. Be placed. The deflecting plates 32 and 33 have their polarization axes 4
The angles β and δ between the directions 2 and 43 and the directions of the optical axes 44 and 45 of the adjacent retardation films 34 and 35 are 20 degrees or more.
It is arranged to be 70 degrees (preferably, 30 degrees to 60 degrees).

FIG. 7 is a schematic sectional view of an essential part for explaining a structural example of a liquid crystal display device according to the present invention, in which the present invention is applied to a color liquid crystal display device.

In FIG. 7, a plurality of color filters 30b partitioned by a light shielding film (black matrix) 30a are formed on the upper substrate 30 side, a smoothing layer 30c is formed thereon, and then one transparent electrode 30d ( For example, segment electrode)
Is formed by patterning. A protective film 30e is formed on the transparent electrode, and an alignment film 36 is further formed thereon. The other transparent electrode 31a (for example, a common electrode) is formed on the inner surface of the lower substrate 31, and a protective film 31b is formed thereon, and then an alignment film 37 is formed.

FIG. 8 is a schematic sectional view of an entire liquid crystal display device in which a liquid crystal panel is integrated with a backlight. A liquid crystal panel 50 in this liquid crystal display device is laminated with a backlight 52 via an optical film 51 such as a prism sheet or a diffusion plate. These components are assembled in a predetermined relationship at the intermediate frame 55,
3 and the lower frame 54 are integrally fixed.

FIG. 9 is a perspective view of a laptop personal computer as an example of an electronic device incorporating the liquid crystal display device according to the present invention.

This laptop personal computer comprises a main body 60 and a monitor 61. The liquid crystal display device according to the present invention is mounted on the monitor section 61, and an image is displayed on the liquid crystal panel 62 thereof. Reference numeral 63 denotes a brightness volume, 64 denotes a contrast volume, and 65 denotes a display device and an image inversion switch.

The cross section shown in FIG. 8 is a cross section taken in the horizontal direction from the center of the monitor 61 in FIG. As shown in FIGS. 8 and 9, the above-mentioned multilayer printed circuit board is disposed in the monitor section. The above-mentioned clock signals CL1, CL2, and CL3 will be described more clearly with reference to FIGS.

The liquid crystal panels are multilayer printed circuit boards 1a, 1
A liquid crystal display module (hereinafter abbreviated as an LC module) is configured in combination with b and 2. L
The system of the clock signal supplied to the C module is shown in FIG.
0 is shown in the block diagram. FIG. 10 shows an SVGA-class liquid crystal display device according to the standard of image definition, and 8 pixels along the common electrode 31a (the y-axis direction of the coordinates shown in FIG. 10).
There are 00 pixels and 600 pixels along the segment electrode 30d. Each of the former pixels has three types of elements (red, green, and blue elements) for displaying a color image, so that the number of segment electrodes is 2,400. These three
FIG. 1 shows a pixel unit having elements as a hatched area PIX.
0 is shown.

Further, as shown in FIG. 10, the screen area is divided into an upper half AR1 and a lower half AR2, and each screen area has 2400 segment electrodes and 300 common electrodes, respectively. Therefore, both the upper half segment driver 16A and the lower half segment driver 16B are required in this case. FIG.
16A for each segment driver of 16AN
In the figure, the respective segment drivers 16B1 to 16BN are collectively and simply shown as 16B. The segment drivers 16A1 to 16AN and 16B1 to 16B1 shown in FIG.
16BN is put together in blocks 16A and 16B. To simplify the block diagram, FIG. 10 shows clock signal lines CL1 and CL related to the upper half of the liquid crystal display device.
2 and CL3, only these clock signal lines and display / reset signal lines DISP (discussed later) output from the buffer circuit 12 are connected to the segment driver 16B and common driver 26 involved in the lower half of the screen area. Partially distributed.

In this example, the line clock signals CL1,
Pixel clock signal CL2 and frame clock signal C
L3 has been generated by the LC module controller Ctrl. The LC module controller generates these clock signals by dividing another clock signal CLK supplied from, for example, a host computer HCOM mounted on the main unit 60 in FIG.

The LC module controller Ctrl is L
Depending on the design of the C module, it may be installed on the LC module or may be installed separately from the LC module. In the case of FIG. 10 in which the LC module is surrounded by a broken line, the LC module controller Ctrl is provided separately from the LC module. Therefore, the connector 11 of FIG. 1 is connected to the LC module controller and the signal line CL.
1, CL2, CL3, and DISP are arranged between the buffer circuits 12. Buffer circuit 12 amplifies the power of the signal associated therewith so as to be sufficient for the operation of the segment or common driver.

The host computer HCOM also supplies image signals (also called video signals and pixel signals) D1 to D8 to the segment driver 16A. In contrast to the clock signal, the image signal supplied to the segment driver 16A and the image signal supplied to the segment driver 16B are different from each other, but are generated by the host computer in response to the clock signal such as CLK described above. Although not shown in FIG. 10, the image signal is supplied to the segment driver 16B.
Are provided in the same manner as that for the segment driver 16A.

In the segment driver 16A, eight types of image signals D1, D2, D3, D4, D5, D6, D
7, and D8 are provided for each of the eight driver units. The driver unit is arranged inside the segment driver 16A and controls the voltage applied to each segment electrode. In FIG. 10, since there are 2400 segment electrodes along the segment driver 16A, 2400 driver units are arranged inside this.

The ten segment drivers 16A1 to 16AN (here, N = 10) shown in FIG.
Each of the segment drivers has 240 driver units therein. On the other hand, the image signal is shown in FIG.
0 are supplied through eight signal lines. Transmitting an image signal over N signal lines is an "N-bit transmission mode for image signals".
Called. Accordingly, FIG. 10 illustrates an 8-bit image signal transmission mode. According to this assumption, each of the segment drivers 16A must receive the image signal from the 8-bit signal transmission line to the associated 240 segment electrodes. Therefore, the segment driver takes eight signals 30 times in a predetermined period.

FIG. 11 shows the segment driver 16 of FIG.
It is explanatory drawing based on one of A1-16AN. FIG. 11 particularly exemplifies the segment driver 16A2, but the other segment drivers have the same configuration except for the address numbers of the segment electrodes shown at the bottom of the related figure. The inside of the segment driver is shown in FIG. 11 as a region surrounded by a broken line. The image signal lines D1 to D8 passing through this area and the segment voltage lines V _Y0 ,
V _Y1 , V _Y2 , and V _Y2H are arranged on the multilayer printed circuit board 1a, and the signals or voltages of these lines are sent to the segment driver 16A2 through the tape carrier pad 15A2.

In FIG. 11, the 8-bit image signal is L
The data is sequentially taken into the first latch circuits indicated as TA-1 to LTA-30. Arrows connecting each image signal line to each of the first latch circuits correspond to the driver units described above. Each capture of an 8-bit signal by the first latch circuit is controlled by a shift register SRT arranged in the segment driver 16A2. This shift register SRT includes first latch circuits LTA-1 to LTA-30.
-Flop circuits F / F-1 to F / F corresponding to
-30.

Each of the flip-flop circuits has a negative edge-triggered D flip-flop obtained by combining a plurality of NOR elements as shown in FIG. 12, for example, and the shift register SRT includes a plurality of flip-flop circuits. Cascade connection. This flip-
The flop circuit may be replaced with a type other than the D flip-flop circuit, and the cascade connection of a plurality of flip-flop circuits may be replaced with a counter or a combination of the counter and a decoder. Such a shift register SR
A sequential logic circuit suitable for T is described in, for example, "Contem" by RH Katz.
porary Logic Design "(The Benjamin / Cummings Publ
ishing Company Inc.) pp. 295-301 and 330-356
Page.

The flip-flops F / F-1 to 1 shown in FIG.
Assuming that each of the F / F-30s is a D flip-flop in FIG. 12, a high-state ("1" logic) enable signal from the segment driver 16A1 via the enable signal line ENA1 is transmitted to the flip-flop circuit F / F-. 1 terminal En (In), and as a result of the pixel clock signal CL2 transiting from the high state to the low state (“0” logic),
The output En (Out) of the flip-flop circuit F / F-1 provides a high state signal. At the same time, its inverted output / E
N (Out) provides a low state signal. The first latch circuit LTA-1 has a corresponding flip-flop circuit F
Assuming that an image signal is taken in in response to the high state signal of the output En (On) of / F-1, the corresponding segment electrodes Y _{241 to} Y ₂₄₁ of the first latch circuit LTA-1 at this time.
The image signal can be taken into the ₂₄₈ , and the other first latch circuits LTA-2 to LTA-30 cannot be taken. After the output of the high state signal from the terminal En (Out),
The flip-flop circuit F / F-1 does not supply a high state signal from its output terminal En (Out) until the next high state enable signal arrives at its input terminal En (In). Until the first flip-flop circuit F / F-1 supplies the next high state output to the first latch circuit LTA-1, its signal capture is also stopped.

In FIG. 11, the high state signal from the terminal En (Out) of the flip-flop circuit F / F-1 enters the terminal En (In) of the flip-flop circuit F / F-2 at the next stage. . Then, the next high-to-low transition of the pixel clock signal causes the flip-flop circuit F / F-2 to output a high state signal from the terminal En (Out) to the corresponding first latch circuit LTA-. Feed to 2. At this point, the first latch circuit LTA-2 can capture the image signal into the corresponding segment electrodes Y ₂₄₉ to Y ₂₅₆ , and the other first latch circuits cannot.

By repeating such an order, in the segment driver 16A2, in response to the transition of the pixel clock signal CL2 from high to low, the first latch circuit from LTA-1 to LTA-30 sequentially takes in the image signal. Done. Flip-flop circuit F / F-
The high state signal output from 30 is provided by another enable line EN.
The signal is sent to the next segment driver 16A3 via A2, and enters the flip-flop circuit F / F-1. Other segment drivers 16A1 and 16A3 to 16A
10 has substantially the same circuit as the segment driver 16A2, the image signals supplied by the signal lines D1 to D8 are supplied to the respective first latch circuits from the LTA-1 of the segment driver 16A1 to the LTA-30 of the segment driver 16A10. Accordingly, the data is sequentially (in other words, time-divisionally) fetched every eight segment electrodes along the y-axis direction. These image signals are stored in the driver units of the respective first latch circuits regardless of the fetch time. After the last signal input to Y ₂₃₉₃ to Y ₂₄₀₀ is completed, the line clock signal CL1 changes from the high state to the low state. This line clock signal C
Transition from L1 high to low, turns on the second latch circuit LTB 11, and supplies the image signal to the level shifter LST to all had been accumulated segment electrodes Y ₀₀₀₁ to Y _2400. The level shifter LST amplifies these video signals so as to operate the segment voltage source SVS provided in the next stage. Finally,
The segment voltage source SVS uses one of V _Y0 , V _Y1 , V _Y2 , and V _Y2H supplied from the segment voltage line as a voltage of the segment electrodes Y _{0001 to} Y ₂₄₀₀ and outputs a signal from the corresponding level shifter. Selection is made according to the output, and each selected voltage is applied to an individual segment electrode.

The sequence of taking in the image signal and applying the voltage to the segment electrodes described above is further explained by the signal waveforms shown in FIG. 13 as the operation of the entire liquid crystal display device. FIG.
In FIG. 3, the time axis (horizontal axis) of the upper five waveforms is the lower three waveforms.
Stretched against that of the waveform. As shown in FIG. 13, each of the clock signals CL1, CL2, and CL3 has a waveform that changes its state between high (H) and low (L) at a predetermined cycle. For this reason, each clock signal has, for example, a frequency defined by the interval between successive high-to-low transition times. Usually these three
Among the frequencies f1, f2, and f3, the frequency f2 of the pixel clock signal CL2 is the highest, and the frequency f3 of the frame clock signal CL3 is the lowest.

On the other hand, each of the image signals D1 to D8 has a pattern corresponding to a plurality of pieces of pixel information. FIG.
Although the waveforms of D3 and D8 are shown, other image signals have similar waveforms. Each waveform of the image signals D1 to D8 is shown as a hexagonal series corresponding to the waveform of CL2. This series means that the image signal can take either a high state or a low state in a predetermined cycle. Therefore, for example, in the signal D1,
When the image signals of the segment electrodes Y ₀₀₀₁ , Y ₀₀₀₉ , and Y ₀₀₁₇ are in the high state and the image signal of the segment electrode Y ₀₀₂₅ is in the low state, the image signal D 1 corresponding to the first three pulses of CL ₂ from time t _1. Stays high.

Image signal capture to all the segment electrodes Y _{0001 to} Y ₂₄₀₀ is completed within a period from t ₁ to t ₃ . In practice, the first latch circuit of the segment driver 16A LTA has already accumulated at time t ₂ the signal to the corresponding segment electrode thereto. In time t _2, the clock signal to the CL1 also the second latch circuit LT
B is the segment voltage source SVS from the first latch circuit LTA.
Transition from the high state to the low state so as to cause the signal to be transmitted. Then, all voltages corresponding to each of the image signals stored in the first latch circuit are applied to the corresponding segment electrodes. At the same time, a predetermined voltage is applied to the common electrode _X001 . Depending on the potential difference between the segment electrodes Y ₀₀₀₁ to Y ₂₄₀₀ respectively and the common electrode X ₀₀₁ of the image appears in a portion corresponding to the common electrode X ₀₀₁ screen area AR1. After time t _3, it begins round of image signal acquisition corresponding to the common electrode X _002. In order to adjust the timing of capturing the image signal and applying the voltage to the common electrode, the signals D1 to D3 and D8 and the waveform of the common driver control COM-Dr have a dummy period that does not directly contribute to image display.

As described above, image signal capture is repeated by the number of common electrodes, and the screen area AR
1 is completed. The order of capturing image signals to each common electrode is called “scanning”, and the voltage applied to the common electrode is also called “scanning voltage”. Line clock signal CL1 is in a manner similar to the voltage distribution to the segment electrodes, for distributing the voltage to each of the common electrode X ₀₀₁ to X _300.

FIG. 14 shows an outline of the common driver 26. After the clock signal CL1 enters the first logic circuit that controls the alternating signal generation source ACS, the shift register SRT
-1 to SRC-15. These shift registers are similar to the shift registers in each of the segment drivers, but differ in their ability to transmit enable signals in both directions. The flow of signals from these shift registers SRT-1 to SRT-15 through the level shifter LSC to the common voltage supply CVS is based on the fact that a latch circuit operating with a clock signal other than that intended for the shift register uses the shift register SRC and the level shifter LS
It is similar to that of the segment driver except that it is not arranged between C and C. Thus, as soon as one driver unit of the shift register outputs a signal to the corresponding common electrode, a predetermined voltage is applied to the common electrode. Since the common voltage is applied to each of the common electrodes X _{001 to} X ₃₀₀ in the manner described above, the common voltage application times are different from each other.

On the other hand, the frame clock signal CL3 has a pulse corresponding to the entire image display, and the pulse is a common electrode X to which a voltage is applied first in the order of the entire image display.
It appears during the period of the pulse of the clock signal CL1 corresponding to ₀₀₁ . For this reason, the clock signal CL3 is “first
Also called "line marker".

[0050] Depending on the pulse of the frame clock signal CL3, the segment driver 15A1 described above, images to in response to a transition to the row from the first high-pixel clock signal CL2, the first segment electrode Y ₀₀₀₁ to Y ₀₀₀₈ Starting with signal capture, the first transition of the line clock signal CL1 from high to low corresponds to the segment electrodes Y _{0001 to} Y ₂₄₀₀
And a voltage is applied to the common electrode _X001 .

Therefore, it can be said that the display operation of the liquid crystal display device depends, in a sense, on the timings of these three clock signals CL1, CL2 and CL3.
In the liquid crystal display device illustrated here, both the first multilayer printed circuit boards 1a and 1b and the second multilayer printed circuit board 2 have signal lines for these three clock signals to the segment or common driver. These three signal lines are supplied from the signal lines of the multilayer printed circuit board to a tape carrier pad having a segment or a common driver mounted thereon.

FIGS. 15 (a) and 15 (b) are enlarged images of the connection portion between the first multilayer printed circuit board 1a (partial) and the tape carrier pad 15A1 in FIGS. 2 (a) and 2 (b). Is shown. FIG. 15A is a plan view of an upper wiring layer (referred to as a “TCP connection surface”) of the first multilayer printed circuit board, on which a plurality of terminals 20a are arranged. Each of these terminals 20a is connected to one of the terminals 20b formed on the tape carrier pad 15A1 by solder or an anisotropic conductive film. Signals or voltages supplied from the respective wiring layers in the multilayer printed board 1a pass through the leads 25 and enter the segment driver 16A1 in FIG. Most of the terminals 20a have a conductive layer 81c terminated by the through hole 19. Only the enable signal is transmitted to another segment driver via a unique signal line 81a provided on this layer. The (NC) terminal not used for ground potential (GND) is connected to the conductive layer 81b interrupted in the y direction. The conductive layer 81b is formed to prevent electromagnetic interference (EMI) from / to other signal lines disposed on the first multilayer printed circuit board.
In consideration of EMI, the clock signal line is arranged near the side opposite to the TCP connection surface of the multilayer printed circuit board, and a plurality of wiring layers are stacked as a shield layer therebetween.

As shown in FIG. 15, the multilayer printed circuit board 1
Many types of lines other than the clock signals CL1, CL2, and CL3 are arranged in a. Other wirings in the multilayer printed circuit board of this example are classified as follows.

Group 1: picture quality control lines W1, W2; Group 2: enable signal lines ENA1, ENA2; Group 3: display reset signal line DIS
P; group 4: driver voltage line V _CC , segment voltage line V _Y0 , V _Y1 , V _Y2 , V _Y2H , ground potential line GND.

When compared with the clock signals CL1, CL2, CL3, the lines of group 4 are completely different from the clock signal lines in their application. Each wiring of group 4 does not transmit any signal, but supplies power to the liquid crystal display panel or its driving circuit. For this reason,
Even if the AC component is accidentally superimposed on the current by EMI from a peripheral circuit, the potential of the wiring of Group 4 is considered to be stable. Since the ground potential is regarded as one of the potentials, the ground potential line GND is also included in Group 4. FIG.
In the block diagram of FIG. 4, common voltages V _M , V _L , and V
_H also belongs to this group.

The display reset signal DISP of group 3 is a signal, but does not change its state during image signal capture by the segment driver defined between t ₁ and t ₂ in FIG. Therefore, the potential of the display reset signal line DISP is considered to be stable during this period. A signal having such a characteristic as the display reset signal is transmitted by wiring classified into group 3.

As described above, the enable signal changes its state (high or low) in response to the image signal capture, and the change occurs locally along the segment driver array. This is because, while the pixel clock signal CL2 is distributed in parallel to the segment drivers, the enable signal lines ENA1 and ENA2 are connected to these segment drivers (to be precise, their shift registers or the like).
Must be connected in series. For this reason, when a plurality of segment drivers are arranged in the extending direction (y) of the multilayer printed circuit board and each of the enable signal lines is connected in series, the potential of the entire enable signal line along the extending direction is 3 as described above. It can be considered substantially stable as compared with one clock signal. The wirings of group 2 transmit signals that can be regarded as substantially stable due to the difference in signal path from the clock signal. Shift register S
In view of its role in a sequential logic circuit such as RT, the enable signal is shown as its unique circuit element, but its operation is dominated by the pixel clock signal CL2 rather than the enable signal.

The image quality control lines W1 and W2 transmit signals generated by the logic control circuit 13 which has received the pixel clock signal CL2 in FIG. Thus, this signal can change its state in response to the clock signal. However, as shown in FIG. 11, the image quality control signals W1 and W2 are not supplied to a shift register (as sequential logic).
A segment voltage source SVS is provided to adjust its operating conditions. Signal lines classified as Group 1
A signal such as an image quality control signal that does not contribute to image signal capture is transmitted. The alternating signal M from the alternating signal generation source ACS is also transmitted by the wiring of group 1.

The AC signal M is for adjusting the bias direction between the segment electrode and the common electrode, and does not contribute to the scanning signal acquisition.

[Improvement in Liquid Crystal Display Device] The present inventor has found that the deterioration of the signal waveform described above with reference to FIG. 4 has a serious effect on the operation of the sequential logic circuit.
When applying the waveforms of FIG. 4 to the rectangular waves of the clock signals CL1, CL2, and CL3, it is clear that the waveform deformation of FIG. 4 causes a problem of miscounting in the timing control of the logic circuit. Although the foregoing description of the counting is based on the negative edge triggered logic, the waveform of FIG. 4 suggests that this problem is due to the positive edge triggered logic (counting by low to high transition of the clock signal. Operation is adjusted). In the above description, the relationship between the first multilayer printed circuit board 1a, the parasitic capacitance, and the pixel clock signal CL2 has been discussed, but such a parasitic capacitance also appears on the second multilayer printed circuit board 2, and other than the pixel clock signal. As long as the signal dominantly controls the timing of the circuit operation, the pixel clock signal CL2
May have similar problems.

In the case of the liquid crystal display device shown in FIG. 1, all of the segment drivers 16A1 to 16AN are monolithically integrated, or they are put together in a package to make a single clock signal supply portion. By reducing the number of contact holes that supply the clock signal to the driver circuit, the parasitic capacitance can be reduced to a value that can sufficiently suppress the waveform deformation of the clock signal. However, considering the dimensions of the liquid crystal display panel, the former method requires that a semiconductor chip extending to 10 cm or more be manufactured. Therefore, this method is not practical from the state of the art. Although the latter method can be realized, it is difficult to mount the driving circuit on the periphery of the liquid crystal display panel.

Accordingly, the inventor has considered the structure of a multilayer printed circuit board that causes the above-described waveform deformation by itself. One preferred configuration for suppressing the parasitic capacitance along the clock signal line CL2 according to the present inventors' consideration is shown in FIG.
(a) and 16 (b). FIG. 16 (b) is the same as FIG. 16 (a).
6B shows a cross-sectional image of 16B-16B.

In FIG. 16B, the clock signal CL2
Is transmitted through a wiring layer 81a (CL2) arranged on the TCP connection surface of the multilayer printed circuit board 1a and extending in the y direction. As described above, the clock signal CL2 has priority over the other clock signals CL1 and CL3.

In this configuration, the wiring layer 81a (CL2)
Are the wiring layer 81a (GND) of the ground potential and the conductive layer 81
b (GND). As shown in FIG. 16B, another wiring 82a (GND) of the ground potential is connected to the wiring layer 8
1a (CL2). The additional through hole 19s is formed by connecting the wiring layer 81a (GND) to another wiring layer 82a (GND).
The potential of 1a (GND) is kept stable. Clock signal CL
2 is surrounded by the ground potential layer, thereby forming the wiring layer 81.
The potential around a (CL2) is stabilized, and electromagnetic interference (EMI) from / to this wiring layer is reduced. For such a purpose, the layer surrounding the wiring layer 81a (CL2)
It is selected from any of the above-mentioned groups 1 to 4, and especially the group 4 is recommended.

The cross section of the multilayer printed circuit board shown in FIG.
It has six steps. The first stage including the wiring layer 81a (CL2) is formed on the film 71 covering the glass-epoxy substrate 72 and has a through hole. The glass-epoxy substrate 71 has sufficient rigidity to sufficiently fix the first layer. The second layer including the wiring layers for the clock signals CL1 and CL3 is formed on the upper surface of the glass-epoxy substrate 72, and the third layer is formed on the lower surface of the substrate. The fourth layer including the wiring layer for the image signal Dn is formed of another glass layer.
It is formed on the upper surface of the epoxy substrate 74, and the fifth layer is formed on the lower surface of the substrate. Further, another film 75 is formed on the lower surface of the glass-epoxy substrate 74, and a sixth layer is formed on the lower surface of the film 75. Glass
A lower surface of the epoxy substrate 72 and another glass-epoxy substrate 7
The upper surface of 4 is affixed with glass fiber impregnated with epoxy resin. By hardening the epoxy resin in the region 73 between the third and fourth stages, the multilayer printed board 1a is completed. The number of stages can be increased by inserting additional glass-epoxy resin between the glass-epoxy resin substrates 72,74. The solder resist layer 90 is provided on the upper surface of the film 71 and the lower surface of the film 75 except for the terminal 20a.

In FIGS. 16A and 16B, the pattern of each conductive layer is changed according to the group to which it belongs. Each conductive layer for the clock signal lines CL1, CL2, CL3 has a common pattern. Each conductive layer for the image signal lines D1 to D8 has another common pattern. Each of the other conductive layers has a pattern classified into the above-described four groups except for the ground potential line GND. These notations are used in other drawings of this specification.

In the current products, one of the main factors is to reduce the frame width of the liquid crystal display device. For this reason, the width Lx of the multilayer printed circuit board must be as narrow as possible.

In order to satisfy such a demand without deforming the waveform of the clock signal, the present inventor considered another structure.
An overview of this structure is described below with reference to FIGS.

FIG. 17 is a sectional view similar to FIG. 2B, illustrating the structure of a segment-side multilayer printed circuit board of a liquid crystal display device according to an embodiment of the present invention.

As in the case of FIG. 2B, the segment 1a as the first multilayer printed circuit board is disposed on the upper side of the liquid crystal panel 3 and connected via the TCP 15A1 or the like on which the segment driver 16A1 and the like are mounted. .

In this embodiment, the wiring 18 for the pixel clock signal CL2 laid on the multilayer printed circuit board 1a is wired on the uppermost layer. The pixel clock signal wiring 18 and the solder connection part 20 of the TCP 15A1 are connected via a short through hole 19. Therefore, the parasitic capacitance due to the through hole 19 is negligible.

FIG. 18 is an equivalent circuit diagram of the clock wiring in the embodiment of FIG. 17, and FIG. 19 is also a waveform diagram of the pixel clock signal CL2.

In FIG. 18, since the parasitic capacitance C _T of the clock wiring is almost negligible, the reflection component (−) due to this is extremely small, and the capacitance component is only the _TCP input capacitance C _TCP . Therefore, as shown in FIG.
The waveform of the pixel clock signal CL2 is not deformed as shown by R in FIG. 4, and the segment driver 16A-1 and the like can correctly count clocks with the threshold value V _TH .

[Supplement] One of the multilayer printed circuit boards based on FIG. 17 will be described in detail with reference to FIGS. 20 (a) to 20 (c) and FIGS. 21 (a) to 21 (c). This multilayer printed circuit board is formed by laminating six layers in the z-axis direction as shown in FIG. FIG. 20A shows the first stage (the TCP connection surface) in FIG.
0 (b) shows the second stage, FIG. 20 (c) shows the third stage, and FIG.
21 shows the fourth stage, FIG. 21 (b) shows the fifth stage, and FIG. 20 (b) shows the sixth stage. Reference numeral 81a specifies a conductive layer used for signal transmission or power supply, 81b specifies a conductive layer used for purposes other than 81a, and 81c specifies a lead between the terminal 20a and the through hole 19. The reference numbers are also changed depending on the number of stages, such as 82 for the second first stage and 86 for the sixth stage. 22 in FIG.
A cross section along -22 is shown in FIG.

As shown in FIG. 20B, the wiring layer 82a for transmitting the pixel clock signal CL2 and the line clock signal CL1 is arranged at the second stage. On the other hand, the frame clock signal CL3 is arranged at the third stage. Therefore, each of the clock signal lines CL1, CL2, CL3 is
It is arranged closer to the first stage (TCP connection surface) than the center of the laminated structure between the third stage and the fourth stage. This layout is recommended when each of the clock signals CL1, CL2, CL3 has a frequency above 10 MHz, especially above 15 MHz. When the frequency of the clock signal is sufficiently low, the above-described miscounting problem can also be solved by circuit design. However, when the frequency of the clock signal is increased to 10 MHz or higher, a circuit design for eliminating the miscounting degrades the high-speed characteristics of the liquid crystal display device that can be achieved with a clock signal having such a high frequency. For this reason, the clock signal line transmitting a sufficiently low clock signal may be arranged at a stage far from the TCP connection surface with respect to the center of the laminated structure. Usually, the center of the laminated structure is defined as the average value of the number of stages, but is defined as a half of the laminated thickness according to the laminated structure from the TCP connection surface to the furthest and the stage having the conductive layer. You may.

Other improvements are as follows. A clock signal line in the following description is defined as having priority over other clock signal lines from the viewpoint of a miscounting problem.

(1) The clock signal lines are connected to groups 2, 3,
And 4 to further reduce the probability of occurrence of parasitic capacitance. Accidental waveform deformation is also a voltage fluctuation in other conductive layers around the clock signal line, especially around its through hole. The through hole is preferably terminated at the layer of the clock signal line, and the projection 19p of the end point thereof is formed.
(Shown by a bold line) may be opposed to wirings selected from groups 2, 3, and 4. As a result, these wirings keep the influence of voltage fluctuation away from the clock signal line. It is preferable that at least one of the wirings surrounding the clock signal line belongs to Group 4, and it is more preferable that all of these wirings belong to Group 4. In preventing voltage fluctuation around the clock signal line, the through hole is defined as a region 20c surrounded by dotted lines extending in the y direction in FIGS. 20 (a) to 20 (c) and FIGS. 21 (a) to 21 (c). It is recommended to keep it away from the indicated terminal area or its projection onto the other stages. FIG.
As shown by 0 (b), according to the priority, the through hole of CL2 is arranged on the side opposite to the area 20c where the terminal area (20c in FIG. 20A) is projected to the second stage, and the through hole of CL1 is placed. Is placed slightly closer to the area 20c while being closer to the area 20c.

(2) As shown in FIGS. 20 and 20, the clock signal line is separated from the other clock signal lines by a space along or between the stages, and the parasitic capacitance induced by electromagnetic interference between the clock signal lines. Suppress. Preferably, it is desirable to separate the clock signal line from a signal line such as an image signal line that can cause a voltage change in a short cycle like this. For this reason, as shown in FIGS. 21 (a) and 21 (b), it is recommended that the image signal lines and the wiring of group 1 be arranged at a lower stage than the stage where the clock signal is arranged. You. 20 (a) and 20 (b), the through hole of the clock signal CL2 is adjacent to that of the image quality control signal line W1, but the through hole of at least one wiring group 2, 3, or 4 is provided between them. Is recommended.

(3) The lead length between the clock signal line and its through hole is made as short as possible, and the probability of occurrence of parasitic capacitance along the lead is reduced. FIG. 23 shows FIG.
It is explanatory drawing based on (b). As shown in FIG. 23, when arranging at least one signal line other than the clock signal line to be prioritized (here, CL2), this lead length Lh
It is recommended that 2 be shorter than Lh1 of another signal line (here, CL1).

The above description is based on a multilayer printed circuit board used on the segment driver side. However, when used on a multilayer printed circuit board on the common driver side, the clock signal CL1 must be given priority over other clock signals. . The clock signal CL2 usually passes through the multilayer printed circuit board on the common driver side and goes to that on the segment driver side. Therefore, when there is no logic circuit that operates in response to the clock signal CL2, the waveform deformation on the multilayer printed circuit board on the common driver side does not need to be reflected on the wiring layout.

FIG. 24 is a plan view of a principal part for explaining the periphery of the driving circuit of the liquid crystal display device according to one embodiment of the present invention. In FIG. 24, a second multilayer printed board (also referred to as a common drive board) 2 is provided on the left side of the liquid crystal panel, and a pixel clock signal CL2 from the host computer is input from the connector 11 to the buffer 12.

The buffer 12 supplies the pixel clock signal CL input from the host as a required level to the pixel clock wiring. The pixel clock wiring is connected from the second multilayer printed circuit board 2 to the clock wiring of the first multilayer printed circuit board 1a by the joiner 14, and the segment driver 16A1 is connected to the first multilayer printed circuit board 1a by the clock wiring described in FIG. And so on.

According to the structure of this embodiment, the through hole connecting the pixel clock wiring and the TCP is shortened, the parasitic capacitance is reduced, and the capacitive reflection noise can be almost ignored. Therefore, a flicker does not occur in the display image, and a high-quality image display can be obtained.

The present invention is not limited to the passive matrix type liquid crystal display device described above, but can be similarly applied to various liquid crystal display devices such as an active matrix type.

A passive matrix type driving circuit and its peripheral circuit are described in, for example, "Liquid Crystal Display Technology-Active Matrix LCD" by S. Matsumoto (industrial book).
It is disclosed on pages 73-82 and 126-130.
As disclosed therein, also in a passive matrix type liquid crystal display device, a logic circuit is required for taking in pixel data and scanning a gate voltage to a desired thin film transistor group. According to the structure of the current passive matrix type liquid crystal display device, the structure of the pixel data driver is similar to the segment driver, and the structure of the scanning driver is similar to the common driver, not only in the structure but also in the function as described above.

Therefore, the laminated structure of the multilayer printed circuit board of the segment driver described above can be used on the data line driver circuit (also referred to as a drain line driver circuit or a video signal driver circuit) side with a slight change. In this modification, an analog or digital video signal generated at the interface between the liquid crystal display device and the computer or the television tuner may be regarded as the image signal in the above description. The plurality of gradation voltages supplied to the data line driver are also characteristic of the active matrix type. These voltage wirings belong to the group 4 described above.

The present invention is effective irrespective of the driving mode of the liquid crystal display device, and is also effective for electric equipment such as a computer shown in FIG. In this laptop personal computer, it is possible to obtain a high-quality image display without a flicker of a display image caused by a clock signal count error as in the related art.

[0088]

As described above, according to the present invention,
Segment driver count errors are less likely to occur,
A high-quality liquid crystal display device with no flickering in an image can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a conventional liquid crystal display device including a liquid crystal panel and a multilayer printed circuit board arranged on the liquid crystal panel.

FIGS. 2 (a) and 2 (b) are schematic diagrams showing a conventional multilayer printed circuit board on the segment side and a cross section of 2B-2B thereof.

FIG. 3 is an equivalent circuit diagram of a clock wiring.

FIG. 4 is a waveform diagram of a pixel clock signal CL2.

FIG. 5 is an explanatory diagram showing an optical arrangement of a liquid crystal display device to which the present invention is applied.

FIG. 6 is an explanatory diagram showing a relationship between an adjacent rubbing direction and an optical axis of a component in an optical arrangement of a liquid crystal display device to which the present invention is applied.

FIG. 7 is a cross-sectional view of a main part showing a structural example of a liquid crystal display device to which the present invention is applied.

FIG. 8 is a schematic sectional view of the entire liquid crystal display device in which a liquid crystal panel is integrated with a backlight.

FIG. 9 is a perspective view of a laptop personal computer as an example of an electronic apparatus incorporating the liquid crystal display device according to the present invention.

FIG. 10 is a block diagram of a signal flow system around a liquid crystal module.

FIG. 11 is a block diagram of a signal flow in the segment driver.

FIG. 12 is a D flip-flop used for a shift register of a segment driver.

FIG. 13 is a waveform diagram of a clock signal and an image signal.

FIG. 14 is a block diagram of a signal flow system in the common driver.

FIG. 15A is an enlarged view of a TCP connection surface of a multilayer printed circuit board, and FIG.
It is an enlarged view of TCP which has a terminal corresponding to a terminal on a CP connection surface.

FIGS. 16 (a) and 16 (b) are one of suitable multilayer printed circuit boards for suppressing the waveform deformation of the clock signal CL2, and FIG. 16 (b) is a diagram of FIG.
16B shows a cross section.

FIG. 17 is a cross-sectional view similar to FIG. 2B, showing a configuration of a segment-side multilayer printed circuit board in a liquid crystal display device according to an embodiment of the present invention.

FIG. 18 is an equivalent circuit diagram of the clock wiring in the embodiment of FIG.

FIG. 19 is a waveform diagram of a pixel clock signal CL2 in the embodiment of FIG.

20 (a) to 20 (c) are plan views of a six-layered (consisting of printed circuit layer) laminated structure based on the embodiment of FIG. 17, and show the first stage (having a TCP connection surface). ) To the third row are shown in this order.

FIGS. 21 (a) to 21 (c) correspond to FIG. 20 (a).
7 is a plan view of the same laminated structure as that shown in FIG.

FIG. 22 is a sectional view 22-2 of the laminated structure of FIG.
2 shows a section along 2.

FIG. 23 is an explanatory diagram based on FIG. 21 (b).

FIG. 24 is a main part plan view showing a driving circuit of the liquid crystal display device of the present invention and its related circuits.

Claims (23)

[Claims] 1. A first substrate having a first electrode group formed in a direction bridging one parallel side forming a rectangular screen, and a second substrate formed in a direction intersecting the electrode group. Through a liquid crystal panel having a liquid crystal layer sandwiched between a second substrate having a group of electrodes and a plurality of segment drive circuits arranged so as to apply a pixel drive voltage to the first electrode group. A first multi-layer printed circuit board connected to the second electrode group via a TCP mounted with a plurality of common drive circuits arranged so as to apply a common voltage to the second electrode group, and a pixel clock signal input from the outside, In a liquid crystal display device having a second multilayer printed circuit board on which a drive circuit such as a buffer circuit for supplying to a segment drive circuit is mounted, a high-speed circuit for wiring to the first multilayer printed circuit board is provided. The liquid crystal display device, characterized in that the click signal wiring was positioned in a layer closer to the connecting surface side of the TCP. 2. The liquid crystal display device according to claim 1, wherein said high-speed clock signal wiring is a pixel clock signal wiring. 3. A first and a second substrate which are superimposed on each other so that their main surfaces constitute a panel, a liquid crystal layer sealed between the first and the second substrates, A plurality of first electrodes formed on one upper portion of the substrate and extending in a first direction and arranged in a second direction crossing the first direction; and the second electrodes formed on one upper portion of the substrate. A plurality of second electrodes extending in the first direction and arranged in the first direction; a stacked structure of a plurality of printed circuit layers arranged in the periphery of the panel and extending in the first direction and stacked; A first printed circuit board having a laminated thickness corresponding to a structure, and arranged in the first direction between the first printed circuit boards, each of which is at least one of the corresponding first electrode or the second electrode. A voltage supply for applying a voltage at one time; A plurality of first driving circuits each having at least one control unit for controlling the voltage supply source in response to at least one clock signal transmitted by a printed circuit board, wherein the first printed circuit board has the laminated structure Having an electrical contact with the first drive circuit for supplying the clock signal to each of the first drive circuits in parallel on a first printed circuit layer disposed at one end of the first drive circuit layer; A liquid crystal display device, wherein a signal transmission line is disposed on one of the printed circuit layers closer to the electrical contact than the center of the stack thickness. 4. The transmission line for a clock signal according to claim 3, wherein said transmission line is disposed on said first printed circuit layer.
3. The liquid crystal display device according to 1. 5. The laminated thickness is defined by the number N of the printed circuit layers excluding the first printed circuit layer, and the transmission line of the clock signal is N / 2 from the first printed circuit layer.
The liquid crystal display device according to claim 3, wherein the liquid crystal display device is arranged on one of the printed circuit layers within a layer. 6. The laminated structure comprises six or more printed circuit layers, and a transmission line of the clock signal is one of the printed circuit layers adjacent to the first printed circuit layer or other than the one adjacent to the first printed circuit layer. The liquid crystal display device according to claim 5, wherein the liquid crystal display device is disposed in the printed circuit layer. 7. The liquid crystal display according to claim 3, wherein said laminated thickness is defined as a distance from said first printed circuit layer to said printed circuit layer at the other end of said laminated structure. apparatus. 8. The liquid crystal display device according to claim 3, wherein said clock signal has a frequency higher than 10 MHz. 9. The liquid crystal display device according to claim 3, wherein said clock signal has a frequency of 15 MHz or more. 10. Each of the control units of the first drive circuit has a sequential logic circuit therein, and the sequential logic circuit responds to the clock signal by the electrode corresponding to the first drive circuit. 4. The liquid crystal display device according to claim 3, wherein a control signal for controlling application of a voltage to each of the first and second components is output. 11. The apparatus of claim 3, wherein the first printed circuit layer supplies a second clock signal having a frequency different from the clock signal to each of the first circuits in parallel. Liquid crystal display device. 12. The printed circuit layer, wherein the second clock signal has a lower frequency than the clock signal and is transmitted on a second transmission line disposed on one of the printed circuit layers. 12. The clock signal transmission line as set forth above, wherein the transmission line is separated from the transmission line.
3. The liquid crystal display device according to 1. 13. A transmission line for the clock signal and the second clock signal on one of the printed circuit layers, wherein the transmission line for the clock signal and the second clock signal is connected to a corresponding electrical contact formed on the first printed circuit layer. 13. The liquid crystal display device according to claim 12, wherein the liquid crystal display devices are connected by respective through holes extending from one printed circuit layer to one of the printed circuit layers. 14. The lead for transmitting the clock signal, wherein the clock signal and the second clock signal transmission line on one of the printed circuit layers are connected to the respective through holes by individual leads. 14. The liquid crystal display device according to claim 13, wherein is shorter than the lead for transmitting the second clock signal. 15. The first printed circuit board supplies a third clock signal having a higher frequency than the clock signal, wherein the third clock signal is transmitted from the printed circuit board on which a transmission line of the clock signal is arranged. The liquid crystal display device according to claim 3, wherein the transmission is performed by a transmission line disposed on one of the printed circuit layers remote from the first printed circuit board. 16. The panel according to claim 15, further comprising a plurality of switching elements disposed on the panel, wherein each of the first electrodes controls switching of the corresponding switching element. Liquid crystal display device. 17. The printed circuit board, wherein the first printed circuit board supplies a third clock signal having a higher frequency than the clock signal, wherein the third clock signal is a printed circuit layer on which a transmission line of the clock signal is arranged. 4. The liquid crystal display device according to claim 3, wherein the clock signal is transmitted via a third transmission line disposed above the third transmission line, and the transmission line for the clock signal is separated from the third transmission line. 5. 18. The panel according to claim 17, further comprising a plurality of switching elements disposed on the panel, wherein each of the first electrodes controls switching of the corresponding switching element. Liquid crystal display. 19. At least one transmission line for transmitting a signal other than the clock signal is further arranged on the printed circuit board such that a signal other than the clock signal is supplied in parallel to each first circuit. The transmission line of the clock signal is separated from the transmission line of the signal other than the clock signal by at least one conductive material that is not electrically connected to any of the transmission line of the clock signal and the transmission line of the signal other than the clock signal. The liquid crystal display device according to claim 3, wherein: 20. A transmission line for transmitting said clock signal is disposed on one of said printed circuit layers other than said first printed circuit board, and is connected to an electrical contact formed on said first printed circuit layer. 20. A connection made by a contact hole extending from a first printed circuit layer to one of the printed circuit layer signals, at least a region connecting the transmission line and the through hole is surrounded by the conductive material. 3. The liquid crystal display device according to 1. 21. At least one of the transmission lines for transmitting signals other than the clock signal is provided on the printed circuit layer further away from the first printed circuit layer than the printed circuit layer on which the transmission line for the clock signal is arranged. The liquid crystal display device according to claim 19, wherein the liquid crystal display device is arranged at a position. 22. At least one of said transmission lines transmits at least one image signal, and at least one control unit in said first drive circuit fetches and arranges said image signal in correspondence with said clock signal. 20. The liquid crystal display device according to claim 19, wherein: 23. The panel according to claim 23, wherein a plurality of switching elements are further disposed on the panel, and each of the first electrodes is electrically connected to a terminal of each of the corresponding switching elements. 23. The liquid crystal display device according to 22.