JPS63250264A - One-dimensional solid-state pickup element having plural analog shift registers - Google Patents

Abstract

PURPOSE:To simultaneously read out each signal load by respectively transferring the signal charges in a different charge accumulating time to plural separate analog shift registers through shift gates in parallel. CONSTITUTION:The plural shift gates 3 and the plural analog shift resisters 4 are alternately arranged in order that the signal charges can be sequentially transferred in parallel from a photosensitive picture element string 2 and the signal charges in different charge accumulating time are separately and respectively transferred in parallel to plural analog shift registers 4 through the shift gates 3. After B, G and R signal charges are respectively transferred in parallel to the analog shift registers 4a-4c, the B, G and R signals are simultaneously read out in series from the respective analog shift registers 4a-4c synchronously with a read clock phi. Thus, the signals of three primary colors can be simultaneously read out without increasing a reading time and deteriorating the picture quality of read pictures and also requesting a high speed circuit as the signal process circuit of a post stage.

Description

Detailed Description of the Invention (Industrial Application Field) This invention relates to a one-dimensional solid-state f1 image element such as a CD line image sensor, and particularly relates to a one-dimensional solid-state f1 image element that enables simultaneous readout of signal charges at different accumulation times. This invention relates to the structure of a solid-state imaging device.

(Prior art and its problems) In the development of a color one-plane scanner that reads color original images by plane scanning using a COD line image sensor (referred to as lower COD), R (red).

A major challenge is how to separate and read the three primary color components of G (green) and B (blue). The method is as follows:
It is broadly divided into

(Method 1) Using COD 1, R, G, and B color signals are read in a time-division manner. Therefore, the three light sources of R, G, and B are turned on sequentially, or the light source is a white light and the R, G light sources are turned on in the middle of the optical path to the COD.

A mechanism such as a rotating filter is provided to sequentially switch the filters B.

(Method 2) Three CODs dedicated to each of R, G, and B are arranged so as to read the same position on the original image, and the three primary color signals are read simultaneously.

In the case of method 2, the cost is high because three CODs are required, and there is a problem of image quality deterioration due to misalignment of each COD. On the other hand, in the case of method 1, although there is no such problem, the reading time is tripled because the three primary color signals are read in a time-division manner.

Therefore, in Method 1, a third method can be considered in which the increase in the reading time is avoided by increasing the intensity of the illumination light, reducing the charge accumulation time to 1/3, and tripling the readout clock frequency given to the COD. , Image quality deteriorates due to a decrease in the transfer efficiency of the analog shift register due to high-speed readout and an increase in noise, i.e., a decrease in S/N, and a high-speed signal processing circuit (especially an A/D converter) is required in the subsequent stage. This poses a problem of complicating the circuit and increasing cost.

In addition, in method 1, the three primary color signals of R, G, and B are obtained in a time-division manner, so when it is necessary to perform time signal processing between the three colors such as color calculation, as in a color scanner for plate making,
Additional memory is required to temporarily store the color signal obtained earlier and to synchronize the timing with the color signal obtained later.

(Object of the Invention) Therefore, the object of the present invention is to solve the problems of the prior art described above, and to improve the image quality of the read image without increasing the reading time when reading a color original image using one one-dimensional solid-state image element. It is an object of the present invention to provide a one-dimensional solid-state image element that does not cause deterioration in performance, does not require a high-speed signal processing circuit in the subsequent stage, and is capable of simultaneously reading three primary color signals.

(Means for Achieving the Object) In order to achieve the above object, the present invention provides a linear image in which signal charges accumulated in a photosensitive pixel column are transferred in parallel to an analog shift register via a shift gate and read out in series. In the sensor, a plurality of the shift gates and analog shift registers are arranged alternately so that signal charges can be sequentially transferred in parallel from the photosensitive pixel row, and signal charges at different charge accumulation times are transferred to the shift gates. These signals can be read out simultaneously by transferring them in parallel to different ones of a plurality of analog shift registers.

In other words, since this invention is equipped with a plurality of analog shift registers, the R and G signals accumulated by strong illumination light within a charge accumulation time that is sufficiently shorter than the processing time for one line.
, B can be transferred to separate analog shift registers and read out simultaneously relatively slowly within one line processing time.

(Example) FIG. 1 is an explanatory diagram showing the configuration of a COD which is an example of a one-dimensional solid-state image sensor according to the present invention.

CCDI is a photosensitive pixel row 2 consisting of a photodiode array.
and a first shift gate 3a for this photosensitive pixel row 2.
, a first analog shift register 4a.

Second shift gate 3b, second analog shift register 4
b. A third shift gate 3C9 and a third analog shift register 4C are connected in order to transfer the signal charge of each pixel accumulated in the photosensitive pixel column 2 to each analog shift register 4a, 4b.
, 4C so that they can be sequentially transferred in parallel.

The shift gates 3a, 3b, 3G have control terminals 5a, 5b.
, 5c are externally applied with shift gate control signals SH, SH, .SHc, and each shift gate 3a, 3b, 3c forms a charge transfer path in response thereto. The signal charges transferred in parallel to the predetermined analog shift registers 4a, 4b, and 4c through this charge transfer path are synchronized with the read clock φ externally applied through the control terminal 6, and the signal charges are transferred in parallel to the predetermined analog shift registers 4a, 4b, and 4c.
4b and 4c simultaneously in series, and the output amplifier 7a
, 7b, 7c, the data output terminals 8a, 8
b, led out to the outside through 8C.

FIG. 2 is a timing diagram showing an example of the operation timing when the CCD 1 shown in FIG. 1 reads a color original image. CCD1
A configuration in which one light source is used and the three primary color light sources of RlG and B are sequentially switched, or a single white light source is used and CCD
Insert R, G, and B filters in the middle of the optical path up to 1,
The configuration is such that these are sequentially switched. In either case, the intensity of the illumination light is set to be sufficiently strong, and the required charge accumulation time is set to be sufficiently smaller than the processing time for one line.

In FIG. 2(a), tc is the charge accumulation time set as described above, and t is the one-line processing time.

The first charge accumulation time t of one line processing time t. , R signal charges are accumulated in the photosensitive pixel row 2 of ccoi, and these R signal charges are shown in FIGS. 2(b), (c), and (d).
Shift gate control pulse 5H81, 5H shown in
In response to b1 and 5HC1, the signals are sequentially transferred in parallel from the first analog shift register 4a to the second analog shift register 4b to the third analog shift register 4C. Next, at the second charge accumulation time tc of the one-line processing time t, G signal charges are accumulated in the photosensitive pixel row 2 of the CCD 1,
This G signal charge responds to the shift gate control pulse SHSH shown in FIGS. 2(b) and 2(c).
b2 are sequentially transferred in parallel from the first analog shift register 4a to the second analog shift register 4b.

Then, the third charge accumulation time t of one line processing time t
At C, a B signal@charge is accumulated in the photosensitive pixel column of the CCD 1, and this B signal charge is transferred in parallel to the first analog shift register 4a in response to the shift gate control pulse 5H33 shown in FIG. 2(b). Ru.

In this way, the first. Second. B and G in the third analog shift registers 4a, 4b, and 4c, respectively.

After the R signal charges are transferred in parallel, B and G are transferred from each analog shift register 4a, 4b, 4c, respectively, in synchronization with the read clock φ shown in FIG. 2(e).

The R signals are simultaneously read out in series. B read out.

After the G and R signals are amplified by output amplifiers 7a, 7b, and 7c, they are simultaneously led out to the outside through data output terminals 8a, 8b, and F1a, as shown in FIG. 2(f), (a), and (h). Ru. Since the read time tR is relatively long and the frequency of the read clock φ does not need to be much higher than in the past, there is no reduction in the transfer efficiency of the analog shift registers 4a, 4b, 4c, and there is no increase in noise, that is, S/
Since there is no decrease in N, the quality of the read image does not deteriorate. Also, the subsequent signal processing circuit (especially A/D
Since a high-speed converter (converter) is not required, there is no need to complicate the circuit or increase costs.In addition, R, G, and B signals can be obtained simultaneously, making it easy to perform color calculations like a color scanner for plate making. Even when performing three-color signal processing simultaneously, there is no need to provide a special configuration for timing alignment of each color signal.

In FIG. 2, the charge accumulation time tc is shorter than 1/3 of the one-line processing time t. This produces other effects as follows.

That is, since sub-scanning is normally performed at a constant speed, if the R, G, and B signals are read at different times, the positions of the read lines will be slightly shifted.

This shift may pose a problem as color shift in high-quality color images. In order to reduce this deviation, it is sufficient to read the R, G, and B signals at times as close as possible in a short time, and the timing shown in FIG. 2 is exactly such. .

FIG. 3 is an explanatory diagram showing another configuration example of CCDI. The CCD 1 according to this embodiment has two sets of shift gates 3a, 3b, ac and analog shift registers 4a, 4b, 4C connected alternately to the photosensitive pixel row 2 (as indicated by subscripts 1 and 2 at the lower right of the symbol). (distinguish each set). The terminal 9 is an input terminal for the switching control signal Sc of the switches 10a to 10g, and its It HIT level and "L I
Each of the switches 10a to 10 (l is connected to the side indicated by symbol H1 in the figure) according to the T level.

FIG. 4 is a timing chart showing an example of the operation timing when reading a color original image using one CCD 1 shown in FIG. 3, and the light source has the same configuration as in FIGS. 1 and 2 described above. t, is the charge accumulation time, and t' is the one-line processing time. As is clear from a comparison with FIG. 2, in this embodiment, the one-line processing time t,' is considerably shorter than t in FIG. 2, and high-speed reading is possible. However, since the readout time t' is correspondingly shortened, problems such as noise arise, so this method is suitable when high speed is given priority over the quality of the read image.

During the “HI+” period of the switching control signal Sc in FIG. 4(b), the shift gate control signals SH, ˜SH are
The read clock φ is applied to the second set of all-log shift registers 4a, 4b2, 4c, . Therefore, the data accumulated in the photosensitive pixel row 2 as shown in FIG.
The R signal charge of the first line 11 shown in FIG.
(di, (e) shift gate control pulse 5
In response to t-181, 8t-1b1.81-161, the analog shift register 4c1 changes the G signal charge to SHa?
In response to 5Hb2, the analog shift register 4b1
Charge No. 88 is transferred in parallel to analog shift registers 4a and 4a in response to 5H33, and transferred in parallel to analog shift registers 4a and 211, 4b2 and 4C2 by scanning the 0th line 1° just before. 8. The double high load of G and R is applied to each analog shift register 4a2, 4b2, 4 in synchronization with the read clock φ.
They are simultaneously read from c2.

On the other hand, the switching control signal S in FIG. 4(b). Ill of L''
], the shift gate control signals SH8 to ST1° are applied to the second set of shift gates 3a, 3b2, 3C2.
The read clock φ is applied to the first dark blue analog shift registers 4a, 4b1, and 4C1. Therefore, contrary to the above, R and G of the M2 line 12 accumulated in the photosensitive pixel column 2.

The B signal charge is transferred to the second set of analog shift registers 4C2,
4b2, 4a2, and the first set of analog shift registers 4a1.4b, 4c.
From 1 to B on the first line 11.

Simultaneous reading of G and R signals is performed. Figure 4(f),
(g) and (h) are connected to the data output terminal 8 in this way.
a.

Each line j! derived from 8b and 8c! . -12 color signals are shown.

In the above embodiment, the shift gate control signal @
SH, st-+, , SHo are each one pulse for one transfer. However, it is known that the transfer efficiency is slightly deteriorated especially in the transfer from the photosensitive pixel row 2 to the analog shift registers 4a, 4a1, 4a2, and in order to solve this problem, the shift gate control signal SHa is set to 1.
Each pulse may be multiple times for multiple transfers. In this case, at the end of the application of the plurality of pulses, shift gate control pulses 5Hb1, 5Hb2°5Hc for the next transfer are applied.
1 will be given. Furthermore, not only the shift gate control signal SH, but also the shift gate control signals SHb and SHc may each have a plurality of pulses for one transfer.

FIG. 5 is an explanatory diagram showing still another example of the configuration of the CCD 1. The CCD 1 according to this embodiment includes an adder circuit 11 that takes the sum of signals simultaneously read out from each analog shift register 4a, 4b, and 4c, and a divider circuit 12 that divides the output by 1/3 to obtain an averaged signal. has. S of the image signal obtained by reading an image of one line of a monochrome original image multiple times (three times in the illustrated example) using the CCD 1 having such a configuration and outputting an averaged signal from the data output terminal 13. /N can be improved. If such an operation is performed with a COD with a conventional configuration, the processing speed will decrease due to multiple readings, and if the reading speed is increased, the reading time will be shortened, causing problems such as noise. .

Further, additional memory, etc. for timing alignment of each read signal to be added is also required. On the other hand, CC in Figure 5
According to D1, there is no such problem.

Note that the addition circuit 11 and the division circuit 12 can also be provided externally.

Although the COD line image sensor has been described as an example, the present invention can be similarly applied to other one-dimensional solid-state sensors. Further, the number of stages of the analog shift register is not limited to three stages.

(Effects of the Invention) As described above, according to the present invention, when reading a color original image using one one-dimensional solid-state 111 image element, the reading time does not increase and the quality of the read image does not deteriorate. Furthermore, a high-speed signal processing circuit is not required in the subsequent stage, and in addition, a one-dimensional solid-state image carrier capable of simultaneously reading three primary color signals can be obtained.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is an operation timing diagram thereof, FIG. 3 is a configuration explanatory diagram showing another embodiment, FIG. 4 is an operation timing diagram thereof, and FIG. The figure is a configuration explanatory diagram showing still another embodiment. 1...COD line image sensor 2...Photosensitive pixel rows 3a, 3b, 3c...Shift gates 4a, 4b, 4c...7 Og shift register SH3
, SHb, SHc...Shift gate control signal φ...Readout 0ts

Claims (2)

[Claims] (1) In a one-dimensional solid-state image sensor in which signal charges accumulated in a photosensitive pixel column are transferred in parallel to an analog shift register via a shift gate and read out in series, it is possible to sequentially transfer signal charges from the photosensitive pixel column in parallel. A plurality of the shift gates and analog shift registers are arranged alternately in the plurality of shift gates, and signal charges at different charge accumulation times are transferred in parallel to separate ones of the plurality of analog shift registers via the shift gates. 1. A one-dimensional solid-state image sensor having a plurality of analog shift registers, characterized in that the signal charges of the two signals can be read out simultaneously. (2) Claim 1 characterized in that it has two sets of a plurality of shift gates and analog shift registers arranged alternately, and these are switched and used in a time division manner.
A one-dimensional solid-state image sensor having a plurality of analog shift registers as described in 1.