JPS6324989U - - Google Patents
Info
- Publication number
- JPS6324989U JPS6324989U JP11816586U JP11816586U JPS6324989U JP S6324989 U JPS6324989 U JP S6324989U JP 11816586 U JP11816586 U JP 11816586U JP 11816586 U JP11816586 U JP 11816586U JP S6324989 U JPS6324989 U JP S6324989U
- Authority
- JP
- Japan
- Prior art keywords
- switching controller
- power supply
- synchronization signal
- oscillation
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 claims 4
- 238000007599 discharging Methods 0.000 claims 1
- 230000007717 exclusion Effects 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Dc-Dc Converters (AREA)
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例にかかる周波数同期
回路図、第２図はスイツチングレギユレータ用コ
ントローラＩＣの回路構成図、第３図は第２図の
発振器回路、第４図はそのＣＴ端子波形図、第５
図は第１図の動作を説明するための各部の波形図
である。
１；外部同期用入力端子、２，４及び７；フリ
ツプフロツプ（Ｆ／Ｆ）、３；排他的論理和回路
、５；スイツチングレギユレータ用コントローラ
ＩＣ、６；トランス、８及び９；ＤＣ入力端子及
び出力端子、Ｑ１，Ｑ２，Ｑ３；トランジスタ、
ＲＴ；抵抗、ＣＴ；コンデンサ、Ｒ１；電流制御
用抵抗。
Fig. 1 is a frequency synchronization circuit diagram according to an embodiment of the present invention, Fig. 2 is a circuit configuration diagram of a controller IC for a switching regulator, Fig. 3 is an oscillator circuit shown in Fig. 2, and Fig. 4 is its oscillator circuit. CT terminal waveform diagram, 5th
The figure is a waveform diagram of each part for explaining the operation of FIG. 1. 1: Input terminal for external synchronization, 2, 4 and 7: Flip-flop (F/F), 3: Exclusive OR circuit, 5: Controller IC for switching regulator, 6: Transformer, 8 and 9: DC input terminals and output terminals, Q 1 , Q 2 , Q 3 ; transistors;
RT: resistor, CT: capacitor, R 1 : current control resistor.
Claims (1)
ローラにおいて、該スイツチング電源の発振周期
パルスを方形波出力に変換する手段と同時に外部
からの同期信号を方形波に変換する手段と、該両
方形波出力の排他的論理和をとる手段と、その出
力レベル（ＨまたＬレベル）により前記スイツチ
ングコントローラの発振器に接続されたコンデン
サの充放電を行う手段と、該スイツチングコント
ローラの発振周期と、前記外部からの同期信号と
比較してその充電電圧を制御することにより前記
発振器に接続された抵抗端子に流れる電流を可変
制御する手段とを備え、前記スイツチングコント
ローラの発振周期を外部からの同期信号に同期さ
せるようにしたことを特徴とするパルス幅変調方
式電源の周波数同期回路。 A switching controller for a pulse-width modulation power supply, comprising a means for converting an oscillation periodic pulse of the switching power supply into a square wave output, and a means for simultaneously converting an external synchronization signal into a square wave, and exclusion of both of the wave outputs. means for calculating a logical OR, means for charging and discharging a capacitor connected to the oscillator of the switching controller according to its output level (H or L level), an oscillation period of the switching controller, and a means for calculating the oscillation period from the outside. means for variably controlling the current flowing through the resistor terminal connected to the oscillator by comparing the charging voltage with a synchronization signal, and synchronizing the oscillation cycle of the switching controller with the synchronization signal from the outside. A frequency synchronization circuit for a pulse width modulation power supply, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11816586U JPH0746068Y2 (en) | 1986-07-30 | 1986-07-30 | Pulse width modulation power supply frequency synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11816586U JPH0746068Y2 (en) | 1986-07-30 | 1986-07-30 | Pulse width modulation power supply frequency synchronization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324989U true JPS6324989U (en) | 1988-02-18 |
| JPH0746068Y2 JPH0746068Y2 (en) | 1995-10-18 |
Family
ID=31004361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11816586U Expired - Lifetime JPH0746068Y2 (en) | 1986-07-30 | 1986-07-30 | Pulse width modulation power supply frequency synchronization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746068Y2 (en) |
-
1986
- 1986-07-30 JP JP11816586U patent/JPH0746068Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746068Y2 (en) | 1995-10-18 |
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