JPS62195803U - - Google Patents
Info
- Publication number
- JPS62195803U JPS62195803U JP8090986U JP8090986U JPS62195803U JP S62195803 U JPS62195803 U JP S62195803U JP 8090986 U JP8090986 U JP 8090986U JP 8090986 U JP8090986 U JP 8090986U JP S62195803 U JPS62195803 U JP S62195803U
- Authority
- JP
- Japan
- Prior art keywords
- photocoupler
- programmable controller
- switch
- alternating current
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Programmable Controllers (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案のプログラマブルコントローラ
の実施例図、第２図はその動作を説明するための
タイムチヤート、第３図は本考案のピーク検出回
路の一実施例図、第４図は従来のプログラマブル
コントローラの構成図、第５図はその動作説明の
ためのタイムチヤートである。
１…入力インピーダンス、２…全波整流回路、
３…フオトカプラ、４…積分回路、５…ヒイテリ
シス回路、６…データバツフア、９…交流電源、
２６…ピーク検出回路、３７…データ保持回路、
５３…反転回路。
Fig. 1 is an embodiment of the programmable controller of the present invention, Fig. 2 is a time chart for explaining its operation, Fig. 3 is an embodiment of the peak detection circuit of the present invention, and Fig. 4 is a conventional one. FIG. 5, which is a block diagram of the programmable controller, is a time chart for explaining its operation. 1...Input impedance, 2...Full wave rectifier circuit,
3...Photocoupler, 4...Integrator circuit, 5...Hyteresis circuit, 6...Data buffer, 9...AC power supply,
26...Peak detection circuit, 37...Data holding circuit,
53...Inversion circuit.
Claims (1)
起されるフオトカプラ、およびこのフオトカプラ
の出力信号により前記スイツチの開閉状態を２値
の論理値で検出する交流入力回路を備えたプログ
ラマブルコントローラにおいて、前記交流信号と
同相の交流電圧から最大値の位相にてパルス信号
を発生するピーク検出回路と、前記パルス信号に
より前記フオトカプラの論理出力信号を読み込む
データ保持回路を設けたことを特徴とするプログ
ラマブルコントローラ。 A programmable controller equipped with a photocoupler excited by an alternating current signal inputted through a switch, and an alternating current input circuit that detects the open/closed state of the switch using binary logical values based on the output signal of the photocoupler. A programmable controller comprising: a peak detection circuit that generates a pulse signal at a maximum phase from an AC voltage of the same phase; and a data holding circuit that reads a logical output signal of the photocoupler using the pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8090986U JPS62195803U (en) | 1986-05-30 | 1986-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8090986U JPS62195803U (en) | 1986-05-30 | 1986-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62195803U true JPS62195803U (en) | 1987-12-12 |
Family
ID=30932150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8090986U Pending JPS62195803U (en) | 1986-05-30 | 1986-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62195803U (en) |
-
1986
- 1986-05-30 JP JP8090986U patent/JPS62195803U/ja active Pending
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