JPS63244868A - Substrate for thin film hybrid ic - Google Patents
Substrate for thin film hybrid icInfo
- Publication number
- JPS63244868A JPS63244868A JP62079258A JP7925887A JPS63244868A JP S63244868 A JPS63244868 A JP S63244868A JP 62079258 A JP62079258 A JP 62079258A JP 7925887 A JP7925887 A JP 7925887A JP S63244868 A JPS63244868 A JP S63244868A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resistance
- substrate
- film
- zrn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 73
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 abstract description 6
- 229910004479 Ta2N Inorganic materials 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 229920000136 polysorbate Polymers 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は同一基板上に、絶縁膜を介在して抵抗体薄膜を
多層に形成してなる薄膜ハイブリッドＩＣ用基板に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a thin film hybrid IC substrate in which multiple resistor thin films are formed on the same substrate with an insulating film interposed therebetween.
「従来の技術」
従来のハイブリッドＩＣに用いられる抵抗体としての薄
膜は、１枚の基板上には単一の比抵抗のものが形成され
ていた０例えば高抵抗薄膜で高抵抗体を得るには第５図
（ａ）のように電極（１）（２）間に、細い高抵抗薄膜
（３ａ）を介在させ、同じく高抵抗薄膜で低抵抗体を得
るには第５図（ｂ）のように幅広の電極（１） （２）
間に、同様に幅の広い高抵抗薄膜（３ｂ）を介在させ、
また、低抵抗薄膜で低抵抗体を得るには第６図（ａ）に
示すように電極（１）（２）間に短かい低抵抗薄膜（４
ａ）を介在させ、同じく低抵抗薄膜で高抵抗体を得るに
は第６図（ｂ）に示すように細長い低抵抗薄膜（４ｂ）
を屈曲して介在させていた。``Prior art'' Conventional thin films as resistors used in hybrid ICs have a single specific resistance formed on one substrate. As shown in Fig. 5(a), a thin high-resistance thin film (3a) is interposed between the electrodes (1) and (2), and in order to obtain a low-resistance element with the same high-resistance thin film, the method shown in Fig. 5(b) is used. Wide electrode (1) (2)
In between, a similarly wide high-resistance thin film (3b) is interposed,
In addition, in order to obtain a low-resistance element using a low-resistance thin film, a short low-resistance thin film (4
In order to obtain a high-resistance element with a low-resistance thin film by interposing a), an elongated low-resistance thin film (4b) is used as shown in FIG. 6(b).
was bent and interposed.
「発明が解決しようとする問題点」
しかるに、従来のように単一の比抵抗のものを用いる方
法では、高抵抗薄膜を用いた場合には高抵抗体を得るの
はよいが、低抵抗体を得るには第５図（ｂ）のように全
体の面積を大きくしなければならず、逆に低抵抗薄膜を
用いた場合には低抵抗体を得るにはよいが、高抵抗体を
得るには第６図（ｂ）のように屈曲しているためやはり
全体として大きな面積を必要とするという問題があった
。抵抗値を膜厚で調整しようとすると膜厚の薄いものは
熱的安定性に欠けるという問題点があった。``Problem to be solved by the invention'' However, with the conventional method of using a single specific resistance, it is possible to obtain a high resistance object when a high resistance thin film is used, but it is difficult to obtain a low resistance object. In order to obtain this, the overall area must be increased as shown in Figure 5(b), and conversely, if a low-resistance thin film is used, it is good to obtain a low-resistance element, but it is difficult to obtain a high-resistance element. Since it is bent as shown in FIG. 6(b), there is still a problem in that it requires a large area as a whole. When attempting to adjust the resistance value by adjusting the film thickness, there is a problem in that thin films lack thermal stability.
「問題点を解決するための手段」
本発明は上述のような問題点を解決するためになされた
もので、１枚の基板上に、抵抗体薄膜を形成し、この抵
抗体薄膜の一部に重合するように順次絶縁膜を介在させ
て抵抗体薄膜を多層に形成してなるものである。"Means for Solving the Problems" The present invention has been made to solve the above-mentioned problems, and includes forming a resistor thin film on one substrate, and forming a part of the resistor thin film on a single substrate. The resistor thin film is formed in multiple layers by sequentially interposing insulating films so that the resistor thin films are polymerized.
「作用」
１枚の基板上全体にまず高抵抗ＺｒＮ薄膜を形成し、こ
の薄膜の一部分に絶縁膜を介在して低抵抗Ｔａ２Ｎ薄膜
を形成する。すると、高抵抗ＺｒＮ薄膜だけの層の部分
は高抵抗体となり、高抵抗ＺｒＮ薄膜と低抵抗Ｔａ、Ｎ
簿膜の２層の部分は低抵抗値となる。上層の抵抗体薄膜
は下層の抵抗体薄膜との間に絶縁膜が介在されているの
で、エツチング等の加工によって抵抗値調整、パターン
変更等ができる。これによって抵抗体パターンを最小に
形成できる。"Operation" First, a high-resistance ZrN thin film is formed on the entire surface of one substrate, and a low-resistance Ta2N thin film is formed on a portion of this thin film with an insulating film interposed therebetween. Then, the part of the layer consisting only of the high resistance ZrN thin film becomes a high resistance body, and the layer consisting of the high resistance ZrN thin film and the low resistance Ta, N
The two-layer portion of the film has a low resistance value. Since an insulating film is interposed between the upper resistor thin film and the lower resistor thin film, the resistance value can be adjusted, the pattern can be changed, etc. by processing such as etching. This allows the resistor pattern to be formed to a minimum size.
「実施例」 以下、本発明の一実施例を図面に基づき説明する。"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.
第３図は１枚の基板（５）上に、所定の間隔で多数の薄
膜ハイブリッドＩＣ用基板（５ａ）、（５ｂ）・・・を
形成したもので、その１チツプが第４図（ａ）（ｂ）に
示されるように、基板（５）の上面全体にまず高抵抗Ｚ
ｒＮ薄膜（６）を形成し、その上面の一部に絶縁膜（７
）を介在して低抵抗Ｔａ、Ｎ薄膜（８）を形成する。In Figure 3, a large number of thin film hybrid IC substrates (5a), (5b), etc. are formed at predetermined intervals on one substrate (5), and one chip is shown in Figure 4 (a). ) As shown in (b), a high resistance Z is first applied to the entire upper surface of the substrate (5).
An rN thin film (6) is formed, and an insulating film (7) is formed on a part of its upper surface.
) is formed to form a low resistance Ta,N thin film (8).
このような構成とすることにより、高抵抗ＺｒＮ薄膜（
６）だけの１層の部分（９）は高抵抗体となる。With this configuration, a high resistance ZrN thin film (
The single layer portion (9) of 6) becomes a high resistance material.
高抵抗ＺｒＮ薄膜（６）の上部に絶縁膜（７）を介在し
て低抵抗Ｔａ、Ｎ薄膜（８）を形成して２層とした部分
（１０）は低抵抗体となる。このようにした形成された
ＩＣは、中間に絶縁膜（７）が介在しているので、低抵
抗Ｔａ、Ｎ薄膜（８）の部分のエツチング等の加工処理
が可能となる。A low-resistance Ta,N thin film (8) is formed on top of a high-resistance ZrN thin film (6) with an insulating film (7) interposed therebetween, and a two-layered portion (10) becomes a low-resistance body. Since the thus formed IC has the insulating film (7) interposed in the middle, processing such as etching of the low resistance Ta and N thin film (8) can be performed.
以上の薄膜ハイブリッドＩＣ用基板を作成するための第
１実施例を説明すると、まず第１図（ａ）に示すように
、基板（５）の上面に、高抵抗ＺｒＮ薄膜（６）をスパ
ッタリング法により成膜する。ついで、第１図（ｂ）に
示すように、高抵抗ＺｒＮ薄膜（６）の一部に印刷によ
り絶縁膜（７）を形成する。つぎに、第１図（ｅ）に示
すように、残りの部分をマスク（１１）により被覆し、
前記絶縁膜（７）の部分に低抵抗Ｔａ、Ｎ薄膜（８）を
スパッタリング法により成膜する。成膜後、前記マスク
（１１）を取除くと第１図（ｄ）のような薄膜ハイブリ
ッドＩＣ用基板が得られる。To explain the first embodiment for producing the above-mentioned thin film hybrid IC substrate, first, as shown in FIG. A film is formed by Then, as shown in FIG. 1(b), an insulating film (7) is formed on a part of the high resistance ZrN thin film (6) by printing. Next, as shown in FIG. 1(e), the remaining part is covered with a mask (11),
A low resistance Ta,N thin film (8) is formed on the insulating film (7) by sputtering. After film formation, the mask (11) is removed to obtain a thin film hybrid IC substrate as shown in FIG. 1(d).
つぎに、薄膜ハイブリッドＩＣ用基板を作成するための
第２実施例を説明すると、まず、第２図（ａ）に示すよ
うに基板（５）の上面に、高抵抗ＺｒＮ薄膜（６）をス
パッタリング法により成膜する。ついで、第１図（ｂ）
に示すように、高抵抗ＺｒＮ薄膜（６）の全面にスパッ
タリングにより絶縁膜（７）を形成する。さらに第２図
（Ｃ）に示すようにこの絶縁膜（７）の全面に低抵抗Ｔ
ａ、Ｎ薄膜（８）をスパッタリング法により成膜する。Next, a second example for producing a thin film hybrid IC substrate will be explained. First, as shown in FIG. 2(a), a high resistance ZrN thin film (6) is sputtered on the upper surface of a substrate (5). The film is formed by the method. Next, Figure 1(b)
As shown in FIG. 2, an insulating film (7) is formed on the entire surface of the high-resistance ZrN thin film (6) by sputtering. Furthermore, as shown in FIG. 2(C), a low resistance T is provided on the entire surface of this insulating film (7).
a, N thin film (8) is formed by sputtering.
ついで、第２図（ｄ）に示すように、低抵抗Ｔａ、Ｎ薄
膜（８）を選択エツチングにより不要な部分を取除く。Then, as shown in FIG. 2(d), unnecessary portions of the low resistance Ta, N thin film (8) are removed by selective etching.
さらに第２図（ｅ）のように絶縁膜（７）も不要部分を
エツチングにより取除くと薄膜ハイブリッドＩＣ用基板
が完成する。Further, as shown in FIG. 2(e), unnecessary portions of the insulating film (7) are also removed by etching to complete the thin film hybrid IC substrate.
前記実施例では高抵抗体をＺｒＮ、低抵抗体をＴａ、Ｎ
としたが、ＺｒＮを用い窒素ガス流量で制御して高抵抗
体と低抵抗体を得るようにしてもよい、また、前記実施
例では抵抗体を２層としたが、さらに中抵抗体を介在さ
せて３層以上とすることもできる。In the above embodiment, the high resistance material is ZrN, and the low resistance material is Ta, N.
However, it is also possible to use ZrN and control the flow rate of nitrogen gas to obtain a high resistance element and a low resistance element.Also, in the above example, the resistor was made of two layers, but a medium resistance element may be further interposed. It is also possible to have three or more layers.
「発明の効果」
本発明は上述のように、高抵抗薄膜と低抵抗薄膜との間
に絶縁膜を介在させたので、上層の抵抗体薄膜をエツチ
ング等が加工でき、薄膜抵抗体の抵抗値調整、パターン
の変更が自由にでき、しかもパターン面積が最小の薄膜
抵抗体を得ることができる。"Effects of the Invention" As described above, in the present invention, an insulating film is interposed between a high resistance thin film and a low resistance thin film, so that the upper resistor thin film can be processed by etching, etc., and the resistance of the thin film resistor can be increased. Adjustment and pattern changes can be made freely, and a thin film resistor with a minimum pattern area can be obtained.
第１図は本発明による薄膜ハイブリッドＩＣ用基板の作
成順序の第１実施例の説明図、第２図は同上第２実施例
の説明図、第３図は１枚の基板に多数のＩＣを形成した
例を示す平面図、第４図（ａ）は１チツプの平面図、第
４図（ｂ）は第４図（ａ）の断面図、第５図および第６
図は従来の薄膜抵抗体の使用状態を示す平面図である。
（１） （２） ・・・電極、（３ａ） （３ｂ） （
６）−高抵抗ＺｒＮ薄膜、（４ａ）（４ｂ） （８）−
低抵抗Ｔａ、Ｎ薄膜、（５）・・・基板、（５ａ） （
５ｂ）〜・・・１チツプ、（７）・・・絶縁膜、（９）
・・・高抵抗体部分、（１０）・・・低抵抗体部分、（
１１）・・・マスク。
出願人 株式会社富士通ゼネラル
手続補正書（自船
昭和６２年０６月Ｏ？日
特許庁長官 黒 １）明 雄 殿
■、事件の表示
昭和６２年特許願第０７９２５８号
２、発明の名称
薄膜ハイブリッドＩＣ用基板
３、補正をする者
事件との関係 特許出願人
住 所 神奈川県用崎市高津区末長１１１６番地名
称 （６６１）株式会社富士通ゼネラル代表者古川志
部
４、代理人FIG. 1 is an explanatory diagram of the first embodiment of the manufacturing order of a thin film hybrid IC substrate according to the present invention, FIG. 2 is an explanatory diagram of the second embodiment of the same, and FIG. FIG. 4(a) is a plan view of one chip, FIG. 4(b) is a sectional view of FIG. 4(a), and FIGS.
The figure is a plan view showing how a conventional thin film resistor is used. (1) (2) ...electrode, (3a) (3b) (
6) - High resistance ZrN thin film, (4a) (4b) (8) -
Low resistance Ta, N thin film, (5)...substrate, (5a) (
5b)...1 chip, (7)...insulating film, (9)
...High resistance part, (10)...Low resistance part, (
11)...Mask. Applicant: Fujitsu General Co., Ltd. Procedural Amendment (own ship June 1985, Japan Patent Office Commissioner Black 1) Mr. Akira Yu, Indication of the case 1988 Patent Application No. 079258 2, Name of the invention Thin film hybrid IC Application board 3, relationship with the case of the person making the amendment Patent applicant address 1116 Suenaga, Takatsu-ku, Yozaki City, Kanagawa Prefecture
Name (661) Fujitsu General Ltd. Representative Shibe Furukawa 4, Agent
Claims (3)
体薄膜の一部に重合するように順次絶縁膜を介在させて
抵抗体薄膜を多層に形成してなることを特徴とする薄膜
ハイブリッドＩＣ用基板。(1) A resistor thin film is formed on a single substrate, and insulating films are successively interposed so as to overlap a portion of the resistor thin film, thereby forming a multilayer resistor thin film. Substrate for thin film hybrid IC.
＿２Ｎからなる特許請求の範囲第１項記載の薄膜ハイブ
リッドＩＣ用基板。(2) The high-resistance thin film is made of ZrN, and the low-resistance thin film is made of Ta.
_2N thin film hybrid IC substrate according to claim 1.
請求の範囲第１項記載の薄膜ハイブリッドＩＣ用基板。(3) The thin film hybrid IC substrate according to claim 1, wherein both the high resistance element and the low resistance element are made of ZrN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62079258A JPS63244868A (en) | 1987-03-31 | 1987-03-31 | Substrate for thin film hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62079258A JPS63244868A (en) | 1987-03-31 | 1987-03-31 | Substrate for thin film hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63244868A true JPS63244868A (en) | 1988-10-12 |
Family
ID=13684830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62079258A Pending JPS63244868A (en) | 1987-03-31 | 1987-03-31 | Substrate for thin film hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63244868A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4823929B1 (en) * | 1967-11-20 | 1973-07-17 | ||
| JPS559301A (en) * | 1978-07-01 | 1980-01-23 | Nissan Motor | Connector for igniter |
| JPS58135661A (en) * | 1982-02-08 | 1983-08-12 | Yokogawa Hokushin Electric Corp | Manufacture of integrated circuit |
| JPS61148859A (en) * | 1984-12-24 | 1986-07-07 | Hitachi Ltd | Hybrid integrated circuit device and manufacture thereof |
-
1987
- 1987-03-31 JP JP62079258A patent/JPS63244868A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4823929B1 (en) * | 1967-11-20 | 1973-07-17 | ||
| JPS559301A (en) * | 1978-07-01 | 1980-01-23 | Nissan Motor | Connector for igniter |
| JPS58135661A (en) * | 1982-02-08 | 1983-08-12 | Yokogawa Hokushin Electric Corp | Manufacture of integrated circuit |
| JPS61148859A (en) * | 1984-12-24 | 1986-07-07 | Hitachi Ltd | Hybrid integrated circuit device and manufacture thereof |
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