JPS63244374A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To miniaturize a circuit scale, to simplify wiring and to permit the titled circuit to have proof of external noise by shifting data which has been stored in a shift register constituted in a ring to two directions by a prescribed quantity and controlling the inputs and outputs of an input part and an output part. CONSTITUTION:If different kinds of data are inputted to a shift register 17a, the data is shifted in one direction by a specified quantity and the prescribed quantity of data are outputted from the output part 29. Data which have been stored in the shift register 17a are shifted in an opposite direction and the output part 27 is set to output data of the prescribed quantity. Thus, required data are outputted firstly and different kinds of data are outputted later. Thus, plural shift registers, a subtractor and the like come to be unnecessary and a processing can be executed with only one shift register 17a, whereby the circuit comes to have proof of external noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital signal processing circuit that performs data shift processing when, for example, PCM data is encoded into an ADPCM signal.

(Prior art) In general, compact discs etc. can be played back for about one hour, but there is also a demand for longer playback times, so a signal processing means for signal compression has been considered, and APCM is one such means. Alternatively, the ADPCM method is used.

For example, in ADPCM, signal components are passed through appropriate filters to compress the signal. In this case, data of the type of filter selected above is added to the signal in addition to the signal. Additionally, there is also a device that includes range data that shifts the amplitude so that it can handle large amplitude signals.

By the way, when range data is used in this way, the compressed signal may not be able to completely represent the source signal.
A discrepancy will occur. It is necessary to correct this deviation at the signal compression stage.

An example of such a correction circuit is the one shown in FIG. The circuit shown in FIG. 5 includes an emphasis filter 1, a subtracter 3, a level shift section 5, a quantization section 7, a subtracter 9, a level shift section 11, a de-emphasis filter 13, and a gain setting section 15.

The level shift unit 5 bit-shifts the signal that has passed through the emphasis filter 1 to the upper side. The quantizer 7 quantizes the level signal from the level shifter 5. The subtracter 9 subtracts the output signal of the quantizer 7 from the signal input to the quantizer 7 and sends the signal that has not been quantized by the quantizer 7 to the level shifter 11 . The signal input to the level shifter 11 is shifted to the lower side by a predetermined amount.

Next, the main operations of this circuit will be explained.

The signal that has passed through the emphasis filter 1 is shifted upward by a predetermined amount by a level shifter 5, and a quantizer 7 outputs only a limited number of bits from the most significant bits as output data. Data other than this limited number of bits is shifted to the lower side by a predetermined amount by the level shifter 11 and inputted to the subtracter 3 via the de-emphasis filter 13 as a signal for correction.

(Problems to be Solved by the Invention) However, in the conventional shift register, the circuit indicated by the dotted line in FIG. 5 needs to be configured with a counter circuit, multiple shift registers, latches, etc. The problem was that it was complex and vulnerable to noise introduced from the outside.

The present invention has been devised in view of these problems, and an object thereof is to provide a digital signal processing circuit that is small in circuit scale, has simple wiring, and is resistant to external noise.

[Configuration of the Invention (Means for Solving the Problems) To achieve the above object, the present invention provides a shift register configured in a ring shape, an input section for inputting data to the shift register, An output section that outputs the data stored in the shift register; and a control section that shifts the data stored in the shift register by a predetermined amount in two directions and controls input and output of the input section and the output section. It is characterized by

(Function) When different types of data are input to the shift register, this data is shifted by a certain amount in one direction, and a predetermined amount of data is output from the output section.

Next, the data stored in the shift register is shifted in the opposite direction to output a predetermined amount of data from the output section. In this way, necessary data can be output first and then different types of data can be output.

This eliminates the need for a plurality of shift registers, subtracters, etc. as in the prior art, and allows processing to be performed using only one shift register.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a configuration diagram according to a first embodiment of the present invention. The digital signal processing circuit shown in the figure includes an 8-bit shift register 17a, a 9-bit shift register 17b, an input terminal group 19, an input terminal group 21, a gate group 23, a gate group 25, an output terminal group 27, and an output terminal group. 29, consists of flip-flops 31.33. The shift register 17a inputs and stores data input from the input terminal group 19 and the gate group 23 when the data set signal is on. The signal stored in the shift register 17a, which shifts data using the shift clock signal, is output from the output terminal group 27.29.

The shift register 17b inputs and stores data input from the input terminal group 21 and the gate group 25 when the data set signal is on. A flip-flop 3 shifts data using a shift clock signal.
1 detects that the 8th bit P of the shift register 17b becomes zero. The flip roller 133 detects that the 9th bit Q of the shift register 17b becomes zero.

Next, the operation of this embodiment will be explained based on FIGS. 2 and 3. FIG. 2 shows the contents of data stored in shift registers 17a and 17b. Figure 2(a)
shows the state when data is input to the shift registers 17a and 17b. That is, shift register 17
a1 through one input terminal group and gate group 23.
When the data ~a1, b1~b4 are input and the data set signal is turned on, the data a1~a4, b1~b4 are stored in the shift register 17a, as shown in FIG. 3 (a>).

Bit shift data is sent to the shift register 17b via an input terminal group 21 and a gate group 25. Then, the bit shift data is stored in the shift register 17b when the data set signal is turned on (FIG. 3(a)).

This bit shift data indicates the shift amount of the input signal input to the shift register 17a. This is the data that causes bits to be shifted. That is, bit shift data in which all bits below the fifth bit of the shift register 17b are 1'' is set.

When the setting of the data shown in FIG. 2(a) is completed, the data is shifted in synchronization with the shift clock signal (FIG. 3(b)). That is, data is sent one bit at a time in the direction of arrow X. For example, the data of the first bit A of the shift register 17a is sent to the second bit B. Further, the data of the eighth bit H of the shift register 17a is sent to the first bit H of the shift register 17b. Furthermore, the data at the 9th bit Q of the shift register 17b is sent to the 1st bit A of the shift register 17a.

When such a shift is repeated for 4 bits, the 8th bit P of the shift register 17b becomes nO'', which is detected by the flip-flops 31 and 33, and the shift clock control signal is turned on (FIG. 3(d)).Shift clock When the control signal turns on, shift register 1
Data from the fifth bit E to the eighth bit H of 7a is output from the output terminal group 29. This output terminal group 29
The output data corresponds to the output signal from the quantization section 7 shown in FIG. When the data from the 5th bit to the 8th bit is output, the subtraction set signal is turned on (Fig. 3(C)), and the data is output from the 6th bit F to the 8th bit H of the shift register 17a. is input. Then, data 0'' is input to the fifth bit E.

When such data is set and a shift clock signal (FIG. 3(b)) is input, the data is shifted in synchronization with this signal. In this case, data is shifted in the opposite direction Y, that is, to the upper side. data shift is 5
When the bit is executed, the 9th bit Q of the shift register 17b becomes 0'', the flip-flop 33 is cleared and the shift clock control signal is turned off. When the shift clock control signal is turned off, the data of the shift register 17a is transferred to the output terminal. The data is output from the group 27. This data corresponds to the correction data input to the de-emphasis 13 shown in FIG.

In this way, this embodiment uses a single shift register to perform the same functions as the conventional example shown in Fig. 5, so the circuit scale can be smaller than the conventional one, the circuit wiring can be simplified, and it is resistant to external noise. can be taken as a thing.

FIG. 4 shows a second embodiment of the present invention, which is characterized in that shift registers 17a and 17b are separated. That is, the data is transferred to the shift register 17a.
, 17b. Further, in this embodiment, even if the shift configuration on the shift register 17b side is changed, the same function as in the first embodiment can be achieved by shifting the bit shift data on the shift register 17a side.

[Effects of the Invention] As described in detail above, according to this embodiment, it is possible to provide a digital signal processing circuit with a small circuit scale, simple wiring, and strong resistance to external noise.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a digital signal processing circuit according to a first embodiment of the present invention, FIG. 2 is a diagram showing the operation of the first real/male side,
FIG. 3 is a signal waveform diagram of the first embodiment, FIG. 4 is a block diagram of the second embodiment of the present invention, and FIG. 5 is a block diagram of the conventional example. 17a, 17b...Shift register 19.21...Input terminal group 27.29.
......Output terminal group 31.33...
...Flip-flop applicant
Toshiba Corporation Representative Patent Attorney Satoshi Suyama - ((:1) (t)) (C) (d
)Figure 2

Claims (2)

[Claims] (1) a ring-shaped shift register, an input section that inputs data to the shift register, and an output section that outputs the data stored in the shift register;
A digital signal processing circuit comprising: a control section that shifts data stored in the shift register by a predetermined amount in two directions and controls input and output of the input section and the output section. (2) When different types of data are input from the input section, the control section shifts the data in the shift register by a certain amount in one direction, outputs a predetermined amount of data from the output section, and then changes the data stored in the shift register. 2. The digital signal processing circuit according to claim 1, wherein the digital signal processing circuit shifts a predetermined amount in a reverse direction to output a predetermined amount of data from an output section.