JPH0531852B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital-to-analog converter (hereinafter referred to as a D/A converter), and particularly to a charge redistribution type D/A converter. One type of D/A converter for converting a binary digital signal of a predetermined number of bits into an analog signal is a so-called charge redistribution type converter. FIG. 1 is a circuit block diagram of an example of a D/A converter using this charge redistribution method, in which first and second capacitors C 1 and ₂ of equal capacitance are connected at one end to a predetermined reference potential point (for example, ground). _C2 is provided, and control of charging and discharging of these capacitors, etc. is performed by on/off operations of switch elements 1 to 3. Specifically, a switch 1 is provided to control the charging of the capacitor _C1 , and a switch 2 is provided to control the redistribution of the charge charged in the capacitor _C1 to the capacitor _C2 . A switch 3 is provided to discharge and reset the charge of the capacitor _C1 , and each of these switches 1 to 3 outputs control signals B to D generated from the control circuit 5 in response to the digital input signal A. The on/off control is performed by the respective on/off controls. The charge charged in the second capacitor _C2 at the end of a series of predetermined bits of the digital input signal is sampled and held in the sample and hold circuit 4, and the hold output becomes an analog signal corresponding to the digital input signal. 2 and 3 are diagrams showing the timing of control signals B to D with respect to digital signal A in the circuit of FIG. 1. FIG. 2 shows the case where the predetermined bit of the digital input signal A is "1", and FIG. 3 shows the case when the predetermined bit of the digital input signal A is "0". Referring to FIG. 2, when the bit code of the input signal is "1" as shown in FIG. During this time, the capacitor C ₁ is charged to have an electric charge of Q ₁ =C ₁ ·V (1). Note that V is a charging voltage. After that, the control signal C becomes high level for a predetermined period of time, turning on the switch 2. At this time, if the capacitor C 2 has already been charged with a charge Q′ ₂ , the new charge Q _{2 in the capacitor C 2 due} to redistribution by turning on the switch ₂ becomes Q ₂ = {C ₂ / (C ₁ +C ₂ )}・(Q′ ₂ +C ₁ V)……(2). After that, the control signal D becomes high level, the switch 3 is turned on, and the capacitor _C1 is discharged and reset. Next, referring to FIG. 3, when the bit code of the input signal is "0" as shown in FIG.
Since remains at a low level, switch 1 remains off and capacitor C ₁ is not charged.
Next, the control signal C goes high for a predetermined period, turning on the switch 2 and redistributing the charges. The charge on the capacitor C ₂ at this time is Q ₂ = {C ₂ /(C ₁ + C ₂ )}·Q′ ₂ ……(3). Thereafter, the control signal D goes high, turning on the switch 3, and the capacitor _C1 is discharged and reset. Now, if the input digital signal A is a k-bit signal (k is a natural number), the second
Each of the control signals B to D is generated from the control circuit ₅ using the procedure explained using _FIG . It is held in the sample hold circuit 4. This hold output becomes an analog signal corresponding to the digital input signal. Using the above equations (2) and (3), the charge Q ₂ resulting from the finally obtained k-bit digital signal is expressed by the following equation. Q ₂ = _k 〓 ⁱ⁼¹ Q ₁・Z _i {C ₂ / (C ₁ + C ₂ )} ^k-i+1 ...(4) Here, Zi is 1, it is defined as 0 when it is “0”. What Equation (4) means is that the charge charged in capacitor C ₂ by the i-th bit gradually decreases in a geometric series of C ₂ / (C ₁ + C ₂ ) times every subsequent 1-bit operation. That's what I'm going to do. Now, Q ₁ is a constant determined by C ₁ and V, so under the ideal state of Q ₀ and C ₁ = C ₂ , equation (4) becomes Q ₂ = Q _0k 〓 ⁱ⁼¹ Zi・( 1/2) ^k-i+1 ...(5), and an analog signal is obtained from the output of capacitor _C2 . The above is an ideal case where C ₁ = C ₂ , but in reality there is an error in the capacitance values C ₁ and C ₂ , so C ₁ = (1-β)C ₀ , C ₂ = (1+
β) Let's consider it as C ₀ . Note that 0<β<1. In equation (4), by substituting C ₁ and C ₂ above, Q ₂ = (1-β) C ₀ V _k 〓 ⁱ⁼¹ Z _i (1+β) ^k-i+1・(1/2) ^{k- i+1} = (1-β ² ) C ₀ V _k 〓 ⁱ⁼¹ Z _i (1+β) ^ki・(1/2) ^k-i+1 ……(6). Comparing equation (5), which is an ideal form, and equation (6), which takes into account the error, the constant difference of (1-β ² ) is unrelated to linearity in absolute value, and if this is ignored, we get 〓 The term (1+β) ^ki in the term is defined by Z _i and may or may not exist, and the term (1+β) ki in the term is defined by Z i and may or may not exist.
β) may vary in magnitude, resulting in a deviation from the ideal type, resulting in distortion and noise. Here, if we consider the standardized deviation E, E= _k 〓 ⁱ⁼¹ Z _i・ΔE _i = _k 〓 ⁱ⁼¹ (1/2) ^k-i+1・{(1+β) ^ki −1}... …(7), and the deviation ΔE _i when the i-th bit operates up to the final k-th bit is ΔE _i = (1/2) ^k-i+1・(Aβ+Bβ ² +…)… …(8) becomes. Here, if β≪1, terms larger than ^β2 can be ignored, so ΔE _i = (1/2) ^k-i+1 ·Aβ ...(9). Table 1 shows the values obtained from equation (9). In Table 1, the maximum distortion is when Z _i is all “1”.

[Table] Let us consider β under the condition that it does not exceed the minimum unit. The minimum unit for each bit number of k = 4, 8, and 16 is (1/2) ⁴ (1/2) ⁸ and (1/2) ¹⁶ , so each value is the maximum distortion.
Assuming that 0.688β, 0.965β and 1・β do not exceed, the tolerance of β is 0.0909, 0.004 and 0.004, respectively.
Calculated as 0.000015. Since the difference between capacitors C ₁ and C ₂ is 2β, this difference is up to 18% for 4 bits and 0.8 for 8 bits.
% respectively are allowed. However, in 16 bits
Only 0.003% is allowed, so even if a capacitor could be manufactured with an error of 0.1%, it would only be possible to realize a D/A converter of about 10 bits. FIG. 4A is a diagram showing an example of analog output distortion caused by a difference in the capacitance values of capacitors C ₁ and C _2. Curve 20 shown by the solid line is the true analog value, and curve 21 shown by the dotted line is the true analog value. This is the analog output of the D/A converter with distortion. Note that T ₀ indicates the sampling period. In this way, it is known that the analog output level corresponding to each sampling value deviates from the true analog level in only one direction (in the positive direction in the figure), and that the deviation width differs for each sampling value and is not constant. This deviation results in output distortion. FIG. 4B shows the deviation of the analog output level for each sampling value, that is, the error component. In order to correct this error component, for each digital signal corresponding to each sampling value, the roles of capacitors C ₁ and C ₂ are switched to perform the same operation as described above.
A possible method is to perform two analog conversion operations and add both analog outputs. In this case, in the second operation, the true analog value deviates only in the negative direction, as shown in Figures 5A and B, and the width of the deviation is the same as that in the first operation shown in Figure 4. Since they are the same, by adding the analog outputs obtained from both operations, the error components cancel each other out and an accurate analog signal can be obtained. However, this method requires two control operations for the same digital signal, making the control complicated and increasing the conversion time. An object of the present invention is to provide a highly accurate D/A converter that reduces output distortion due to the difference in capacitance between two capacitors without increasing conversion time. The digital-to-analog converter according to the present invention comprises:
first and second capacitors; control means for controlling charging and discharging of the first and second capacitors according to a digital input signal of a predetermined number of bits supplied at each sampling period; An electric redistribution type digital signal having an output means for deriving an analog signal according to the charged charge.
In the analog converter, the control means charges the first capacitor according to the bit content for each bit of the digital input signal, and then distributes the charged charge of the first capacitor to a second capacitor. a first capacitor for discharging the first capacitor;
for each bit of the digital input signal, charging the second capacitor according to the bit content, then distributing the charged charge of the second capacitor to the first capacitor, and then distributing the charge of the second capacitor to the first capacitor;
A second control for discharging the capacitor is performed by switching alternately at each sampling period, and the output means samples and holds a voltage output across the second capacitor obtained by the first control. The low-pass filter receives as input a voltage signal obtained by sampling and holding the voltage signal obtained by the second control and the voltage output across the first capacitor obtained by the second control, and outputs an analog signal. The present invention will be explained below using the drawings. FIG. 6 is a circuit block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same symbols. In this example, in addition to the circuit configuration shown in FIG. 1, charge/discharge switches 6 and 7 for the second capacitor C ₂ and a second hold circuit 8 that samples and holds the output corresponding to the charge of the first capacitor C ₁ are added. The hold outputs of both hold circuits 4 and 8 are selected by an output selection switch 9 and outputted via an LPF (low pass filter) 11. Also in the control circuit 10 in this example, control signals B to D and B',
D′ is generated respectively, and the signal
Switches 6 and 7 are controlled on and off by B' and D', respectively. Further, sample pulses for the hold circuits 4 and 8, control signals for the switch 9, etc. are also generated from the control circuit 10. In this configuration, for each bit of the k-bit digital input signal A, the bit contents shown in FIGS. 7 and 8 are
Control signals B to D as shown in the figure are sequentially generated and switches 1 to 3 operate accordingly. This is the same operation as the conventional example shown in Fig. 1.
The timing waveform is exactly the same as the one shown in the figure. When the above operations are completed for all bits, the second capacitor _C2 has been charged with the charge _Q2 shown in equation (6), so this is sampled and held in the hold circuit 4. For the k-bit digital signal A that is subsequently input, each switch operates at the timing shown in FIGS. 9 and 10. That is, when the predetermined bit of the digital signal is "1", as shown in FIG. 9, the control signal B' becomes high level, the switch 6 is turned on, and the second capacitor _C2 is charged. Thereafter, the control signal C becomes high level, turning on the switch 2, and the charge is distributed. Then, the control signal D' becomes high level, the switch 7 is turned on, and the capacitor _C2 is discharged and reset. Next, referring to FIG. 10, if the bit of the input signal is "0" as shown in FIG.
Since B' remains at a low level, switch 6 is off and capacitor _C2 is not charged.
Next, the control signal C goes high, turns on the switch 2, and charges are distributed. Thereafter, the control signal D' becomes high level, the switch 7 is turned on, and the discharge of the capacitor _C2 is reset. These operations are performed sequentially, and when the k-th bit operation is completed, the hold circuit 8 closes the first capacitor.
A signal corresponding to the charge on _C1 is sampled and held. The hold output thus obtained is selected and derived by the switch 9. In this way, the functions of the first and second capacitors are alternately switched and operated for each digital signal obtained by sampling the analog signal, and the outputs of these capacitors are alternately selected by the switch 9. and apply it to LPF11, and this
The above object of the present invention is achieved by making the output of the LPF 11 an analog signal. FIG. 11 is a diagram showing the relationship between the analog output and error at the output terminal of the switch 9 (input terminal of the LPF 11) obtained in this way, where the solid line curve 20 in A is the true analog value, and the dotted line curve 20 is the true analog value. 21
is the analog output obtained by the circuit system shown in FIG. The error component waveform is shown in Figure B.
The frequency component of this error waveform has 1/2 of the sampling frequency ₀ (1/T ₀ ) as a fundamental wave. Therefore, if the LPF 11 is an ideal filter that blocks components of _0/2 or more, the error component will almost disappear, but in reality, the characteristics of the LPF are not ideal. Therefore, if the sampling frequency when sampling and digitizing the original analog signal is set high enough,
The LPF 11 makes it possible to completely remove error components having a fundamental wave of _0/2 . Considering the magnitude of the error component below, if the capacitor _C1 is charged and the charge is distributed to the capacitor _C2 in the same way as in the conventional example, and the output is obtained from the capacitor _C2 , this output will be It is shown in equation (6), and its error component is shown in equation (9). On the other hand, when the functions of capacitors C ₁ and C ₂ are reversed to obtain an output from capacitor C ₁ , this output is Q ₁ = (1-β ² ) C ₀ V _k 〓 〓 ⁱ⁼¹ {1−(−1) ^ki・β} ^ki・(1/2) ^k−i+1 ……(10
) becomes. Therefore, the standardized deviation E is E= _k 〓 ⁱ⁼¹ Z _i・ΔE _i = _k 〓 〓 ⁱ⁼¹ (1/2) ^k-i+1・[{1−(−1) ^ki・β } ^ki −1
]...(12), and if we ignore terms larger than β ² , ΔE _i = (-1) ^k-i+1・(1/2) ^k-i+
1・A′・β……(13) The values of each error component in the case of k=16 obtained by equations (10) and (13) are standardized by β (as 1/β) and are shown in Table 2. In order to further reduce the error component in the method shown in the present invention, if an extra "0" bit is added to the most significant bit of the digital input signal and the above operation is performed, each bit becomes 1. Since the bits are shifted to the lower digits, the analog output level becomes 1/2, but the standardized error component is (-1) ^k-i+2・(1/2) ^k-i+2 -A', and when calculated, it is reduced to 1/4 compared to the case where no additional "0" bit is added, so the S/N is doubled, making it possible to improve the S/N.

【table】

Claims (1)

[Scope of Claims] 1: first and second capacitors; control means for controlling charging and discharging of the first and second capacitors according to a digital input signal of a predetermined number of bits supplied at each sampling period; A charge redistribution type digital-to-analog converter having an output means for deriving an analog signal corresponding to the charge in the first and second capacitors, wherein the control means outputs an analog signal corresponding to the charges of the first and second capacitors, , charging the first capacitor in accordance with the bit content thereof, distributing the charge of the first capacitor to a second capacitor, and then discharging the first capacitor.
for each bit of the digital input signal, charging the second capacitor according to the bit content, then distributing the charged charge of the second capacitor to the first capacitor, and then distributing the charge of the second capacitor to the first capacitor;
A second control for discharging the capacitor is performed by switching alternately at each sampling period, and the output means samples and holds a voltage output across the second capacitor obtained by the first control. The digital filter comprises a low-pass filter that receives as input a voltage signal obtained by sampling and holding the voltage signal obtained by the second control and the voltage output across the first capacitor obtained by the second control, and outputs an analog signal. analog converter.