JPS63244246A - Wrap-around detector - Google Patents

Abstract

PURPOSE:To detect wrap-around at a high speed by generating the logical product of the output of an adder to add a two-bit instruction data with an address data in a memory and that of an all-'1' detection means. CONSTITUTION:The titled detector are provided: with the adding means 10 to add two-bit instruction data instructing the size of memory data with an address data in the memory, and the all-'1' detection means 20 to detect whether all the high-order bits except the low order 2 bit of the address data or not. And further, the AND gate 30 to generate the logical product of the outputs of the means 10 and the means 20. As a result, 2 bit data in a memory data field and an address data are added together; in case said adding results in '1' and all the high order bits except the low order 2 bit of the address data are in '1', the occurrence of wrap-around in the memory can be detected swiftly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to Hra that detects the occurrence of so-called wraparound in a memory.

(Conventional technology) First, an overview of wraparound will be explained.

The wraparound mentioned here has the following function. When 32-bit data is accessed byte by byte using a 32-bit address line in memory access, the address-to-data configuration is as shown in FIG. 2. That is, 32-bit data is divided into four parts, and memory access is performed in units of bytes.

This means that the start address of memory access can be freely set for each byte. Therefore,
In FIG. 2, memory access can be started from any part of the 32-bit data divided into four parts.

The area is divided into four areas, respectively, areas A, B, and C.

Assuming O, if the lower 2 bits of the 32-bit address are "00", it is area A, and "01" is area B1.
"10" indicates the area 01"11", and the address can start from any area A to D.

In the above memory configuration, the memory data size handled is in bytes (8 btt) and words (8 btt), respectively.
16 bits) and double word units (32 bits), memory access becomes complicated. FIG. 3 shows the relationship between the start address of this memory and the range to be accessed depending on the size of memory data. The figure (A) shows the relationship between each address start address and the data size in bytes, the figure (B) shows the relationship between the address start address and word data, and the figure (C) shows the relationship between the address start address and double word data. Shows data relationships.

As can be seen from these relationships, memory access may straddle two boundaries depending on the address start address and data size. In other words, a situation arises in which it is necessary to access addresses n and n+1. - As an example, in Figure 3 (A), if the start address is 8 areas and the data size is double word, three areas B, C, and D are accessed at address n, and the AI area is further accessed at address n+1. .

In this way, when accessing memory, the address must always be determined taking into account the data size. Therefore, it is necessary to calculate the address by adding the data size to the current address.

At this time, address modification is performed by calculating addresses in the range from 0 to 0 to 1 to 1 (each having a length of 32 bits) on a 32-bit address line.

In that case, the lower 2b1 of the 32-bit address is 3
Since addressing is performed in byte units obtained by dividing 2 bits into 4, the data size for each byte is added to the current address, and when determining the limit address for memory access, the data size can be added to the lower 2 bits of the address.

This method is shown in FIG. In other words, add "01" for byte data, "11" for 10n1 double word data. As a result of this addition, all addresses are "1", that is, the address exceeds the maximum address. Then, a decrease again starts from the o-otl point. This is usually said to have occurred as a wraparound. FIG. 5 shows a situation in which a wraparound has occurred.

Conventionally, the circuit for detecting the above wraparound is as follows:
The devices shown in FIGS. 6 and 7 are known.

In the conventional example shown in Fig. 6, 2 bits of the data size are added to the current 32-bit address using a 32-bit adder, and at that time, the occurrence of wrap-around is determined based on the result of whether a carry occurs from the most significant digit. Detected.

Note that when adding the data size, the lower 2 bits indicate the data size, and the remaining 3Qbits are all “0”.
Then, perform the addition.

Further, in the embodiment shown in FIG. 7, the lower 2 bits are added to the current address, and in the 2nd to 31st bits m, the carry from the lower order and the current address are ANDed, and the output is transmitted to the higher order. The presence or absence of a wraparound is detected based on the presence or absence of a carry from the most significant digit.

(Problems to be Solved by the Invention) As described above, the conventional wrap-acland detection circuit shown in FIG.
A 32-bit adder is required to add only t, which increases the amount of hardware and has the disadvantage that it takes a long calculation time because carries propagate.

In addition, in the case shown in FIG. 7, the circuit system takes the AND of the current address and the carry from the lower order instead of the adder for 2 to 31 bats, so although the hardware is reduced, the 2 to 31 Since the carry propagates to the bit fill, the computation time is long.

The present invention has been made in view of the above problems, and an object thereof is to provide a device that has a simplified device configuration and can detect the occurrence of wraparound at high speed.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an adding means for adding 2-bit instruction data indicating the size of memory data and address data of the memory. , all "1" detection means for detecting whether or not the upper bits except the lower two bits of the address data are all "1", and the logical product of the addition means and the all "1" detection means; It is characterized by detecting the occurrence of memory wraparound.

(Function) In the present invention, two bit data and address data in a memory data field are added, and the addition result is "1".
If all the upper bits except the lower two bits of the address data are "1", it is quickly detected that wraparound has occurred in the memory.

(Example) FIG. 1 shows the configuration of a wraparound detection device according to the present invention.

This embodiment is composed of a lower 2 bttm trigger section 10, an all "1" detection section 20, and an AND gate 30.

The lower 2 bits 2IO sieve unit 10 selects the lower 2 bits of the address.
It adds t and 2 bits of the data size field, and when the data size is "byte", it is "01".
, "1o" is added to the address for "word", and 11" is added for "double word" to the address. The result of the addition is output to the AND gate 30. Note that,
In the figure, FA indicates a full adder and HA indicates a half adder.

On the other hand, the all “1” detection unit 2o has addresses 2b+t to 3.
It detects whether all 1 bits are "1" or not, and current address 2 bat to 31 bits are input in parallel.
It consists of Nantes gates 21, 22, and 23, and a NOR gate 24 that inputs the output of the Nantes gates 21, 22, and 23.

Next, the action will be explained.

□ The lower 2 bits of the 32-bit address of bat~3 i bits are added to the data size "01", "10", or "11" by the lower 2-bit adder 10. The carry output is then supplied to the AND gate 30.

・On the other hand, the all “1” detection section detects 2 bits of the current address.
It is detected that all 30 bits of 31 bits are "1". Therefore, even if i btt is “0” during 30 btt
'' exists, the output of any of the Nant gates 21, 22, 23 becomes "1" and the output of the Nant gate 24 becomes "0".
”.

When the 2nd to 31st bits of the address are all 1, the outputs of the Nantes gates 21, 22, and 23 are all 0. Therefore, the output of the Nantes gate 24 is 1.

Then, the AND gate 30 calculates the logical product of the output of this all "1" detection section, that is, the output of the Nant gate 24, and the carry output of the lower 2 bits 2IO1la.

The output of Nant gate 24 is “1” and the carry output is “0”
In this case, it can be seen that wraparound has not yet occurred.

Then, when the re-output reaches "1#", the output of the AND gate 30 becomes "1", and it is thus detected that wraparound has occurred.

As described above, according to this embodiment, the carry of the addition result of the lower 2b1 is propagated, and whether or not a carry occurs from the final stage is determined by the lower 2b1 if the 2nd to 31st bits are "1".
The carry of the addition result of it is transmitted, and anything other than all "1" is not transmitted. The all "1" detection between bits 2 to 31 is logically ANDed with the lower 212 bits, and the output is used to determine the presence or absence of a crossover, that is, the presence or absence of wraparound, so the all "1" detection unit 20 detects 3Q bits at once. This makes detection faster.

Additionally, the hardware can be relatively small-scale.

Even with the conventional method shown in Figure 7, which requires a relatively small amount of hardware, an AND gate is required for each bat between 2 and 31 bits, and 66 transistors are required for the total number of 2 to 31 bits. -18
0 pieces were required, but in this embodiment, about 120 pieces between 2 and 31 bits are required, so '5Ar11 can be constructed at low cost.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a wraparound detection device that can detect the occurrence of wraparound at high speed and has a simplified device configuration at a low cost.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment of the li device according to the present invention;
The figure is an explanatory diagram showing the relationship between addresses when 32-bit memory data is divided into bytes, and Figure 3 shows the start address of memory access when the memory is divided into bytes,
An explanatory diagram showing the relationship with memory access areas according to data size, FIG. 4 is an explanatory diagram of the addition method according to the data size to be added to the current address, FIG. 5 is an explanatory diagram of wraparound occurrence, and FIGS. 6 and 7 The figure is a configuration diagram of a conventional example. 10...Lower 2 bit addition section 20...All "1" detection section 30...AND gate

Claims (1)

[Claims] Addition means for adding 2-bit instruction data indicating the size of memory data and address data of the memory, and whether all upper bits of the address data except the lower 2 bits are "1". 1. A wraparound detection device comprising: all "1" detection means for detecting whether the addition means and all "1" detection means are present;