JPS632419A - Pseudo noise code generation circuit - Google Patents

Abstract

PURPOSE:To output plural codes having less interrelation with each other from a single circuit and, at the same time, to change the output periods repeatedly, by selecting each-stage output of a shift register by using select signals outputted from a decoder in accordance with a stage-number setting input. CONSTITUTION:The 1st-i-th selecting sections 3-1-3-i select plural outputs of each stage of a shift register in accordance with select signals outputted from a decoder 3 in corresponding to a stage-number setting input. Each selecting section is composed of a prescribed number of sets of NAND gates for outputting one or plural PN (pseudo noise) codes having different phases out of the outputs of the register 1 and a prescribed number of NAND gates for collecting the output of each set. A prescribed number of outputs selected by each selecting section are inputted to arithmetic sections 4-1-4-i and addition is performed by means of an NAND gate and its succeeding NAND gate. Therefore, plural codes (1st-i-th PN codes) having less interrelation with each other can be outputted from a single circuit and the period can be changed repeatedly.

Description

[Detailed Description of the Invention] [Summary] When generating a PN code of arbitrary length with one PN code generation circuit, by providing a selection section and an operation section that are extracted by two stages of NAND gates, A small-scale and high-speed PN code generation circuit can be achieved.

[Industrial application field]

The present invention relates to a circuit for generating pseudo-noise (PN) codes.

In a digital inorganic transmission system, when an intermediate station detects a loss of the received signal from the previous station, if the carrier wave is sent to the downstream station without modulation, the downstream station will also receive an abnormal reception, so it is modulated with a PN code. In some cases, PN codes are used to transmit signals to prevent reception abnormalities at subsequent stations.Also, in order to obtain a flat spectrum within the band in various tests, PN codes are sometimes used.
When transmitting a plurality of bits in one time slot as in multilevel QAM, it is necessary to select a pattern in which each bit has little correlation.

[Problems to be solved by conventional technology and invention] Conventionally,
Since separate PN code generation circuits were used to obtain a pattern in which each bit has little correlation, there was a problem that the hard bottom became harsh. Furthermore, since each system requires a different repetition period of the PN code, it is necessary to design a separate PN code generation circuit for each system, resulting in an increase in cost.

Therefore, it is an object of the present invention F1 to obtain a PN code generating circuit in which a plurality of outputs having little correlation with each other can be obtained from one PN code generating circuit, and in which one repetition period is variable, in a simple circuit tank.

[Means for solving problems]

FIG. 1 is a diagram showing the basic configuration of the present invention. 1 is a shift register, which stores a value that is the basis of the PN code. 2
is a decoder, which outputs a selection signal according to the stage number setting input. 3-1 to 3-1 are the first to first selection parts,
Depending on the selection signal, one or a plurality of PN codes (first
~ith PN code)), and a predetermined number of NAND gates that combine the outputs of each set. 4-1～
4-1 are first to first calculation units, respectively.
N in the previous stage that outputs "0" for each combination in which an odd number of "1"s are present among the predetermined number of outputs selected by the selection section.
The AND gate and the subsequent NAND gate inputting all of the outputs for the combination perform all additions modulo 2 and output the rL first to first PN codes, respectively.

[Effect]

A maximum period sequence (M sequence) is generally used as a PN code. The M-series pulse is a pulse train with a period of 2n-1 bits, excluding all zero sequences, and is expressed by the characteristic polynomial b (7=x”
+xm+...+xO=0 (n>m) This can be realized relatively easily. In addition, 1m is x.

(indicates the input of the shift register) 0 indicates a pulse train with a phase delayed by 100 bits. Specifically, the output of the final stage of an n-stage shift register (corresponding to the xn term) and the output of at least one of the intermediate stages. (addition modulo 2 with n corresponding to the term xTn (in the case of two people, it becomes exclusive OR)), and input to the first stage at the next timing (corresponding to the term xO) It can be obtained by

If the period of the pulse train obtained in this way is long enough, the same pulse train obtained by being delayed by a period obtained by dividing the period into approximately equal parts will have little correlation with each other. Therefore, in order to obtain a plurality of pulse trains with low correlation to each other from one PN code generation circuit, the above-mentioned n
In addition to the output of the PN code generation circuit using the stage shift register, all the shift register roles may be made into a 2n-1 stage shift register, and the output may be output at every predetermined stage.

However, since the 2n-1 stage shift register is a very thick Hiko circuit, the output f! is equivalent to the output of a predetermined stage of the 2n-1 stage shift register. : It can be obtained by adding the outputs of a plurality of predetermined stages of an n-stage shift register modulo 2. The following shows how this is possible.

When the above-mentioned characteristic polynomial is transformed, x''=x''+−−+xO. Also, the process corresponding to the output of 1 stage (7I>n) is X A! == X n * z J−n= (xm+
-=・+xO) ・x'-n:xl-(n-m)+,,
, , +xJ-n, the order can be reduced.

In this way, it is possible to transform the polynomial into a polynomial whose maximum degree is less than n, so the output of one stage can be obtained with equal constraints by adding modulo 2 the predetermined outputs of up to n stages. become. The combination of taking at least one of the outputs of each stage of the n-stage shift register is 2n-1.
Furthermore, since the period of the output PN code is 2n-1, it can be seen that these combinations and 2n-1 phases have a one-to-IK correspondence. Also, even with a combination of a small number of outputs, such as 2 to 4, a relatively large number of PN codes with almost random phases can be obtained, so these combinations can generate PN codes with a phase that divides one period almost equally.
N codes can be obtained.

Also, if you use the outputs from the first stage to the stage (k<n), it becomes 2 -
A PN code with one period (length) can be obtained, and in this case also, PN codes with a plurality of phases can be obtained by adding modulo 2 the outputs of appropriate stages. In order to select the length of the PN code, rather than generating PN codes of various lengths and selecting one of them, it is better to select the human power used for addition using the 2t-method. For example, only one circuit is required for this operation, and it can be realized with a simple circuit.

- On the other hand, when integrating, NAND gates are easy to make and operate at high speed, so the selection of the output of each stage of the shift register and the addition modulo 2 are each configured with two stages of NAND gates. FIG. 2 shows five examples of the problem II of the present invention, and FIGS. 3 to 8 show specific circuit configuration diagrams of each block.

In FIG. 2, the shift register 11 is the shift register 1 of FIG. 1, the decoder 21 is the decoder 2, and the first to eighth selection units 31 to 38 are the first to first selection units 3-1 to 3-1
The first to eighth arithmetic units 41 to 48 correspond to the first to first arithmetic units 4-1 to 4-1, respectively.The switching circuit 12 switches the input to the shift register 11, and It is possible to input signals of
Applications such as enabling necessary code self-synchronization in an error rate measuring circuit using a PN code are possible.

FIG. 3 is a bottom diagram of the circuit 1s of the shift register 11.
7 lip 70 knobs for 5 roles (FF) 11-1 to 11-15
The signal input to the flip-flop 11-1 is sequentially moved to the next flip-flop in accordance with the clock. Further, the outputs of each stage are led out in parallel.

The period of the PN code is given by 2n-1, where n is the number of stages of the base shift register. In order to obtain the PN code of this period, the crotch output of the shift register that is input to the arithmetic unit is determined, and when n is determined, a certain number of combinations are determined. The fewer the number of connections, the better. Table 1 shows an example of the crotch output that should be connected when n=3 to 15. The gate outputs a selection signal that becomes @l'' only on a predetermined signal line.

FIG. 5 shows the configuration of the first selection section 31, which selects the crotch output using two stages of NAND gates in accordance with a selection signal corresponding to the set number of stages nVc. The NAND gate at the front stage is configured to enable the + of the necessary four or less outputs among the outputs of each stage of the shift register according to the selection signal from the decoder, and the NAND gate at the rear stage is configured to enable the positive outputs according to the selection signal from the outputs of each stage of the shift register. Collectively, each of the four sets of outputs that can be
- 4 outputs (A, B, C, D) to be added modulo
Output as . Since the selection section employs a NAND-NAND configuration, the speed can be increased.

FIG. 6 is a circuit diagram of the first arithmetic unit 41, which is composed of an inverter and two stages of NAND gates. The inverter is provided to obtain inverted outputs of the four forces (A, B, C, D) to be calculated. The first stage NAND gate is 11
``Detects that there is an odd number of inputs. In other words, 4 people (
If the number of inputs that are 1" among A, B, C, and D is an odd number, one of the NAND gates will output all @0", and the other seven NAND gates will output @1. ” is output.

Furthermore, if the number of 11'' out of the four manpower is an even number, all NAND gates output "1".

The second-stage NAND gate inputs all the outputs of the first-stage NAND gate, and outputs 11' when any of them is θ'', that is, when an odd number of the four outputs is 11'', and 4 When an even number of the human forces are "1", "O" is outputted.As a result, 2t-method addition of 94 human forces is performed.

Normally, when performing addition modulo 2 for 4 manpower,
After taking the exclusive OR (EX-OR) by two people,
This is done by further EX-ORt-ing the two outputs, but EX-ORK requires multiple stages of gates and OR gates, so the disadvantage is that the calculation is slow because it requires multiple stages of gates in total. There is.

However, in this embodiment, only two stages of NAND gates are required, and the speed can be increased.

FIG. 7 shows the configuration of the synchronization pulse detection unit 5, which outputs a positive synchronization pulse corresponding to a portion of n consecutive 11'' in the PN code.

Depending on the number of stages n, an extension section consisting of a NOR gate and an inverter is used to enable the stage after the specified setup, and a mask section consisting of an inverter and a NAND gate selects the output of the shift register and inputs it to the AND gate. to obtain the synchronization pulse.

Figure 8 shows the configuration of the all @O'' detection unit 6. When the shift register becomes all @O'', the PN code generation stops and startup is no longer possible, so this state is detected by an inverter and a NAND gate. Enables shift register presetting.

The PN code output from the first selection section and the first calculation section is 1
However, as described above, a communication device may require multiple sequences of PN codes with different phases.

As an example, a configuration will be described in which 8 series of PN codes having different phases of approximately 178 cycles are output.

Prior to explaining the second to eighth selection units 32 to 38 in FIG. 2, a method of generating PN with a phase difference will be explained using a 21s-1t example.

■　X”+X’+1=O holds true.

) (k is bit delayed from Xo. Using these two points, further according to the above rules, X = X"+1 X = X+1 X" = X'+1 X = X+1 X +1 x =x'+x"+i X =X +X +1 Xisu20 =X"+X"+X'+1X""=X'
It is based on the fact that +X'+1 X"" = X'+X"+1 holds true.

2 ” -1 = 178 cycles from 32767 is 4096
It is.

PNI;X'PN2;
X”93=X’+X’+X”PN4; X122
“Two x”+x’+x’+x’+x”PNs;
85=X'+X"PN6;X2048'=X"+X"+X'+X'
+X”PN7; X =X +X +XP
N8; Calculating unit input 'f: Consider setting it within 4.

PN4; X””’=X”+X’+X’+X’PN6
．． Although there is a deviation of 29 from the original phase for each of X - For each PN, by inputting the shift register output of the upper right numbered stage of X to the arithmetic unit, it is possible to generate a PN code having a phase difference of approximately 178 cycles.

Other combinations are possible by changing the phase of PNI or by slightly shifting the phases of PN2 to PN8 from the above.

215 We need to find a combination with a small value.

The first to eighth arithmetic units 32 to 38 have second arithmetic units corresponding to the PN code length.
-8 Selects the input to the calculation units 42 to 48,
Further, the first to eighth calculation units 41 to 48 all have the same configuration.

〔Effect of the invention〕

As explained above, when configuring a single PN code generation circuit to obtain a PN code of any length, the present invention uses a shift register by a selection signal output from a decoder in response to a stage number setting input. The outputs of each stage are selected and input to the arithmetic unit to obtain a PN code of a desired length. The selection section and calculation section each consist of two stages of NAND gates, allowing high-speed operation.] Also, since only one calculation section is required for one output, it is possible to simply use multiple PN gates with different numbers of stages. A configuration that selects and outputs the output of the code generator also greatly reduces the circuit scale, especially for LS.
Suitable for I.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a diagram of an embodiment of the invention, Figure 3 is a circuit diagram of a shift register, Figure 4 is a circuit diagram of a decoder, and Figure 5 is a selection section. 6 is a circuit diagram of the calculation section, FIG. 7 is a circuit diagram of the synchronous pulse detection section, and FIG. 8 is a circuit diagram of the total 10" detection section. is a shift register, 2 is a decoder, 3
-1 to 3-i are 1st to 1st selection part, 4-1 to main hit/l
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Claims (1)

[Claims] A shift register (
1), and a decoder (2) that outputs a selection signal according to the stage number setting input.
), among the outputs of each stage of the shift register (1), a predetermined number or less outputs required to generate one or a plurality of pseudo-noise codes each having a different phase are enabled based on the output of the decoder (2). one or a plurality of selections that perform a predetermined selection; Part (3-1 to 3-
i), and a pre-stage that outputs "0" for each of the combinations in which the number of "1"s is an odd number among the outputs of each of the one or more selection units (3-1 to 3-i); NAND gate and
A subsequent NAND that inputs all outputs for the combination.
A pseudo-noise code generation circuit comprising one or more arithmetic units that perform modulo-2 addition using a gate.